From 72bb4d79dcc8addf59e9ea513be059fce6edff9a Mon Sep 17 00:00:00 2001 From: Job Noorman Date: Thu, 15 Aug 2024 08:46:36 +0200 Subject: [PATCH] ir3/legalize: handle scalar ALU WAR hazards for a0.x It turns out that mova executes on the normal pipeline, which means that users of a0.x on the scalar pipeline might cause a WAR hazard with mova. Fixes: 876c5396a78 ("ir3: Add support for "scalar ALU"") Signed-off-by: Job Noorman Part-of: --- src/freedreno/ir3/ir3.h | 6 ++++++ src/freedreno/ir3/ir3_legalize.c | 2 +- 2 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/freedreno/ir3/ir3.h b/src/freedreno/ir3/ir3.h index 57c50e6ba78..e88a09f1293 100644 --- a/src/freedreno/ir3/ir3.h +++ b/src/freedreno/ir3/ir3.h @@ -1416,6 +1416,12 @@ is_reg_gpr(const struct ir3_register *reg) return true; } +static inline bool +is_reg_a0(const struct ir3_register *reg) +{ + return reg->num == regid(REG_A0, 0); +} + /* is dst a normal temp register: */ static inline bool is_dest_gpr(const struct ir3_register *dst) diff --git a/src/freedreno/ir3/ir3_legalize.c b/src/freedreno/ir3/ir3_legalize.c index fc66882038a..233f9eecdb8 100644 --- a/src/freedreno/ir3/ir3_legalize.c +++ b/src/freedreno/ir3/ir3_legalize.c @@ -647,7 +647,7 @@ legalize_block(struct ir3_legalize_ctx *ctx, struct ir3_block *block) * need to wait for previous ones. */ foreach_src (reg, n) { - if (reg->flags & IR3_REG_SHARED) { + if ((reg->flags & IR3_REG_SHARED) || is_reg_a0(reg)) { regmask_set(&state->needs_ss_scalar_war, reg); } }