From 43e9af713b134a893779fa0dbbb9720cfb402e0d Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Marek=20Ol=C5=A1=C3=A1k?= Date: Fri, 30 Jan 2026 13:48:35 -0500 Subject: [PATCH] radv: use DCC definitions more Reviewed-by: Samuel Pitoiset Reviewed-by: Pierre-Eric Pelloux-Prayer Part-of: --- src/amd/vulkan/meta/radv_meta_clear.c | 2 +- src/amd/vulkan/meta/radv_meta_fast_clear.c | 2 +- src/amd/vulkan/meta/radv_meta_resolve.c | 2 +- src/amd/vulkan/meta/radv_meta_resolve_cs.c | 2 +- src/amd/vulkan/radv_cmd_buffer.c | 6 +++--- 5 files changed, 7 insertions(+), 7 deletions(-) diff --git a/src/amd/vulkan/meta/radv_meta_clear.c b/src/amd/vulkan/meta/radv_meta_clear.c index a2ab2064049..c25ce1980dc 100644 --- a/src/amd/vulkan/meta/radv_meta_clear.c +++ b/src/amd/vulkan/meta/radv_meta_clear.c @@ -1981,7 +1981,7 @@ radv_cmd_clear_image(struct radv_cmd_buffer *cmd_buffer, struct radv_image *imag enum radv_cmd_flush_bits flush_bits = 0; for (unsigned i = 0; i < range_count; i++) { if (radv_dcc_enabled(image, ranges[i].baseMipLevel)) - flush_bits |= radv_clear_dcc(cmd_buffer, image, &ranges[i], 0xffffffffu); + flush_bits |= radv_clear_dcc(cmd_buffer, image, &ranges[i], DCC_UNCOMPRESSED); } cmd_buffer->state.flush_bits |= flush_bits; } diff --git a/src/amd/vulkan/meta/radv_meta_fast_clear.c b/src/amd/vulkan/meta/radv_meta_fast_clear.c index b4462fa2f7c..d7d31e62966 100644 --- a/src/amd/vulkan/meta/radv_meta_fast_clear.c +++ b/src/amd/vulkan/meta/radv_meta_fast_clear.c @@ -576,7 +576,7 @@ radv_decompress_dcc_compute(struct radv_cmd_buffer *cmd_buffer, struct radv_imag VK_ACCESS_2_SHADER_WRITE_BIT, 0, image, subresourceRange); /* Initialize the DCC metadata as "fully expanded". */ - cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, image, subresourceRange, 0xffffffff); + cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, image, subresourceRange, DCC_UNCOMPRESSED); } void diff --git a/src/amd/vulkan/meta/radv_meta_resolve.c b/src/amd/vulkan/meta/radv_meta_resolve.c index 87dee7bdd17..f399f3c40be 100644 --- a/src/amd/vulkan/meta/radv_meta_resolve.c +++ b/src/amd/vulkan/meta/radv_meta_resolve.c @@ -279,7 +279,7 @@ radv_meta_resolve_hardware_image(struct radv_cmd_buffer *cmd_buffer, struct radv .layerCount = 1, }; - cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, dst_image, &range, 0xffffffff); + cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, dst_image, &range, DCC_UNCOMPRESSED); } VkRect2D resolve_area = { diff --git a/src/amd/vulkan/meta/radv_meta_resolve_cs.c b/src/amd/vulkan/meta/radv_meta_resolve_cs.c index 6411277e0c0..3d2a03a44f3 100644 --- a/src/amd/vulkan/meta/radv_meta_resolve_cs.c +++ b/src/amd/vulkan/meta/radv_meta_resolve_cs.c @@ -357,7 +357,7 @@ radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer, struct radv_ .layerCount = vk_image_subresource_layer_count(&dst_image->vk, ®ion->dstSubresource), }; - cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, dst_image, &range, 0xffffffff); + cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, dst_image, &range, DCC_UNCOMPRESSED); } } diff --git a/src/amd/vulkan/radv_cmd_buffer.c b/src/amd/vulkan/radv_cmd_buffer.c index 7d0a32462f9..54e677056a1 100644 --- a/src/amd/vulkan/radv_cmd_buffer.c +++ b/src/amd/vulkan/radv_cmd_buffer.c @@ -14379,10 +14379,10 @@ radv_init_color_image_metadata(struct radv_cmd_buffer *cmd_buffer, struct radv_i } if (radv_dcc_enabled(image, range->baseMipLevel)) { - uint32_t value = 0xffffffffu; /* Fully expanded mode. */ + uint32_t value = DCC_UNCOMPRESSED; /* Fully expanded mode. */ if (radv_layout_dcc_compressed(device, image, range->baseMipLevel, dst_layout, dst_queue_mask)) { - value = 0u; + value = DCC_CLEAR_0000; } flush_bits |= radv_init_dcc(cmd_buffer, image, range, value); @@ -14443,7 +14443,7 @@ radv_handle_color_image_transition(struct radv_cmd_buffer *cmd_buffer, struct ra if (radv_dcc_enabled(image, range->baseMipLevel)) { if (src_layout == VK_IMAGE_LAYOUT_PREINITIALIZED) { - cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, image, range, 0xffffffffu); + cmd_buffer->state.flush_bits |= radv_init_dcc(cmd_buffer, image, range, DCC_UNCOMPRESSED); } else if (radv_layout_dcc_compressed(device, image, range->baseMipLevel, src_layout, src_queue_mask) && !radv_layout_dcc_compressed(device, image, range->baseMipLevel, dst_layout, dst_queue_mask)) { needs_dcc_decompress = true;