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iris: Drop GPGPU Tex Invalidate restriction for TGL+

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According to the HW docs, TGL+ no longer requires that a CS stall be
added to a texture cache invalidate done in the compute pipeline.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18725>
This commit is contained in:
Nanley Chery 2022-09-20 16:39:01 -07:00 • committed by Marge Bot
parent e3b794c184
commit 397e728ef4
1 changed files with 3 additions and 2 deletions
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5
src/gallium/drivers/iris/iris_state.c
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@ -8546,8 +8546,9 @@ iris_emit_raw_pipe_control(struct iris_batch *batch,
/* "GPGPU specific workarounds" (both post-sync and flush) ------------ */ /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */
if (IS_COMPUTE_PIPELINE(batch)) { if (IS_COMPUTE_PIPELINE(batch)) {
if (GFX_VER >= 9 && (flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE)) { if ((GFX_VER == 9 || GFX_VER == 11) &&
/* Project: SKL+ / Argument: Tex Invalidate (flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE)) {
/* Project: SKL, ICL / Argument: Tex Invalidate
* "Requires stall bit ([20] of DW) set for all GPGPU Workloads." * "Requires stall bit ([20] of DW) set for all GPGPU Workloads."
*/ */
flags |= PIPE_CONTROL_CS_STALL; flags |= PIPE_CONTROL_CS_STALL;