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iris: Drop the RT flush for PIPE_BARRIER_TEXTURE

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The render target flush would have been needed if it was possible to:

1) pollute the render cache and write to the data port in one draw
   call.

2) perform a subsequent operation that assumed the render cache was
   up-to-date.

However, this is not possible for the two glMemoryBarrier barrier bits
that get translated to this pipe barrier:

* GL_TEXTURE_FETCH_BARRIER_BIT is only used for sampling operations.
  It's possible to pollute the render cache and data cache with writes
  to a texture in one draw call (1). However, the GL spec states that
  apps cannot assume that any existing render caches are up-to-date for
  sampling the written locations immediately afterwards. Apps are
  required to use glTextureBarrier before the sampling operation, so
  requirement #2 is not satisfied.

* GL_PIXEL_BUFFER_BARRIER_BIT could be used for a PBO upload (2), but
  it's not possible to pollute the render cache and data cache with a
  PBO access in one draw call. PBOs cannot be bound to framebuffers
  for rendering, so requirement #1 is not satisfied.

Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> (v1)
Reviewed-by: Francisco Jerez <currojerez@riseup.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18725>
This commit is contained in:
Nanley Chery 2022-09-15 15:41:59 -07:00 • committed by Marge Bot
parent bb6d300b3a
commit e3b794c184
1 changed files with 10 additions and 1 deletions
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11
src/gallium/drivers/iris/iris_pipe_control.c
View file

@ -409,7 +409,16 @@ iris_memory_barrier(struct pipe_context *ctx, unsigned flags)
PIPE_CONTROL_CONST_CACHE_INVALIDATE;
}
if (flags & (PIPE_BARRIER_TEXTURE | PIPE_BARRIER_FRAMEBUFFER)) {
if (flags & PIPE_BARRIER_TEXTURE)
bits |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE;
if (flags & PIPE_BARRIER_FRAMEBUFFER) {
/* The caller may have issued a render target read and a data cache data
* port write in the same draw call. Depending on the hardware, iris
* performs render target reads with either the sampler or the render
* cache data port. If the next framebuffer access is a render target
* read, the previously affected caches must be invalidated.
*/
bits |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE |
PIPE_CONTROL_RENDER_TARGET_FLUSH;
}