From 397e728ef4f1247c0c2d11bf8516763b2a3088ff Mon Sep 17 00:00:00 2001 From: Nanley Chery Date: Tue, 20 Sep 2022 16:39:01 -0700 Subject: [PATCH] iris: Drop GPGPU Tex Invalidate restriction for TGL+ According to the HW docs, TGL+ no longer requires that a CS stall be added to a texture cache invalidate done in the compute pipeline. Reviewed-by: Lionel Landwerlin Part-of: --- src/gallium/drivers/iris/iris_state.c | 5 +++-- 1 file changed, 3 insertions(+), 2 deletions(-) diff --git a/src/gallium/drivers/iris/iris_state.c b/src/gallium/drivers/iris/iris_state.c index 90091021813..0aa320d402d 100644 --- a/src/gallium/drivers/iris/iris_state.c +++ b/src/gallium/drivers/iris/iris_state.c @@ -8546,8 +8546,9 @@ iris_emit_raw_pipe_control(struct iris_batch *batch, /* "GPGPU specific workarounds" (both post-sync and flush) ------------ */ if (IS_COMPUTE_PIPELINE(batch)) { - if (GFX_VER >= 9 && (flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE)) { - /* Project: SKL+ / Argument: Tex Invalidate + if ((GFX_VER == 9 || GFX_VER == 11) && + (flags & PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE)) { + /* Project: SKL, ICL / Argument: Tex Invalidate * "Requires stall bit ([20] of DW) set for all GPGPU Workloads." */ flags |= PIPE_CONTROL_CS_STALL;