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intel/fs: Teach IR about EOT instruction writing the accumulator implicitly on TGL+.

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This is unlikely to have had any negative side effect on the original
TGL, but will lead to issues on XeHP+ if the software scoreboard pass
isn't able to synchronize the accumulator writes.

Fixes: a27542c5dd ("intel/compiler: Clear accumulator register before EOT")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11433>
(cherry picked from commit 63abc083ce)
This commit is contained in:
Francisco Jerez 2021-05-25 15:43:01 -07:00 • committed by Eric Engestrom
parent 7a2e0b2a87
commit 2b5ac1147b
2 changed files with 3 additions and 2 deletions
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2
.pick_status.json
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@ -1336,7 +1336,7 @@
"description": "intel/fs: Teach IR about EOT instruction writing the accumulator implicitly on TGL+.",
"nominated": true,
"nomination_type": 1,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": "a27542c5ddec8dd6a64a9c236cf6bea1db1b9e48"
},

3
src/intel/compiler/brw_shader.cpp
View file

@ -1088,7 +1088,8 @@ backend_instruction::writes_accumulator_implicitly(const struct gen_device_info
((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
(opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) ||
(opcode == FS_OPCODE_LINTERP &&
(!devinfo->has_pln || devinfo->ver <= 6));
(!devinfo->has_pln || devinfo->ver <= 6)) ||
(eot && devinfo->ver >= 12); /* See Wa_14010017096. */
}
bool