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intel/fs: Teach IR about EOT instruction writing the accumulator implicitly on TGL+.

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This is unlikely to have had any negative side effect on the original
TGL, but will lead to issues on XeHP+ if the software scoreboard pass
isn't able to synchronize the accumulator writes.

Fixes: a27542c5dd ("intel/compiler: Clear accumulator register before EOT")
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11433>
This commit is contained in:
Francisco Jerez 2021-05-25 15:43:01 -07:00 • committed by Marge Bot
parent 5e7f443de0
commit 63abc083ce
1 changed files with 2 additions and 1 deletions
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3
src/intel/compiler/brw_shader.cpp
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@ -1090,7 +1090,8 @@ backend_instruction::writes_accumulator_implicitly(const struct intel_device_inf
((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) ||
(opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) ||
(opcode == FS_OPCODE_LINTERP &&
(!devinfo->has_pln || devinfo->ver <= 6));
(!devinfo->has_pln || devinfo->ver <= 6)) ||
(eot && devinfo->ver >= 12); /* See Wa_14010017096. */
}
bool