From 2b5ac1147bec23c0509109feb50c8f4a639d4fba Mon Sep 17 00:00:00 2001 From: Francisco Jerez Date: Tue, 25 May 2021 15:43:01 -0700 Subject: [PATCH] intel/fs: Teach IR about EOT instruction writing the accumulator implicitly on TGL+. This is unlikely to have had any negative side effect on the original TGL, but will lead to issues on XeHP+ if the software scoreboard pass isn't able to synchronize the accumulator writes. Fixes: a27542c5ddec8 ("intel/compiler: Clear accumulator register before EOT") Reviewed-by: Jason Ekstrand Part-of: (cherry picked from commit 63abc083ce5e03843d72465a76fdb93064bc3eb9) --- .pick_status.json | 2 +- src/intel/compiler/brw_shader.cpp | 3 ++- 2 files changed, 3 insertions(+), 2 deletions(-) diff --git a/.pick_status.json b/.pick_status.json index ed90019df52..2348f4225f5 100644 --- a/.pick_status.json +++ b/.pick_status.json @@ -1336,7 +1336,7 @@ "description": "intel/fs: Teach IR about EOT instruction writing the accumulator implicitly on TGL+.", "nominated": true, "nomination_type": 1, - "resolution": 0, + "resolution": 1, "main_sha": null, "because_sha": "a27542c5ddec8dd6a64a9c236cf6bea1db1b9e48" }, diff --git a/src/intel/compiler/brw_shader.cpp b/src/intel/compiler/brw_shader.cpp index 1ea61205b09..74b0db058bb 100644 --- a/src/intel/compiler/brw_shader.cpp +++ b/src/intel/compiler/brw_shader.cpp @@ -1088,7 +1088,8 @@ backend_instruction::writes_accumulator_implicitly(const struct gen_device_info ((opcode >= BRW_OPCODE_ADD && opcode < BRW_OPCODE_NOP) || (opcode >= FS_OPCODE_DDX_COARSE && opcode <= FS_OPCODE_LINTERP))) || (opcode == FS_OPCODE_LINTERP && - (!devinfo->has_pln || devinfo->ver <= 6)); + (!devinfo->has_pln || devinfo->ver <= 6)) || + (eot && devinfo->ver >= 12); /* See Wa_14010017096. */ } bool