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brw: scalarize even 64-bit scratch access

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No, I don't know how this worked before, thanks for asking.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40843>
This commit is contained in:
Alyssa Rosenzweig 2026-01-21 15:53:13 -05:00 • committed by Marge Bot
parent 15b11635a2
commit 140616d26a
1 changed files with 1 additions and 1 deletions
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src/intel/compiler/brw/brw_nir.c
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@ -2350,7 +2350,7 @@ get_mem_access_size_align(nir_intrinsic_op intrin, uint8_t bytes,
* two 32bit single vector access since it supports direct 64bit data
* operation.
*/
if (devinfo->has_lsc && align == 8 && bit_size == 64) {
if (devinfo->has_lsc && align == 8 && bit_size == 64 && !is_scratch) {
return (nir_mem_access_size_align) {
.bit_size = bit_size,
.num_components = bytes / 8,