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brw: Move intel_nir_opt_peephole_imul32x16 later in compilation

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(Split by Ken out of a patch authored by Alyssa.)

Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40843>
This commit is contained in:
Alyssa Rosenzweig 2026-04-06 17:06:31 -07:00 • committed by Marge Bot
parent e5598166b0
commit 15b11635a2
1 changed files with 5 additions and 1 deletions
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6
src/intel/compiler/brw/brw_nir.c
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@ -2803,7 +2803,6 @@ brw_postprocess_nir_opts(brw_pass_tracker *pt)
if (OPT(intel_nir_opt_peephole_ffma))
OPT(nir_opt_shrink_vectors, false);
OPT(intel_nir_opt_peephole_imul32x16);
OPT(nir_opt_generate_bfi);
OPT(nir_opt_reassociate_bfi);
@ -2923,6 +2922,11 @@ brw_postprocess_nir_out_of_ssa(brw_pass_tracker *pt,
{
nir_shader *nir = pt->nir;
/* Run this late - it interferes with algebraic opts after applying the SIMD
* width key if we have expressions like `(x * simd width) * 4.
*/
OPT(intel_nir_opt_peephole_imul32x16);
/* Run fsign lowering again after the last time brw_nir_optimize is called.
* As is the case with conversion lowering (below), brw_nir_optimize can
* create additional fsign instructions.