From 140616d26a0807c979641d60913a86a0580f1c14 Mon Sep 17 00:00:00 2001
From: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Date: Wed, 21 Jan 2026 15:53:13 -0500
Subject: [PATCH] brw: scalarize even 64-bit scratch access

No, I don't know how this worked before, thanks for asking.

Signed-off-by: Alyssa Rosenzweig <alyssa.rosenzweig@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40843>
---
 src/intel/compiler/brw/brw_nir.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/src/intel/compiler/brw/brw_nir.c b/src/intel/compiler/brw/brw_nir.c
index b23a3de388a..50cca73644c 100644
--- a/src/intel/compiler/brw/brw_nir.c
+++ b/src/intel/compiler/brw/brw_nir.c
@@ -2350,7 +2350,7 @@ get_mem_access_size_align(nir_intrinsic_op intrin, uint8_t bytes,
        * two 32bit single vector access since it supports direct 64bit data
        * operation.
        */
-      if (devinfo->has_lsc && align == 8 && bit_size == 64) {
+      if (devinfo->has_lsc && align == 8 && bit_size == 64 && !is_scratch) {
          return (nir_mem_access_size_align) {
             .bit_size = bit_size,
             .num_components = bytes / 8,