fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-05-08 11:18:08 +02:00
Code Issues Projects Releases Packages Wiki Activity Actions 1

anv: implement state cache invalidate for Wa_16013063087

Browse source 
Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22651>
(cherry picked from commit e501b31e15)
This commit is contained in:
Tapani Pälli 2023-04-24 13:11:48 +03:00 • committed by Eric Engestrom
parent aa48b8dc8d
commit 025b6a79c6
2 changed files with 12 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
.pick_status.json
View file

@ -778,7 +778,7 @@
"description": "anv: implement state cache invalidate for Wa_16013063087",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null
},

11
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -6665,6 +6665,17 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT;
#endif
/* Wa_16013063087 - State Cache Invalidate must be issued prior to
* PIPELINE_SELECT when switching from 3D to Compute.
*
* SW must do this by programming of PIPECONTROL with “CS Stall” followed by
* a PIPECONTROL with State Cache Invalidate bit set.
*
*/
if (cmd_buffer->state.current_pipeline == _3D && pipeline == GPGPU &&
intel_needs_workaround(cmd_buffer->device->info, 16013063087))
bits |= ANV_PIPE_STATE_CACHE_INVALIDATE_BIT;
anv_add_pending_pipe_bits(cmd_buffer, bits, "flush/invalidate PIPELINE_SELECT");
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);