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anv: cleanup bitmask construction for PIPELINE_SELECT

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Cc: mesa-stable
Signed-off-by: Tapani Pälli <tapani.palli@intel.com>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/22651>
(cherry picked from commit 72fc56aa37)
This commit is contained in:
Tapani Pälli 2023-04-24 13:10:31 +03:00 • committed by Eric Engestrom
parent 49d09360b5
commit aa48b8dc8d
2 changed files with 16 additions and 16 deletions
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2
.pick_status.json
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@ -787,7 +787,7 @@
"description": "anv: cleanup bitmask construction for PIPELINE_SELECT",
"nominated": true,
"nomination_type": 0,
"resolution": 0,
"resolution": 1,
"main_sha": null,
"because_sha": null
},

30
src/intel/vulkan/genX_cmd_buffer.c
View file

@ -6600,7 +6600,6 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
cmd_buffer->state.compute.pipeline_dirty = true;
#endif
#if GFX_VERx10 < 125
/* We apparently cannot flush the tile cache (color/depth) from the GPGPU
* pipeline. That means query clears will not be visible to query
@ -6615,6 +6614,9 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
}
#endif
/* Flush and invalidate bits done needed prior PIPELINE_SELECT. */
enum anv_pipe_bits bits = 0;
#if GFX_VER >= 12
/* From Tigerlake PRM, Volume 2a, PIPELINE_SELECT:
*
@ -6630,8 +6632,7 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
* Note: Issuing PIPE_CONTROL_MEDIA_STATE_CLEAR causes GPU hangs, probably
* because PIPE was not in MEDIA mode?!
*/
enum anv_pipe_bits bits = ANV_PIPE_CS_STALL_BIT |
ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
bits |= ANV_PIPE_CS_STALL_BIT | ANV_PIPE_HDC_PIPELINE_FLUSH_BIT;
if (cmd_buffer->state.current_pipeline == _3D) {
bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
@ -6639,7 +6640,6 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
} else {
bits |= ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT;
}
anv_add_pending_pipe_bits(cmd_buffer, bits, "flush PIPELINE_SELECT");
#else
/* From "BXML » GT » MI » vol1a GPU Overview » [Instruction]
* PIPELINE_SELECT [DevBWR+]":
@ -6654,18 +6654,18 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
* Note the cmd_buffer_apply_pipe_flushes will split this into two
* PIPE_CONTROLs.
*/
anv_add_pending_pipe_bits(cmd_buffer,
ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
ANV_PIPE_HDC_PIPELINE_FLUSH_BIT |
ANV_PIPE_CS_STALL_BIT |
ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT |
ANV_PIPE_STATE_CACHE_INVALIDATE_BIT |
ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT |
ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT,
"flush and invalidate for PIPELINE_SELECT");
bits |= ANV_PIPE_RENDER_TARGET_CACHE_FLUSH_BIT |
ANV_PIPE_DEPTH_CACHE_FLUSH_BIT |
ANV_PIPE_HDC_PIPELINE_FLUSH_BIT |
ANV_PIPE_CS_STALL_BIT |
ANV_PIPE_TEXTURE_CACHE_INVALIDATE_BIT |
ANV_PIPE_CONSTANT_CACHE_INVALIDATE_BIT |
ANV_PIPE_STATE_CACHE_INVALIDATE_BIT |
ANV_PIPE_INSTRUCTION_CACHE_INVALIDATE_BIT |
ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT;
#endif
anv_add_pending_pipe_bits(cmd_buffer, bits, "flush/invalidate PIPELINE_SELECT");
genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);
#if GFX_VER == 9