diff --git a/.pick_status.json b/.pick_status.json
index 573cff403c5..ec4c040d688 100644
--- a/.pick_status.json
+++ b/.pick_status.json
@@ -778,7 +778,7 @@
         "description": "anv: implement state cache invalidate for Wa_16013063087",
         "nominated": true,
         "nomination_type": 0,
-        "resolution": 0,
+        "resolution": 1,
         "main_sha": null,
         "because_sha": null
     },
diff --git a/src/intel/vulkan/genX_cmd_buffer.c b/src/intel/vulkan/genX_cmd_buffer.c
index 0b41c9dcdcc..0b4ec5ba472 100644
--- a/src/intel/vulkan/genX_cmd_buffer.c
+++ b/src/intel/vulkan/genX_cmd_buffer.c
@@ -6665,6 +6665,17 @@ genX(flush_pipeline_select)(struct anv_cmd_buffer *cmd_buffer,
            ANV_PIPE_UNTYPED_DATAPORT_CACHE_FLUSH_BIT;
 #endif
 
+   /* Wa_16013063087 -  State Cache Invalidate must be issued prior to
+    * PIPELINE_SELECT when switching from 3D to Compute.
+    *
+    * SW must do this by programming of PIPECONTROL with “CS Stall” followed by
+    * a PIPECONTROL with State Cache Invalidate bit set.
+    *
+    */
+   if (cmd_buffer->state.current_pipeline == _3D && pipeline == GPGPU &&
+       intel_needs_workaround(cmd_buffer->device->info, 16013063087))
+      bits |= ANV_PIPE_STATE_CACHE_INVALIDATE_BIT;
+
    anv_add_pending_pipe_bits(cmd_buffer, bits, "flush/invalidate PIPELINE_SELECT");
    genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer);