2017-09-14 17:57:17 -07:00
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# Copyright © 2017 Intel Corporation
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2024-06-28 13:16:28 -07:00
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# SPDX-License-Identifier: MIT
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2017-09-14 17:57:17 -07:00
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2023-11-01 12:51:33 -07:00
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intel_nir_files = files(
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'intel_nir.h',
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'intel_nir.c',
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2023-11-01 15:15:43 -07:00
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'intel_nir_blockify_uniform_loads.c',
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'intel_nir_clamp_image_1d_2d_array_sizes.c',
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'intel_nir_clamp_per_vertex_loads.c',
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'intel_nir_lower_non_uniform_barycentric_at_sample.c',
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'intel_nir_lower_non_uniform_resource_intel.c',
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2023-09-05 16:11:56 +03:00
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'intel_nir_lower_printf.c',
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2023-11-01 15:15:43 -07:00
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'intel_nir_lower_shading_rate_output.c',
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'intel_nir_lower_sparse.c',
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'intel_nir_opt_peephole_ffma.c',
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'intel_nir_opt_peephole_imul32x16.c',
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'intel_nir_tcs_workarounds.c',
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2023-11-01 12:51:33 -07:00
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)
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2024-02-09 15:37:14 -08:00
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libintel_compiler_brw_files = files(
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2024-12-06 20:02:38 -08:00
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'brw_analysis.h',
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2024-12-06 20:35:37 -08:00
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'brw_analysis.cpp',
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2024-12-06 19:48:54 -08:00
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'brw_analysis_def.cpp',
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2024-12-06 19:48:54 -08:00
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'brw_analysis_liveness.cpp',
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2024-12-06 19:48:54 -08:00
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'brw_analysis_performance.cpp',
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2024-12-06 21:46:48 -08:00
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'brw_builder.cpp',
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2025-01-15 08:20:46 -08:00
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'brw_builder.h',
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2017-09-14 17:57:17 -07:00
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'brw_cfg.cpp',
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'brw_cfg.h',
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2024-07-12 13:52:46 -07:00
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'brw_compile_bs.cpp',
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'brw_compile_cs.cpp',
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'brw_compile_fs.cpp',
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2024-02-14 18:17:59 -08:00
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'brw_compile_gs.cpp',
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2024-07-12 13:52:46 -07:00
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'brw_compile_mesh.cpp',
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2024-02-14 18:17:59 -08:00
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'brw_compile_tcs.cpp',
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2024-07-12 13:52:46 -07:00
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'brw_compile_tes.cpp',
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2024-02-14 18:17:59 -08:00
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'brw_compile_vs.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_compiler.c',
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'brw_compiler.h',
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2019-04-15 21:59:50 -07:00
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'brw_debug_recompile.c',
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2017-09-14 17:57:17 -07:00
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'brw_disasm.c',
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2024-02-29 17:53:53 -08:00
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'brw_disasm_info.cpp',
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2017-11-16 11:43:51 -08:00
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'brw_disasm_info.h',
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2022-06-30 01:47:09 -07:00
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'brw_eu.c',
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2017-09-14 17:57:17 -07:00
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'brw_eu_compact.c',
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'brw_eu_defines.h',
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'brw_eu_emit.c',
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2024-12-14 14:36:38 -08:00
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'brw_eu_inst.h',
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2017-09-14 17:57:17 -07:00
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'brw_eu.h',
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'brw_eu_validate.c',
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2025-01-31 10:56:33 -08:00
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'brw_from_nir.cpp',
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2025-01-13 17:47:32 -08:00
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'brw_generator.cpp',
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2024-12-06 16:17:46 -08:00
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'brw_generator.h',
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2024-12-06 13:05:43 -08:00
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'brw_inst.cpp',
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'brw_inst.h',
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2022-06-29 14:25:19 -07:00
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'brw_isa_info.h',
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2025-07-28 16:07:44 -04:00
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'brw_list.h',
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brw: Add passes to generate and lower load_reg
v2: Add support for WE_all instructions... this already just worked, so
I only had to delete the check and the FINISHME comment.
v3: Use logic more like def_analysis::update_for_reads to determine when
to not insert LOAD_REG instructions. Based on a suggestion by Ken.
v4: Eliminate "store" from all the names since STORE_REG does not exist
anymore. Fold insert_load_reg into brw_insert_load_reg. Elminate extra
call to s.def_analysis.require() after progress. Pull a loop-invariant
check out of the inst->srouces loop. Drop call to
brw_opt_split_virtual_grfs after lowering load_reg. All suggested by
Caio.
v5: Assert that LOAD_REG doesn't already exist in
brw_insert_load_reg. Update comment before fully_defines. Both
suggested by Caio.
v6: Don't explicitly special-case SHADER_OPCODE_MEMORY_STORE_LOGICAL.
Move the inst->dst.file != VGRF check earlier to avoid the loop over
sources. Both suggested by Ken. Move the call the brw_insert_load_reg
a little bit later, and explain why it's at that location. Suggested
by Caio.
v7: Many changes to the for-each-source loop in brw_insert_load_reg.
Removes incorrect multiplication of s.alloc.sizes with reg_unit. Adds
checks for matching SIMD size and NoMask in the search for pre-existing
LOAD_REG of same value.
v8: Add some unit tests. Suggested by Caio.
shader-db:
Lunar Lake
total instructions in shared programs: 16923237 -> 16921895 (<.01%)
instructions in affected programs: 450565 -> 449223 (-0.30%)
helped: 251 / HURT: 377
total cycles in shared programs: 910428418 -> 889920590 (-2.25%)
cycles in affected programs: 719248184 -> 698740356 (-2.85%)
helped: 9076 / HURT: 9082
total fills in shared programs: 2242 -> 2218 (-1.07%)
fills in affected programs: 116 -> 92 (-20.69%)
helped: 2 / HURT: 0
total sends in shared programs: 848635 -> 848421 (-0.03%)
sends in affected programs: 810 -> 596 (-26.42%)
helped: 10 / HURT: 0
LOST: 82
GAINED: 78
Meteor Lake and DG2 had similar results. (Meteor Lake shown)
total instructions in shared programs: 19875784 -> 19871694 (-0.02%)
instructions in affected programs: 1050091 -> 1046001 (-0.39%)
helped: 251 / HURT: 2403
total cycles in shared programs: 905328238 -> 882446458 (-2.53%)
cycles in affected programs: 682736344 -> 659854564 (-3.35%)
helped: 7869 / HURT: 7911
total spills in shared programs: 5512 -> 5032 (-8.71%)
spills in affected programs: 1830 -> 1350 (-26.23%)
helped: 8 / HURT: 0
total fills in shared programs: 5648 -> 4782 (-15.33%)
fills in affected programs: 3312 -> 2446 (-26.15%)
helped: 8 / HURT: 0
total sends in shared programs: 1032942 -> 1032722 (-0.02%)
sends in affected programs: 572 -> 352 (-38.46%)
helped: 10 / HURT: 0
LOST: 138
GAINED: 53
Tiger Lake
total instructions in shared programs: 19711930 -> 19715591 (0.02%)
instructions in affected programs: 1040623 -> 1044284 (0.35%)
helped: 317 / HURT: 2474
total cycles in shared programs: 862988990 -> 860573870 (-0.28%)
cycles in affected programs: 612392461 -> 609977341 (-0.39%)
helped: 7447 / HURT: 7686
total sends in shared programs: 1034763 -> 1034555 (-0.02%)
sends in affected programs: 784 -> 576 (-26.53%)
helped: 8 / HURT: 0
LOST: 56
GAINED: 143
Ice Lake and Skylake had similar results. (Ice Lake shown)
total instructions in shared programs: 20545461 -> 20545220 (<.01%)
instructions in affected programs: 422405 -> 422164 (-0.06%)
helped: 180 / HURT: 459
total cycles in shared programs: 872697345 -> 866874523 (-0.67%)
cycles in affected programs: 573117917 -> 567295095 (-1.02%)
helped: 6783 / HURT: 6980
total spills in shared programs: 4335 -> 4336 (0.02%)
spills in affected programs: 90 -> 91 (1.11%)
helped: 1 / HURT: 2
total fills in shared programs: 4194 -> 4196 (0.05%)
fills in affected programs: 463 -> 465 (0.43%)
helped: 1 / HURT: 2
total sends in shared programs: 1079446 -> 1079238 (-0.02%)
sends in affected programs: 784 -> 576 (-26.53%)
helped: 8 / HURT: 0
LOST: 117
GAINED: 37
fossil-db:
All Intel platforms had similar results. (Lunar Lake shown)
Totals:
Instrs: 209708136 -> 209695617 (-0.01%); split: -0.02%, +0.01%
Send messages: 10927753 -> 10927640 (-0.00%)
Cycle count: 30540172048 -> 30427084732 (-0.37%); split: -0.99%, +0.62%
Spill count: 511621 -> 510932 (-0.13%); split: -0.22%, +0.08%
Fill count: 621166 -> 618440 (-0.44%); split: -0.56%, +0.12%
Scratch Memory Size: 35574784 -> 35648512 (+0.21%); split: -0.06%, +0.26%
Max live registers: 65453860 -> 65453140 (-0.00%); split: -0.00%, +0.00%
Non SSA regs after NIR: 75374990 -> 35195764 (-53.31%)
Totals from 503284 (71.25% of 706391) affected shaders:
Instrs: 180203778 -> 180191259 (-0.01%); split: -0.02%, +0.01%
Send messages: 9699732 -> 9699619 (-0.00%)
Cycle count: 30080349592 -> 29967262276 (-0.38%); split: -1.01%, +0.63%
Spill count: 511584 -> 510895 (-0.13%); split: -0.22%, +0.08%
Fill count: 621120 -> 618394 (-0.44%); split: -0.56%, +0.12%
Scratch Memory Size: 35443712 -> 35517440 (+0.21%); split: -0.06%, +0.27%
Max live registers: 52566092 -> 52565372 (-0.00%); split: -0.01%, +0.00%
Non SSA regs after NIR: 70110949 -> 29931723 (-57.31%)
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31497>
2024-09-18 18:11:13 -07:00
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'brw_load_reg.cpp',
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2024-12-29 10:01:36 -08:00
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'brw_lower.cpp',
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'brw_lower_dpas.cpp',
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'brw_lower_integer_multiplication.cpp',
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2022-06-27 12:24:58 -07:00
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'brw_lower_logical_sends.cpp',
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2024-12-29 10:01:36 -08:00
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'brw_lower_pack.cpp',
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'brw_lower_regioning.cpp',
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'brw_lower_scoreboard.cpp',
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'brw_lower_simd_width.cpp',
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2024-07-15 15:09:12 -07:00
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'brw_lower_subgroup_ops.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_nir.h',
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'brw_nir.c',
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'brw_nir_analyze_ubo_ranges.c',
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2023-06-13 19:45:49 -07:00
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'brw_nir_lower_cooperative_matrix.c',
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2017-10-06 10:08:11 -07:00
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'brw_nir_lower_cs_intrinsics.c',
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2019-09-27 16:23:46 -07:00
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'brw_nir_lower_alpha_to_coverage.c',
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2025-03-11 15:47:40 -07:00
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'brw_nir_lower_fs_barycentrics.c',
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brw: run the nir_opt_offsets pass and set the maximum offset size
Perf A/B testing on DG2: no changes
Perf A/B testing on BMG: +2.1% Blackops3, +1.5% Cyberpunk
DG2 stats (mostly insignificant):
Assassins Creed Valhalla:
Totals from 1169 (55.67% of 2100) affected shaders:
Instrs: 509237 -> 509215 (-0.00%)
Cycle count: 30614325 -> 30607419 (-0.02%); split: -0.03%, +0.00%
Non SSA regs after NIR: 83434 -> 85909 (+2.97%)
Blackops 3:
Totals from 1045 (64.63% of 1617) affected shaders:
Instrs: 527312 -> 527310 (-0.00%)
Cycle count: 496912222 -> 496902846 (-0.00%); split: -0.00%, +0.00%
Non SSA regs after NIR: 106883 -> 109095 (+2.07%)
Cyberpunk:
Totals from 706 (56.03% of 1260) affected shaders:
Instrs: 345976 -> 345974 (-0.00%); split: -0.00%, +0.00%
Cycle count: 9775138 -> 9775472 (+0.00%); split: -0.00%, +0.00%
Max live registers: 40295 -> 40297 (+0.00%)
Non SSA regs after NIR: 93245 -> 94718 (+1.58%)
Fortnite:
Totals from 4210 (55.98% of 7521) affected shaders:
Instrs: 2205471 -> 2205469 (-0.00%)
Cycle count: 91451040 -> 91450956 (-0.00%); split: -0.00%, +0.00%
Non SSA regs after NIR: 952354 -> 961664 (+0.98%)
LNL stats (notable changes):
Assassins Creed Valhalla:
Totals from 1684 (83.57% of 2015) affected shaders:
Instrs: 774305 -> 764501 (-1.27%); split: -1.27%, +0.01%
Cycle count: 58845842 -> 58699250 (-0.25%); split: -0.98%, +0.73%
Spill count: 625 -> 638 (+2.08%)
Fill count: 1490 -> 1503 (+0.87%)
Scratch Memory Size: 41984 -> 44032 (+4.88%)
Max live registers: 196424 -> 197561 (+0.58%); split: -0.10%, +0.68%
Blackops 3:
Totals from 1125 (76.53% of 1470) affected shaders:
Instrs: 781749 -> 773275 (-1.08%); split: -1.08%, +0.00%
Subgroup size: 22896 -> 22912 (+0.07%)
Cycle count: 659864454 -> 654641032 (-0.79%); split: -1.10%, +0.31%
Max live registers: 116772 -> 116854 (+0.07%); split: -0.01%, +0.08%
Non SSA regs after NIR: 172648 -> 168260 (-2.54%); split: -2.55%, +0.01%
Control:
Totals from 378 (51.50% of 734) affected shaders:
Instrs: 148184 -> 147544 (-0.43%)
Cycle count: 6905200 -> 6913366 (+0.12%); split: -0.30%, +0.42%
Max live registers: 41271 -> 41281 (+0.02%)
Non SSA regs after NIR: 44964 -> 43868 (-2.44%); split: -2.45%, +0.01%
Cyberpunk:
Totals from 1141 (92.46% of 1234) affected shaders:
Instrs: 636744 -> 629333 (-1.16%)
Subgroup size: 24256 -> 24272 (+0.07%)
Cycle count: 24952258 -> 24801298 (-0.60%); split: -1.39%, +0.78%
Max live registers: 125848 -> 126855 (+0.80%); split: -0.00%, +0.80%
Non SSA regs after NIR: 127399 -> 119837 (-5.94%); split: -5.95%, +0.02%
Fortnite:
Totals from 5497 (83.52% of 6582) affected shaders:
Instrs: 4072831 -> 4041852 (-0.76%); split: -0.77%, +0.01%
Subgroup size: 103296 -> 103312 (+0.02%)
Cycle count: 133046874 -> 132789242 (-0.19%); split: -0.67%, +0.48%
Spill count: 7218 -> 7254 (+0.50%); split: -0.33%, +0.83%
Fill count: 11724 -> 11749 (+0.21%); split: -0.34%, +0.55%
Scratch Memory Size: 591872 -> 599040 (+1.21%)
Max live registers: 816530 -> 818522 (+0.24%); split: -0.01%, +0.26%
Non SSA regs after NIR: 1610296 -> 1560284 (-3.11%); split: -3.11%, +0.00%
Hitman3:
Totals from 4713 (92.39% of 5101) affected shaders:
Instrs: 2731598 -> 2698224 (-1.22%)
Cycle count: 186422098 -> 185472640 (-0.51%); split: -1.12%, +0.61%
Spill count: 3244 -> 3242 (-0.06%)
Fill count: 9937 -> 9933 (-0.04%)
Max live registers: 585035 -> 589801 (+0.81%); split: -0.00%, +0.82%
Non SSA regs after NIR: 347681 -> 324314 (-6.72%); split: -6.73%, +0.01%
Hogwarts Legacy:
Totals from 930 (59.81% of 1555) affected shaders:
Instrs: 464146 -> 459526 (-1.00%); split: -1.00%, +0.01%
Subgroup size: 19104 -> 19120 (+0.08%)
Cycle count: 24062460 -> 24078964 (+0.07%); split: -0.49%, +0.56%
Spill count: 2068 -> 1964 (-5.03%); split: -5.22%, +0.19%
Fill count: 2342 -> 2205 (-5.85%); split: -6.40%, +0.56%
Scratch Memory Size: 147456 -> 141312 (-4.17%)
Max live registers: 112384 -> 112787 (+0.36%); split: -0.08%, +0.44%
Non SSA regs after NIR: 80293 -> 79161 (-1.41%); split: -1.72%, +0.32%
Metro Exodus:
Totals from 29755 (78.62% of 37846) affected shaders:
Instrs: 11495578 -> 11492951 (-0.02%); split: -0.02%, +0.00%
Subgroup size: 644688 -> 644704 (+0.00%)
Cycle count: 301572068 -> 301548054 (-0.01%); split: -0.03%, +0.02%
Max live registers: 3369504 -> 3370454 (+0.03%); split: -0.00%, +0.03%
Non SSA regs after NIR: 2476561 -> 2396090 (-3.25%); split: -3.27%, +0.02%
Red Dead Redemption 2:
Totals from 4161 (78.61% of 5293) affected shaders:
Instrs: 2428782 -> 2409032 (-0.81%); split: -0.82%, +0.00%
Subgroup size: 85344 -> 85360 (+0.02%)
Cycle count: 8514984142 -> 8533415324 (+0.22%); split: -0.02%, +0.23%
Spill count: 4659 -> 4674 (+0.32%); split: -0.02%, +0.34%
Fill count: 11236 -> 11231 (-0.04%); split: -0.19%, +0.14%
Scratch Memory Size: 398336 -> 397312 (-0.26%)
Max live registers: 473946 -> 475798 (+0.39%); split: -0.08%, +0.47%
Non SSA regs after NIR: 616820 -> 567706 (-7.96%); split: -8.09%, +0.12%
Rise Of The Tomb Raider:
Totals from 68 (46.58% of 146) affected shaders:
Instrs: 28209 -> 27801 (-1.45%)
Subgroup size: 1584 -> 1600 (+1.01%)
Cycle count: 16182992 -> 16249364 (+0.41%); split: -0.97%, +1.38%
Max live registers: 7320 -> 7296 (-0.33%); split: -0.38%, +0.05%
Non SSA regs after NIR: 8438 -> 8207 (-2.74%); split: -2.82%, +0.08%
Spiderman Remastered:
Totals from 6403 (93.87% of 6821) affected shaders:
Instrs: 5662713 -> 5597949 (-1.14%); split: -1.28%, +0.14%
Cycle count: 282861519016 -> 279806958122 (-1.08%); split: -1.26%, +0.18%
Spill count: 61150 -> 60754 (-0.65%); split: -1.13%, +0.48%
Fill count: 162597 -> 163190 (+0.36%); split: -0.84%, +1.21%
Scratch Memory Size: 5834752 -> 5804032 (-0.53%); split: -0.70%, +0.18%
Max live registers: 901926 -> 903820 (+0.21%); split: -0.01%, +0.22%
Non SSA regs after NIR: 555053 -> 521016 (-6.13%); split: -6.14%, +0.01%
Signed-off-by: Rohan Garg <rohan.garg@intel.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/35252>
2024-05-22 12:22:47 +02:00
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'brw_nir_lower_immediate_offsets.c',
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2020-08-06 16:22:15 -05:00
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'brw_nir_lower_intersection_shader.c',
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2021-06-21 13:44:53 +03:00
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'brw_nir_lower_ray_queries.c',
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2020-08-06 12:59:49 -05:00
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'brw_nir_lower_rt_intrinsics.c',
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2025-03-26 16:05:15 +02:00
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'brw_nir_lower_rt_intrinsics_pre_trace.c',
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2023-10-04 15:39:48 -07:00
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'brw_nir_lower_sample_index_in_coord.c',
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2020-08-06 13:53:34 -05:00
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'brw_nir_lower_shader_calls.c',
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2021-02-03 11:34:46 -08:00
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'brw_nir_lower_storage_image.c',
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2024-12-07 03:56:38 +08:00
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'brw_nir_lower_texel_address.c',
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2025-03-26 10:48:51 +02:00
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'brw_nir_lower_texture.c',
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2025-05-16 11:46:33 +03:00
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'brw_nir_wa_18019110168.c',
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intel/brw: Move fsat instructions closer to the source
Intel GPUs have a saturate destination modifier, and
brw_fs_opt_saturate_propagation tries to replace explicit saturate
operations with this destination modifier. That pass is limited in
several ways. If the source of the explicit saturate is in a different
block or if the source of the explicit saturate is live after the
explicit saturate, brw_fs_opt_saturate_propagation will be unable to
make progress.
This optimization exists to help brw_fs_opt_saturate_propagation make
more progress. It tries to move NIR fsat instructions to the same block
that contains the definition of its source. It does this only in cases
where it will not create additional live values. It also attempts to do
this only in cases where the explicit saturate will ultimiately be
converted to a destination modifier.
v2: Fix metadata_preserve when theres no progress and use
nir_metadata_control_flow when there is progress. All suggested by
Alyssa.
v3: Fix a typo in the file header comment. Noticed by Ken. Don't
require nir_metadata_instr_index. Use nir_def_rewrite_uses_after instead
of open-coding something slightly more specific. Both suggested by Ken.
shader-db:
All Intel platforms had similar results. (Meteor Lake shown)
total instructions in shared programs: 19733645 -> 19733028 (<.01%)
instructions in affected programs: 193300 -> 192683 (-0.32%)
helped: 246
HURT: 1
helped stats (abs) min: 2 max: 48 x̄: 2.51 x̃: 2
helped stats (rel) min: 0.18% max: 0.39% x̄: 0.33% x̃: 0.34%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 0.31% max: 0.31% x̄: 0.31% x̃: 0.31%
95% mean confidence interval for instructions value: -2.87 -2.13
95% mean confidence interval for instructions %-change: -0.34% -0.32%
Instructions are helped.
total cycles in shared programs: 916180971 -> 916264656 (<.01%)
cycles in affected programs: 30197180 -> 30280865 (0.28%)
helped: 194
HURT: 142
helped stats (abs) min: 1 max: 21251 x̄: 872.75 x̃: 19
helped stats (rel) min: <.01% max: 23.17% x̄: 2.59% x̃: 0.23%
HURT stats (abs) min: 1 max: 28058 x̄: 1781.68 x̃: 399
HURT stats (rel) min: <.01% max: 37.21% x̄: 4.85% x̃: 1.63%
95% mean confidence interval for cycles value: -196.84 694.97
95% mean confidence interval for cycles %-change: -0.17% 1.27%
Inconclusive result (value mean confidence interval includes 0).
fossil-db:
Meteor Lake, DG2, and Tiger Lake had similar results. (Meteor Lake shown)
Totals:
Instrs: 151512021 -> 151511351 (-0.00%); split: -0.00%, +0.00%
Cycle count: 17209013596 -> 17209840995 (+0.00%); split: -0.02%, +0.02%
Max live registers: 32013312 -> 32013549 (+0.00%)
Max dispatch width: 5512304 -> 5512136 (-0.00%)
Totals from 774 (0.12% of 630172) affected shaders:
Instrs: 1559285 -> 1558615 (-0.04%); split: -0.05%, +0.01%
Cycle count: 1312656268 -> 1313483667 (+0.06%); split: -0.24%, +0.30%
Max live registers: 82195 -> 82432 (+0.29%)
Max dispatch width: 6664 -> 6496 (-2.52%)
Ice Lake
Totals:
Instrs: 151416791 -> 151416137 (-0.00%); split: -0.00%, +0.00%
Cycle count: 15162468885 -> 15163298824 (+0.01%); split: -0.00%, +0.01%
Max live registers: 32471367 -> 32471603 (+0.00%)
Max dispatch width: 5623752 -> 5623712 (-0.00%)
Totals from 733 (0.12% of 635598) affected shaders:
Instrs: 877965 -> 877311 (-0.07%); split: -0.09%, +0.01%
Cycle count: 190763628 -> 191593567 (+0.44%); split: -0.21%, +0.64%
Max live registers: 72067 -> 72303 (+0.33%)
Max dispatch width: 6216 -> 6176 (-0.64%)
Skylake
Totals:
Instrs: 140794845 -> 140794075 (-0.00%); split: -0.00%, +0.00%
Cycle count: 14665159301 -> 14665320514 (+0.00%); split: -0.00%, +0.01%
Max live registers: 31783341 -> 31783662 (+0.00%); split: -0.00%, +0.00%
Totals from 659 (0.11% of 625670) affected shaders:
Instrs: 829061 -> 828291 (-0.09%); split: -0.09%, +0.00%
Cycle count: 185478478 -> 185639691 (+0.09%); split: -0.33%, +0.41%
Max live registers: 67491 -> 67812 (+0.48%); split: -0.01%, +0.48%
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29774>
2024-06-07 13:08:06 -07:00
|
|
|
'brw_nir_opt_fsat.c',
|
2020-08-06 12:59:49 -05:00
|
|
|
'brw_nir_rt.h',
|
2020-08-06 13:20:07 -05:00
|
|
|
'brw_nir_rt.c',
|
2020-08-06 12:44:57 -05:00
|
|
|
'brw_nir_rt_builder.h',
|
2024-12-29 10:01:36 -08:00
|
|
|
'brw_opt.cpp',
|
brw: move final send lowering up into the IR
Because we do emit the final send message form in code generation, a
lot of emissions look like this :
add(8) vgrf0, u0, 0x100
mov(1) a0.1, vgrf0 # emitted by the generator
send(8) ..., a0.1
By moving address register manipulation in the IR, we can get this
down to :
add(1) a0.1, u0, 0x100
send(8) ..., a0.1
This reduce register pressure around some send messages by 1 vgrf.
All lost shaders in the below results are fragment SIMD32, due to the
throughput estimator. If turned off, we loose no SIMD32 shaders with
this change.
DG2 results:
Assassin's Creed Valhalla:
Totals from 2044 (96.87% of 2110) affected shaders:
Instrs: 852879 -> 832044 (-2.44%); split: -2.45%, +0.00%
Subgroup size: 23832 -> 23824 (-0.03%)
Cycle count: 53345742 -> 52144277 (-2.25%); split: -5.08%, +2.82%
Spill count: 729 -> 554 (-24.01%); split: -28.40%, +4.39%
Fill count: 2005 -> 1256 (-37.36%)
Scratch Memory Size: 25600 -> 19456 (-24.00%); split: -32.00%, +8.00%
Max live registers: 116765 -> 115058 (-1.46%)
Max dispatch width: 19152 -> 18872 (-1.46%); split: +0.21%, -1.67%
Cyberpunk 2077:
Totals from 1181 (93.43% of 1264) affected shaders:
Instrs: 667192 -> 663615 (-0.54%); split: -0.55%, +0.01%
Subgroup size: 13016 -> 13032 (+0.12%)
Cycle count: 17383539 -> 17986073 (+3.47%); split: -0.93%, +4.39%
Spill count: 12 -> 8 (-33.33%)
Fill count: 9 -> 6 (-33.33%)
Dota2:
Totals from 173 (11.59% of 1493) affected shaders:
Cycle count: 274403 -> 280817 (+2.34%); split: -0.01%, +2.34%
Max live registers: 5787 -> 5779 (-0.14%)
Max dispatch width: 1344 -> 1152 (-14.29%)
Hitman3:
Totals from 5072 (95.39% of 5317) affected shaders:
Instrs: 2879952 -> 2841804 (-1.32%); split: -1.32%, +0.00%
Cycle count: 153208505 -> 165860401 (+8.26%); split: -2.22%, +10.48%
Spill count: 3942 -> 3200 (-18.82%)
Fill count: 10158 -> 8846 (-12.92%)
Scratch Memory Size: 257024 -> 223232 (-13.15%)
Max live registers: 328467 -> 324631 (-1.17%)
Max dispatch width: 43928 -> 42768 (-2.64%); split: +0.09%, -2.73%
Fortnite:
Totals from 360 (4.82% of 7472) affected shaders:
Instrs: 778068 -> 777925 (-0.02%)
Subgroup size: 3128 -> 3136 (+0.26%)
Cycle count: 38684183 -> 38734579 (+0.13%); split: -0.06%, +0.19%
Max live registers: 50689 -> 50658 (-0.06%)
Hogwarts Legacy:
Totals from 1376 (84.00% of 1638) affected shaders:
Instrs: 758810 -> 749727 (-1.20%); split: -1.23%, +0.03%
Cycle count: 27778983 -> 28805469 (+3.70%); split: -1.42%, +5.12%
Spill count: 2475 -> 2299 (-7.11%); split: -7.47%, +0.36%
Fill count: 2677 -> 2445 (-8.67%); split: -9.90%, +1.23%
Scratch Memory Size: 99328 -> 89088 (-10.31%)
Max live registers: 84969 -> 84671 (-0.35%); split: -0.58%, +0.23%
Max dispatch width: 11848 -> 11920 (+0.61%)
Metro Exodus:
Totals from 92 (0.21% of 43072) affected shaders:
Instrs: 262995 -> 262968 (-0.01%)
Cycle count: 13818007 -> 13851266 (+0.24%); split: -0.01%, +0.25%
Max live registers: 11152 -> 11140 (-0.11%)
Red Dead Redemption 2 :
Totals from 451 (7.71% of 5847) affected shaders:
Instrs: 754178 -> 753811 (-0.05%); split: -0.05%, +0.00%
Cycle count: 3484078523 -> 3484111965 (+0.00%); split: -0.00%, +0.00%
Max live registers: 42294 -> 42185 (-0.26%)
Spiderman Remastered:
Totals from 6820 (98.02% of 6958) affected shaders:
Instrs: 6921500 -> 6747933 (-2.51%); split: -4.16%, +1.65%
Cycle count: 234400692460 -> 236846720707 (+1.04%); split: -0.20%, +1.25%
Spill count: 72971 -> 72622 (-0.48%); split: -8.08%, +7.61%
Fill count: 212921 -> 198483 (-6.78%); split: -12.37%, +5.58%
Scratch Memory Size: 3491840 -> 3410944 (-2.32%); split: -12.05%, +9.74%
Max live registers: 493149 -> 487458 (-1.15%)
Max dispatch width: 56936 -> 56856 (-0.14%); split: +0.06%, -0.20%
Strange Brigade:
Totals from 3769 (91.21% of 4132) affected shaders:
Instrs: 1354476 -> 1321474 (-2.44%)
Cycle count: 25351530 -> 25339190 (-0.05%); split: -1.64%, +1.59%
Max live registers: 199057 -> 193656 (-2.71%)
Max dispatch width: 30272 -> 30240 (-0.11%)
Witcher 3:
Totals from 25 (2.40% of 1041) affected shaders:
Instrs: 24621 -> 24606 (-0.06%)
Cycle count: 2218793 -> 2217503 (-0.06%); split: -0.11%, +0.05%
Max live registers: 1963 -> 1955 (-0.41%)
LNL results:
Assassin's Creed Valhalla:
Totals from 1928 (98.02% of 1967) affected shaders:
Instrs: 856107 -> 835756 (-2.38%); split: -2.48%, +0.11%
Subgroup size: 41264 -> 41280 (+0.04%)
Cycle count: 64606590 -> 62371700 (-3.46%); split: -5.57%, +2.11%
Spill count: 915 -> 669 (-26.89%); split: -32.79%, +5.90%
Fill count: 2414 -> 1617 (-33.02%); split: -36.62%, +3.60%
Scratch Memory Size: 62464 -> 44032 (-29.51%); split: -36.07%, +6.56%
Max live registers: 205483 -> 202192 (-1.60%)
Cyberpunk 2077:
Totals from 1177 (96.40% of 1221) affected shaders:
Instrs: 682237 -> 678931 (-0.48%); split: -0.51%, +0.03%
Subgroup size: 24912 -> 24944 (+0.13%)
Cycle count: 24355928 -> 25089292 (+3.01%); split: -0.80%, +3.81%
Spill count: 8 -> 3 (-62.50%)
Fill count: 6 -> 3 (-50.00%)
Max live registers: 126922 -> 125472 (-1.14%)
Dota2:
Totals from 428 (32.47% of 1318) affected shaders:
Instrs: 89355 -> 89740 (+0.43%)
Cycle count: 1152412 -> 1152706 (+0.03%); split: -0.52%, +0.55%
Max live registers: 32863 -> 32847 (-0.05%)
Fortnite:
Totals from 5354 (81.72% of 6552) affected shaders:
Instrs: 4135059 -> 4239015 (+2.51%); split: -0.01%, +2.53%
Cycle count: 132557506 -> 132427302 (-0.10%); split: -0.75%, +0.65%
Spill count: 7144 -> 7234 (+1.26%); split: -0.46%, +1.72%
Fill count: 12086 -> 12403 (+2.62%); split: -0.73%, +3.35%
Scratch Memory Size: 600064 -> 604160 (+0.68%); split: -1.02%, +1.71%
Hitman3:
Totals from 4912 (97.09% of 5059) affected shaders:
Instrs: 2952124 -> 2916824 (-1.20%); split: -1.20%, +0.00%
Cycle count: 179985656 -> 189175250 (+5.11%); split: -2.44%, +7.55%
Spill count: 3739 -> 3136 (-16.13%)
Fill count: 10657 -> 9564 (-10.26%)
Scratch Memory Size: 373760 -> 318464 (-14.79%)
Max live registers: 597566 -> 589460 (-1.36%)
Hogwarts Legacy:
Totals from 1471 (96.33% of 1527) affected shaders:
Instrs: 748749 -> 766214 (+2.33%); split: -0.71%, +3.05%
Cycle count: 33301528 -> 34426308 (+3.38%); split: -1.30%, +4.68%
Spill count: 3278 -> 3070 (-6.35%); split: -8.30%, +1.95%
Fill count: 4553 -> 4097 (-10.02%); split: -10.85%, +0.83%
Scratch Memory Size: 251904 -> 217088 (-13.82%)
Max live registers: 168911 -> 168106 (-0.48%); split: -0.59%, +0.12%
Metro Exodus:
Totals from 18356 (49.81% of 36854) affected shaders:
Instrs: 7559386 -> 7621591 (+0.82%); split: -0.01%, +0.83%
Cycle count: 195240612 -> 196455186 (+0.62%); split: -1.22%, +1.84%
Spill count: 595 -> 546 (-8.24%)
Fill count: 1604 -> 1408 (-12.22%)
Max live registers: 2086937 -> 2086933 (-0.00%)
Red Dead Redemption 2:
Totals from 4171 (79.31% of 5259) affected shaders:
Instrs: 2619392 -> 2719587 (+3.83%); split: -0.00%, +3.83%
Subgroup size: 86416 -> 86432 (+0.02%)
Cycle count: 8542836160 -> 8531976886 (-0.13%); split: -0.65%, +0.53%
Fill count: 12949 -> 12970 (+0.16%); split: -0.43%, +0.59%
Scratch Memory Size: 401408 -> 385024 (-4.08%)
Spiderman Remastered:
Totals from 6639 (98.94% of 6710) affected shaders:
Instrs: 6877980 -> 6800592 (-1.13%); split: -3.11%, +1.98%
Cycle count: 282183352210 -> 282100051824 (-0.03%); split: -0.62%, +0.59%
Spill count: 63147 -> 64218 (+1.70%); split: -7.12%, +8.82%
Fill count: 184931 -> 175591 (-5.05%); split: -10.81%, +5.76%
Scratch Memory Size: 5318656 -> 5970944 (+12.26%); split: -5.91%, +18.17%
Max live registers: 918240 -> 906604 (-1.27%)
Strange Brigade:
Totals from 3675 (92.24% of 3984) affected shaders:
Instrs: 1462231 -> 1429345 (-2.25%); split: -2.25%, +0.00%
Cycle count: 37404050 -> 37345292 (-0.16%); split: -1.25%, +1.09%
Max live registers: 361849 -> 351265 (-2.92%)
Witcher 3:
Totals from 13 (46.43% of 28) affected shaders:
Instrs: 593 -> 660 (+11.30%)
Cycle count: 28302 -> 28714 (+1.46%)
Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28199>
2024-02-29 20:51:50 +02:00
|
|
|
'brw_opt_address_reg_load.cpp',
|
2024-12-29 10:01:36 -08:00
|
|
|
'brw_opt_algebraic.cpp',
|
|
|
|
|
'brw_opt_bank_conflicts.cpp',
|
|
|
|
|
'brw_opt_cmod_propagation.cpp',
|
|
|
|
|
'brw_opt_combine_constants.cpp',
|
|
|
|
|
'brw_opt_copy_propagation.cpp',
|
|
|
|
|
'brw_opt_cse.cpp',
|
|
|
|
|
'brw_opt_dead_code_eliminate.cpp',
|
|
|
|
|
'brw_opt_register_coalesce.cpp',
|
|
|
|
|
'brw_opt_saturate_propagation.cpp',
|
brw: Combine convergent texture buffer fetches into fewer loads
Borderlands 3 (both DX11 and DX12 renderers) have a common pattern
across many shaders:
con 32x4 %510 = (uint32)txf %2 (handle), %1191 (0x10) (coord), %1 (0x0) (lod), 0 (texture)
con 32x4 %512 = (uint32)txf %2 (handle), %1511 (0x11) (coord), %1 (0x0) (lod), 0 (texture)
...
con 32x4 %550 = (uint32)txf %2 (handle), %1549 (0x25) (coord), %1 (0x0) (lod), 0 (texture)
con 32x4 %552 = (uint32)txf %2 (handle), %1551 (0x26) (coord), %1 (0x0) (lod), 0 (texture)
A single basic block contains piles of texelFetches from a 1D buffer
texture, with constant coordinates. In most cases, only the .x channel
of the result is read. So we have something on the order of 28 sampler
messages, each asking for...a single uint32_t scalar value. Because our
sampler doesn't have any support for convergent block loads (like the
untyped LSC transpose messages for SSBOs)...this means we were emitting
SIMD8/16 (or SIMD16/32 on Xe2) sampler messages for every single scalar,
replicating what's effectively a SIMD1 value to the entire register.
This is hugely wasteful, both in terms of register pressure, and also in
back-and-forth sending and receiving memory messages.
The good news is we can take advantage of our explicit SIMD model to
handle this more efficiently. This patch adds a new optimization pass
that detects a series of SHADER_OPCODE_TXF_LOGICAL, in the same basic
block, with constant offsets, from the same texture. It constructs a
new divergent coordinate where each channel is one of the constants
(i.e <10, 11, 12, ..., 26> in the above example). It issues a new
NoMask divergent texel fetch which loads N useful channels in one go,
and replaces the rest with expansion MOVs that splat the SIMD1 result
back to the full SIMD width. (These get copy propagated away.)
We can pick the SIMD size of the load independently of the native shader
width as well. On Xe2, those 28 convergent loads become a single SIMD32
ld message. On earlier hardware, we use 2 SIMD16 messages. Or we can
use a smaller size when there aren't many to combine.
In fossil-db, this cuts 27% of send messages in affected shaders, 3-6%
of cycles, 2-3% of instructions, and 8-12% of live registers. On A770,
this improves performance of Borderlands 3 by roughly 2.5-3.5%.
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32573>
2024-12-09 13:25:18 -08:00
|
|
|
'brw_opt_txf_combiner.cpp',
|
2024-12-29 10:01:36 -08:00
|
|
|
'brw_opt_virtual_grfs.cpp',
|
2017-09-14 17:57:17 -07:00
|
|
|
'brw_packed_float.c',
|
2024-07-12 16:20:55 -07:00
|
|
|
'brw_print.cpp',
|
2022-06-29 15:19:57 -07:00
|
|
|
'brw_prim.h',
|
2021-10-06 22:37:42 -07:00
|
|
|
'brw_private.h',
|
2024-12-06 23:36:12 -08:00
|
|
|
'brw_reg.cpp',
|
2017-09-14 17:57:17 -07:00
|
|
|
'brw_reg.h',
|
2025-01-19 08:53:33 -08:00
|
|
|
'brw_reg_allocate.cpp',
|
2017-09-14 17:57:17 -07:00
|
|
|
'brw_reg_type.c',
|
|
|
|
|
'brw_reg_type.h',
|
2020-08-06 12:53:47 -05:00
|
|
|
'brw_rt.h',
|
2017-09-14 17:57:17 -07:00
|
|
|
'brw_schedule_instructions.cpp',
|
2025-02-05 14:25:15 -08:00
|
|
|
'brw_shader.cpp',
|
|
|
|
|
'brw_shader.h',
|
2022-11-07 17:35:16 -08:00
|
|
|
'brw_simd_selection.cpp',
|
2025-01-14 15:23:18 +02:00
|
|
|
'brw_spirv.c',
|
2024-12-06 22:13:36 -08:00
|
|
|
'brw_thread_payload.cpp',
|
|
|
|
|
'brw_thread_payload.h',
|
2024-12-29 17:39:39 -08:00
|
|
|
'brw_validate.cpp',
|
2017-09-14 17:57:17 -07:00
|
|
|
'brw_vue_map.c',
|
2024-12-29 10:01:36 -08:00
|
|
|
'brw_workaround.cpp',
|
2017-09-14 17:57:17 -07:00
|
|
|
)
|
|
|
|
|
|
2024-02-09 15:30:57 -08:00
|
|
|
brw_device_sha1_gen_src = custom_target('brw_device_sha1_gen.c',
|
|
|
|
|
input : ['brw_device_sha1_gen_c.py', '../dev/intel_device_info.py'],
|
|
|
|
|
output : ['brw_device_sha1_gen.c'],
|
|
|
|
|
command : [prog_python, '@INPUT0@', '--outdir', meson.current_build_dir()])
|
|
|
|
|
|
|
|
|
|
|
intel/brw: Handle fsign optimization in a NIR algebraic pass
This is a lot less code, and it makes it easier to experiment with other
pattern-based optimizations in the future.
The results here are nearly identical to the results I got from Ken's
"intel/brw: Make fsign (for 16/32-bit) in SSA form"... which are not
particularly good.
In this commit and in Ken's, all of the shader-db shaders hurt for
spills and fills are from Deus Ex Mankind Divided. Each shader has a
bunch of texture instructions with a single fsign between the
blocks. With the dependency on the flag removed, the scheduler puts all
of the texture instructions at the start... and there are a LOT of them.
shader-db:
All Intel platforms had similar results. (Meteor Lake shown)
total instructions in shared programs: 19647060 -> 19650207 (0.02%)
instructions in affected programs: 734718 -> 737865 (0.43%)
helped: 382 / HURT: 1984
total cycles in shared programs: 823238442 -> 822785913 (-0.05%)
cycles in affected programs: 426901157 -> 426448628 (-0.11%)
helped: 3408 / HURT: 3671
total spills in shared programs: 3887 -> 3891 (0.10%)
spills in affected programs: 256 -> 260 (1.56%)
helped: 0 / HURT: 4
total fills in shared programs: 3236 -> 3306 (2.16%)
fills in affected programs: 882 -> 952 (7.94%)
helped: 0 / HURT: 12
LOST: 37
GAINED: 34
fossil-db:
DG2 and Meteor Lake had similar results. (Meteor Lake shown)
Totals:
Instrs: 154005469 -> 154008294 (+0.00%); split: -0.00%, +0.00%
Cycle count: 17551859277 -> 17554293955 (+0.01%); split: -0.02%, +0.04%
Spill count: 142078 -> 142090 (+0.01%)
Fill count: 266761 -> 266729 (-0.01%); split: -0.02%, +0.01%
Max live registers: 32593578 -> 32593858 (+0.00%)
Max dispatch width: 5535944 -> 5536816 (+0.02%); split: +0.02%, -0.01%
Totals from 5867 (0.93% of 631350) affected shaders:
Instrs: 5475544 -> 5478369 (+0.05%); split: -0.04%, +0.09%
Cycle count: 1649032029 -> 1651466707 (+0.15%); split: -0.24%, +0.39%
Spill count: 26411 -> 26423 (+0.05%)
Fill count: 57364 -> 57332 (-0.06%); split: -0.10%, +0.04%
Max live registers: 431561 -> 431841 (+0.06%)
Max dispatch width: 49784 -> 50656 (+1.75%); split: +2.38%, -0.63%
Tiger Lake
Totals:
Instrs: 149530671 -> 149533588 (+0.00%); split: -0.00%, +0.00%
Cycle count: 15261418953 -> 15264764921 (+0.02%); split: -0.00%, +0.03%
Spill count: 60317 -> 60316 (-0.00%); split: -0.02%, +0.01%
Max live registers: 32249201 -> 32249464 (+0.00%)
Max dispatch width: 5540608 -> 5540584 (-0.00%)
Totals from 5862 (0.93% of 630309) affected shaders:
Instrs: 4740800 -> 4743717 (+0.06%); split: -0.04%, +0.10%
Cycle count: 566531248 -> 569877216 (+0.59%); split: -0.13%, +0.72%
Spill count: 11709 -> 11708 (-0.01%); split: -0.09%, +0.08%
Max live registers: 424560 -> 424823 (+0.06%)
Max dispatch width: 50304 -> 50280 (-0.05%)
Ice Lake
Totals:
Instrs: 150499705 -> 150502608 (+0.00%); split: -0.00%, +0.00%
Cycle count: 15105629116 -> 15105425880 (-0.00%); split: -0.00%, +0.00%
Spill count: 60087 -> 60090 (+0.00%)
Fill count: 100542 -> 100541 (-0.00%); split: -0.00%, +0.00%
Max live registers: 32605215 -> 32605495 (+0.00%)
Max dispatch width: 5617752 -> 5617792 (+0.00%); split: +0.00%, -0.00%
Totals from 5882 (0.93% of 634934) affected shaders:
Instrs: 4737206 -> 4740109 (+0.06%); split: -0.04%, +0.10%
Cycle count: 598882104 -> 598678868 (-0.03%); split: -0.08%, +0.05%
Spill count: 10278 -> 10281 (+0.03%)
Fill count: 22504 -> 22503 (-0.00%); split: -0.01%, +0.01%
Max live registers: 424184 -> 424464 (+0.07%)
Max dispatch width: 50216 -> 50256 (+0.08%); split: +0.25%, -0.18%
Skylake
Totals:
Instrs: 139092612 -> 139095257 (+0.00%); split: -0.00%, +0.00%
Cycle count: 14533550285 -> 14533544716 (-0.00%); split: -0.00%, +0.00%
Spill count: 58176 -> 58172 (-0.01%)
Fill count: 95877 -> 95796 (-0.08%)
Max live registers: 31924594 -> 31924874 (+0.00%)
Max dispatch width: 5484568 -> 5484552 (-0.00%); split: +0.00%, -0.00%
Totals from 5789 (0.93% of 625512) affected shaders:
Instrs: 4481987 -> 4484632 (+0.06%); split: -0.04%, +0.10%
Cycle count: 578310124 -> 578304555 (-0.00%); split: -0.05%, +0.05%
Spill count: 9248 -> 9244 (-0.04%)
Fill count: 19677 -> 19596 (-0.41%)
Max live registers: 415340 -> 415620 (+0.07%)
Max dispatch width: 49720 -> 49704 (-0.03%); split: +0.10%, -0.13%
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095>
2024-05-01 21:02:13 -07:00
|
|
|
brw_nir_lower_fsign = custom_target(
|
|
|
|
|
'brw_nir_lower_fsign.c',
|
|
|
|
|
input : 'brw_nir_lower_fsign.py',
|
|
|
|
|
output : 'brw_nir_lower_fsign.c',
|
|
|
|
|
command : [
|
|
|
|
|
prog_python, '@INPUT@', '-p', dir_compiler_nir,
|
|
|
|
|
],
|
|
|
|
|
depend_files : nir_algebraic_depends,
|
|
|
|
|
capture : true,
|
|
|
|
|
)
|
|
|
|
|
|
2017-09-14 17:57:17 -07:00
|
|
|
brw_nir_trig = custom_target(
|
|
|
|
|
'brw_nir_trig_workarounds.c',
|
|
|
|
|
input : 'brw_nir_trig_workarounds.py',
|
|
|
|
|
output : 'brw_nir_trig_workarounds.c',
|
2017-12-11 15:56:08 -08:00
|
|
|
command : [
|
2022-08-10 02:04:51 +03:00
|
|
|
prog_python, '@INPUT@', '-p', dir_compiler_nir,
|
2017-12-11 15:56:08 -08:00
|
|
|
],
|
2022-02-16 14:02:16 -08:00
|
|
|
depend_files : nir_algebraic_depends,
|
2017-09-14 17:57:17 -07:00
|
|
|
capture : true,
|
|
|
|
|
)
|
|
|
|
|
|
2024-02-09 15:37:14 -08:00
|
|
|
libintel_compiler_brw = static_library(
|
2017-09-14 17:57:17 -07:00
|
|
|
'intel_compiler',
|
intel/brw: Handle fsign optimization in a NIR algebraic pass
This is a lot less code, and it makes it easier to experiment with other
pattern-based optimizations in the future.
The results here are nearly identical to the results I got from Ken's
"intel/brw: Make fsign (for 16/32-bit) in SSA form"... which are not
particularly good.
In this commit and in Ken's, all of the shader-db shaders hurt for
spills and fills are from Deus Ex Mankind Divided. Each shader has a
bunch of texture instructions with a single fsign between the
blocks. With the dependency on the flag removed, the scheduler puts all
of the texture instructions at the start... and there are a LOT of them.
shader-db:
All Intel platforms had similar results. (Meteor Lake shown)
total instructions in shared programs: 19647060 -> 19650207 (0.02%)
instructions in affected programs: 734718 -> 737865 (0.43%)
helped: 382 / HURT: 1984
total cycles in shared programs: 823238442 -> 822785913 (-0.05%)
cycles in affected programs: 426901157 -> 426448628 (-0.11%)
helped: 3408 / HURT: 3671
total spills in shared programs: 3887 -> 3891 (0.10%)
spills in affected programs: 256 -> 260 (1.56%)
helped: 0 / HURT: 4
total fills in shared programs: 3236 -> 3306 (2.16%)
fills in affected programs: 882 -> 952 (7.94%)
helped: 0 / HURT: 12
LOST: 37
GAINED: 34
fossil-db:
DG2 and Meteor Lake had similar results. (Meteor Lake shown)
Totals:
Instrs: 154005469 -> 154008294 (+0.00%); split: -0.00%, +0.00%
Cycle count: 17551859277 -> 17554293955 (+0.01%); split: -0.02%, +0.04%
Spill count: 142078 -> 142090 (+0.01%)
Fill count: 266761 -> 266729 (-0.01%); split: -0.02%, +0.01%
Max live registers: 32593578 -> 32593858 (+0.00%)
Max dispatch width: 5535944 -> 5536816 (+0.02%); split: +0.02%, -0.01%
Totals from 5867 (0.93% of 631350) affected shaders:
Instrs: 5475544 -> 5478369 (+0.05%); split: -0.04%, +0.09%
Cycle count: 1649032029 -> 1651466707 (+0.15%); split: -0.24%, +0.39%
Spill count: 26411 -> 26423 (+0.05%)
Fill count: 57364 -> 57332 (-0.06%); split: -0.10%, +0.04%
Max live registers: 431561 -> 431841 (+0.06%)
Max dispatch width: 49784 -> 50656 (+1.75%); split: +2.38%, -0.63%
Tiger Lake
Totals:
Instrs: 149530671 -> 149533588 (+0.00%); split: -0.00%, +0.00%
Cycle count: 15261418953 -> 15264764921 (+0.02%); split: -0.00%, +0.03%
Spill count: 60317 -> 60316 (-0.00%); split: -0.02%, +0.01%
Max live registers: 32249201 -> 32249464 (+0.00%)
Max dispatch width: 5540608 -> 5540584 (-0.00%)
Totals from 5862 (0.93% of 630309) affected shaders:
Instrs: 4740800 -> 4743717 (+0.06%); split: -0.04%, +0.10%
Cycle count: 566531248 -> 569877216 (+0.59%); split: -0.13%, +0.72%
Spill count: 11709 -> 11708 (-0.01%); split: -0.09%, +0.08%
Max live registers: 424560 -> 424823 (+0.06%)
Max dispatch width: 50304 -> 50280 (-0.05%)
Ice Lake
Totals:
Instrs: 150499705 -> 150502608 (+0.00%); split: -0.00%, +0.00%
Cycle count: 15105629116 -> 15105425880 (-0.00%); split: -0.00%, +0.00%
Spill count: 60087 -> 60090 (+0.00%)
Fill count: 100542 -> 100541 (-0.00%); split: -0.00%, +0.00%
Max live registers: 32605215 -> 32605495 (+0.00%)
Max dispatch width: 5617752 -> 5617792 (+0.00%); split: +0.00%, -0.00%
Totals from 5882 (0.93% of 634934) affected shaders:
Instrs: 4737206 -> 4740109 (+0.06%); split: -0.04%, +0.10%
Cycle count: 598882104 -> 598678868 (-0.03%); split: -0.08%, +0.05%
Spill count: 10278 -> 10281 (+0.03%)
Fill count: 22504 -> 22503 (-0.00%); split: -0.01%, +0.01%
Max live registers: 424184 -> 424464 (+0.07%)
Max dispatch width: 50216 -> 50256 (+0.08%); split: +0.25%, -0.18%
Skylake
Totals:
Instrs: 139092612 -> 139095257 (+0.00%); split: -0.00%, +0.00%
Cycle count: 14533550285 -> 14533544716 (-0.00%); split: -0.00%, +0.00%
Spill count: 58176 -> 58172 (-0.01%)
Fill count: 95877 -> 95796 (-0.08%)
Max live registers: 31924594 -> 31924874 (+0.00%)
Max dispatch width: 5484568 -> 5484552 (-0.00%); split: +0.00%, -0.00%
Totals from 5789 (0.93% of 625512) affected shaders:
Instrs: 4481987 -> 4484632 (+0.06%); split: -0.04%, +0.10%
Cycle count: 578310124 -> 578304555 (-0.00%); split: -0.05%, +0.05%
Spill count: 9248 -> 9244 (-0.04%)
Fill count: 19677 -> 19596 (-0.41%)
Max live registers: 415340 -> 415620 (+0.07%)
Max dispatch width: 49720 -> 49704 (-0.03%); split: +0.10%, -0.13%
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095>
2024-05-01 21:02:13 -07:00
|
|
|
[libintel_compiler_brw_files, intel_nir_files, brw_nir_lower_fsign, brw_nir_trig, ir_expression_operation_h, [brw_device_sha1_gen_src]],
|
2023-08-02 19:24:14 +08:00
|
|
|
include_directories : [inc_include, inc_src, inc_intel],
|
2020-04-24 13:10:41 -07:00
|
|
|
c_args : [no_override_init_args],
|
2025-01-08 22:56:08 -08:00
|
|
|
cpp_args : ['-Werror=vla'],
|
2020-04-24 13:10:41 -07:00
|
|
|
gnu_symbol_visibility : 'hidden',
|
2023-02-15 10:09:57 -08:00
|
|
|
dependencies : [idep_nir_headers, idep_mesautil, idep_intel_dev],
|
2017-09-14 17:57:17 -07:00
|
|
|
build_by_default : false,
|
|
|
|
|
)
|
|
|
|
|
|
2024-02-28 17:38:04 -08:00
|
|
|
idep_intel_compiler_brw = declare_dependency(
|
2023-04-10 13:28:48 +03:00
|
|
|
link_with : [libintel_compiler_brw, libisl],
|
2024-02-28 17:41:46 -08:00
|
|
|
dependencies : [
|
|
|
|
|
idep_nir,
|
2024-06-06 16:09:00 +01:00
|
|
|
idep_mesautil,
|
2025-01-14 15:23:18 +02:00
|
|
|
idep_vtn,
|
2024-02-28 17:41:46 -08:00
|
|
|
],
|
2024-02-28 17:38:04 -08:00
|
|
|
)
|
|
|
|
|
|
2017-09-14 17:57:17 -07:00
|
|
|
if with_tests
|
2021-10-11 23:27:53 -07:00
|
|
|
test(
|
2024-02-09 15:37:14 -08:00
|
|
|
'intel_compiler_brw_tests',
|
2021-10-11 23:27:53 -07:00
|
|
|
executable(
|
2024-02-09 15:37:14 -08:00
|
|
|
'intel_compiler_brw_tests',
|
2021-10-11 23:27:53 -07:00
|
|
|
files(
|
|
|
|
|
'test_eu_compact.cpp',
|
|
|
|
|
'test_eu_validate.cpp',
|
brw: Simplify the test code for brw passes
The key change is to use a builder to write the expected shader result
and compare that. To make this less error prone, a few helper functions
were added
- a way to allocate VGRFs from both shaders in parallel, that way the
same brw_reg can be used in both of them;
- assertions that a pass will make progress or not, and proper output
when the unexpected happens;
- use a common brw_shader_pass_test class so to collect some of the helpers;
- make some helpers work directly with builder.
The idea is to improve the signal in tests, so that the disasm comments
are not necessary anymore. For example
```
TEST_F(saturate_propagation_test, basic)
{
brw_reg dst1 = bld.vgrf(BRW_TYPE_F);
brw_reg src0 = bld.vgrf(BRW_TYPE_F);
brw_reg src1 = bld.vgrf(BRW_TYPE_F);
brw_reg dst0 = bld.ADD(src0, src1);
set_saturate(true, bld.MOV(dst1, dst0));
/* = Before =
*
* 0: add(16) dst0 src0 src1
* 1: mov.sat(16) dst1 dst0
*
* = After =
* 0: add.sat(16) dst0 src0 src1
* 1: mov(16) dst1 dst0
*/
brw_calculate_cfg(*v);
bblock_t *block0 = v->cfg->blocks[0];
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
EXPECT_TRUE(saturate_propagation(v));
EXPECT_EQ(0, block0->start_ip);
EXPECT_EQ(1, block0->end_ip);
EXPECT_EQ(BRW_OPCODE_ADD, instruction(block0, 0)->opcode);
EXPECT_TRUE(instruction(block0, 0)->saturate);
EXPECT_EQ(BRW_OPCODE_MOV, instruction(block0, 1)->opcode);
EXPECT_FALSE(instruction(block0, 1)->saturate);
}
```
becomes
```
TEST_F(saturate_propagation_test, basic)
{
brw_builder bld = make_shader(MESA_SHADER_FRAGMENT, 16);
brw_builder exp = make_shader(MESA_SHADER_FRAGMENT, 16);
brw_reg dst0 = vgrf(bld, exp, BRW_TYPE_F);
brw_reg dst1 = vgrf(bld, exp, BRW_TYPE_F);
brw_reg src0 = vgrf(bld, exp, BRW_TYPE_F);
brw_reg src1 = vgrf(bld, exp, BRW_TYPE_F);
bld.ADD(dst0, src0, src1);
bld.MOV(dst1, dst0)->saturate = true;
EXPECT_PROGRESS(brw_opt_saturate_propagation, bld);
exp.ADD(dst0, src0, src1)->saturate = true;
exp.MOV(dst1, dst0);
EXPECT_SHADERS_MATCH(bld, exp);
}
```
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33936>
2025-03-05 16:58:32 -08:00
|
|
|
'test_helpers.cpp',
|
|
|
|
|
'test_helpers.h',
|
brw: Add passes to generate and lower load_reg
v2: Add support for WE_all instructions... this already just worked, so
I only had to delete the check and the FINISHME comment.
v3: Use logic more like def_analysis::update_for_reads to determine when
to not insert LOAD_REG instructions. Based on a suggestion by Ken.
v4: Eliminate "store" from all the names since STORE_REG does not exist
anymore. Fold insert_load_reg into brw_insert_load_reg. Elminate extra
call to s.def_analysis.require() after progress. Pull a loop-invariant
check out of the inst->srouces loop. Drop call to
brw_opt_split_virtual_grfs after lowering load_reg. All suggested by
Caio.
v5: Assert that LOAD_REG doesn't already exist in
brw_insert_load_reg. Update comment before fully_defines. Both
suggested by Caio.
v6: Don't explicitly special-case SHADER_OPCODE_MEMORY_STORE_LOGICAL.
Move the inst->dst.file != VGRF check earlier to avoid the loop over
sources. Both suggested by Ken. Move the call the brw_insert_load_reg
a little bit later, and explain why it's at that location. Suggested
by Caio.
v7: Many changes to the for-each-source loop in brw_insert_load_reg.
Removes incorrect multiplication of s.alloc.sizes with reg_unit. Adds
checks for matching SIMD size and NoMask in the search for pre-existing
LOAD_REG of same value.
v8: Add some unit tests. Suggested by Caio.
shader-db:
Lunar Lake
total instructions in shared programs: 16923237 -> 16921895 (<.01%)
instructions in affected programs: 450565 -> 449223 (-0.30%)
helped: 251 / HURT: 377
total cycles in shared programs: 910428418 -> 889920590 (-2.25%)
cycles in affected programs: 719248184 -> 698740356 (-2.85%)
helped: 9076 / HURT: 9082
total fills in shared programs: 2242 -> 2218 (-1.07%)
fills in affected programs: 116 -> 92 (-20.69%)
helped: 2 / HURT: 0
total sends in shared programs: 848635 -> 848421 (-0.03%)
sends in affected programs: 810 -> 596 (-26.42%)
helped: 10 / HURT: 0
LOST: 82
GAINED: 78
Meteor Lake and DG2 had similar results. (Meteor Lake shown)
total instructions in shared programs: 19875784 -> 19871694 (-0.02%)
instructions in affected programs: 1050091 -> 1046001 (-0.39%)
helped: 251 / HURT: 2403
total cycles in shared programs: 905328238 -> 882446458 (-2.53%)
cycles in affected programs: 682736344 -> 659854564 (-3.35%)
helped: 7869 / HURT: 7911
total spills in shared programs: 5512 -> 5032 (-8.71%)
spills in affected programs: 1830 -> 1350 (-26.23%)
helped: 8 / HURT: 0
total fills in shared programs: 5648 -> 4782 (-15.33%)
fills in affected programs: 3312 -> 2446 (-26.15%)
helped: 8 / HURT: 0
total sends in shared programs: 1032942 -> 1032722 (-0.02%)
sends in affected programs: 572 -> 352 (-38.46%)
helped: 10 / HURT: 0
LOST: 138
GAINED: 53
Tiger Lake
total instructions in shared programs: 19711930 -> 19715591 (0.02%)
instructions in affected programs: 1040623 -> 1044284 (0.35%)
helped: 317 / HURT: 2474
total cycles in shared programs: 862988990 -> 860573870 (-0.28%)
cycles in affected programs: 612392461 -> 609977341 (-0.39%)
helped: 7447 / HURT: 7686
total sends in shared programs: 1034763 -> 1034555 (-0.02%)
sends in affected programs: 784 -> 576 (-26.53%)
helped: 8 / HURT: 0
LOST: 56
GAINED: 143
Ice Lake and Skylake had similar results. (Ice Lake shown)
total instructions in shared programs: 20545461 -> 20545220 (<.01%)
instructions in affected programs: 422405 -> 422164 (-0.06%)
helped: 180 / HURT: 459
total cycles in shared programs: 872697345 -> 866874523 (-0.67%)
cycles in affected programs: 573117917 -> 567295095 (-1.02%)
helped: 6783 / HURT: 6980
total spills in shared programs: 4335 -> 4336 (0.02%)
spills in affected programs: 90 -> 91 (1.11%)
helped: 1 / HURT: 2
total fills in shared programs: 4194 -> 4196 (0.05%)
fills in affected programs: 463 -> 465 (0.43%)
helped: 1 / HURT: 2
total sends in shared programs: 1079446 -> 1079238 (-0.02%)
sends in affected programs: 784 -> 576 (-26.53%)
helped: 8 / HURT: 0
LOST: 117
GAINED: 37
fossil-db:
All Intel platforms had similar results. (Lunar Lake shown)
Totals:
Instrs: 209708136 -> 209695617 (-0.01%); split: -0.02%, +0.01%
Send messages: 10927753 -> 10927640 (-0.00%)
Cycle count: 30540172048 -> 30427084732 (-0.37%); split: -0.99%, +0.62%
Spill count: 511621 -> 510932 (-0.13%); split: -0.22%, +0.08%
Fill count: 621166 -> 618440 (-0.44%); split: -0.56%, +0.12%
Scratch Memory Size: 35574784 -> 35648512 (+0.21%); split: -0.06%, +0.26%
Max live registers: 65453860 -> 65453140 (-0.00%); split: -0.00%, +0.00%
Non SSA regs after NIR: 75374990 -> 35195764 (-53.31%)
Totals from 503284 (71.25% of 706391) affected shaders:
Instrs: 180203778 -> 180191259 (-0.01%); split: -0.02%, +0.01%
Send messages: 9699732 -> 9699619 (-0.00%)
Cycle count: 30080349592 -> 29967262276 (-0.38%); split: -1.01%, +0.63%
Spill count: 511584 -> 510895 (-0.13%); split: -0.22%, +0.08%
Fill count: 621120 -> 618394 (-0.44%); split: -0.56%, +0.12%
Scratch Memory Size: 35443712 -> 35517440 (+0.21%); split: -0.06%, +0.27%
Max live registers: 52566092 -> 52565372 (-0.00%); split: -0.01%, +0.00%
Non SSA regs after NIR: 70110949 -> 29931723 (-57.31%)
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/31497>
2024-09-18 18:11:13 -07:00
|
|
|
'test_insert_load_reg.cpp',
|
2024-12-29 10:01:36 -08:00
|
|
|
'test_lower_scoreboard.cpp',
|
2025-03-10 11:24:18 -07:00
|
|
|
'test_opt_algebraic.cpp',
|
2024-12-29 10:01:36 -08:00
|
|
|
'test_opt_cmod_propagation.cpp',
|
|
|
|
|
'test_opt_combine_constants.cpp',
|
|
|
|
|
'test_opt_copy_propagation.cpp',
|
|
|
|
|
'test_opt_cse.cpp',
|
2025-03-27 19:48:13 -07:00
|
|
|
'test_opt_register_coalesce.cpp',
|
2024-12-29 10:01:36 -08:00
|
|
|
'test_opt_saturate_propagation.cpp',
|
2021-10-06 22:37:42 -07:00
|
|
|
'test_simd_selection.cpp',
|
2021-10-11 23:27:53 -07:00
|
|
|
'test_vf_float_conversions.cpp',
|
2018-11-19 13:44:15 -08:00
|
|
|
),
|
2021-10-11 23:27:53 -07:00
|
|
|
ir_expression_operation_h,
|
2023-08-02 19:24:14 +08:00
|
|
|
include_directories : [inc_include, inc_src, inc_intel],
|
2025-01-08 22:56:08 -08:00
|
|
|
cpp_args : ['-Werror=vla'],
|
2024-05-10 22:40:52 +03:00
|
|
|
link_with : libisl,
|
2024-02-28 17:38:04 -08:00
|
|
|
dependencies : [idep_gtest, idep_nir, idep_mesautil, idep_intel_dev,
|
|
|
|
|
idep_intel_compiler_brw],
|
2021-10-11 23:27:53 -07:00
|
|
|
),
|
|
|
|
|
suite : ['intel'],
|
2023-02-23 10:49:37 +00:00
|
|
|
protocol : 'gtest',
|
2021-10-11 23:27:53 -07:00
|
|
|
)
|
2017-09-14 17:57:17 -07:00
|
|
|
endif
|
2024-02-09 13:55:14 -08:00
|
|
|
|
|
|
|
|
if with_intel_tools
|
|
|
|
|
|
|
|
|
|
bison_command = []
|
|
|
|
|
if yacc_is_bison
|
|
|
|
|
bison_command = [
|
|
|
|
|
prog_bison, '@INPUT@', '--defines=@OUTPUT1@',
|
|
|
|
|
'--output=@OUTPUT0@'
|
|
|
|
|
]
|
|
|
|
|
else
|
|
|
|
|
bison_command = [
|
|
|
|
|
prog_bison, '-H', '@OUTPUT1@',
|
|
|
|
|
'-o', '@OUTPUT0@', '@INPUT@'
|
|
|
|
|
]
|
|
|
|
|
endif
|
|
|
|
|
|
|
|
|
|
brw_gram_tab = custom_target(
|
|
|
|
|
'brw_gram.tab.[ch]',
|
|
|
|
|
input : 'brw_gram.y',
|
|
|
|
|
output : ['brw_gram.tab.c', 'brw_gram.tab.h'],
|
|
|
|
|
command : bison_command
|
|
|
|
|
)
|
|
|
|
|
|
|
|
|
|
brw_lex_yy_c = custom_target(
|
|
|
|
|
'brw_lex.yy.c',
|
|
|
|
|
input : 'brw_lex.l',
|
|
|
|
|
output : 'brw_lex.yy.c',
|
|
|
|
|
command : [prog_flex, '-o', '@OUTPUT@', '@INPUT@']
|
|
|
|
|
)
|
|
|
|
|
|
2024-07-02 11:57:39 -07:00
|
|
|
brw_asm_deps = [
|
|
|
|
|
dep_thread,
|
|
|
|
|
idep_intel_compiler_brw,
|
|
|
|
|
idep_intel_dev,
|
|
|
|
|
idep_mesautil,
|
|
|
|
|
]
|
|
|
|
|
|
|
|
|
|
brw_asm = static_library(
|
|
|
|
|
'brw_asm',
|
|
|
|
|
['brw_asm.c', brw_gram_tab[0], brw_gram_tab[1], brw_lex_yy_c],
|
|
|
|
|
dependencies : brw_asm_deps,
|
|
|
|
|
include_directories : [inc_include, inc_src, inc_intel],
|
|
|
|
|
c_args : [no_override_init_args],
|
|
|
|
|
gnu_symbol_visibility : 'hidden',
|
|
|
|
|
build_by_default : false,
|
|
|
|
|
)
|
|
|
|
|
|
|
|
|
|
idep_brw_asm = declare_dependency(
|
|
|
|
|
link_with : brw_asm,
|
|
|
|
|
dependencies : brw_asm_deps,
|
|
|
|
|
)
|
|
|
|
|
|
2024-02-09 13:55:14 -08:00
|
|
|
brw_asm_tool = executable(
|
|
|
|
|
'brw_asm',
|
2024-07-02 11:57:39 -07:00
|
|
|
['brw_asm_tool.c'],
|
|
|
|
|
dependencies : idep_brw_asm,
|
2024-02-09 13:55:14 -08:00
|
|
|
include_directories : [inc_include, inc_src, inc_intel],
|
|
|
|
|
c_args : [no_override_init_args],
|
|
|
|
|
gnu_symbol_visibility : 'hidden',
|
|
|
|
|
install : true
|
|
|
|
|
)
|
|
|
|
|
|
|
|
|
|
asm_testcases = [
|
|
|
|
|
['skl', 'gfx9'],
|
|
|
|
|
['icl', 'gfx11'],
|
|
|
|
|
['tgl', 'gfx12'],
|
|
|
|
|
['dg2', 'gfx12.5'],
|
|
|
|
|
]
|
|
|
|
|
|
|
|
|
|
test_runner = find_program('tests/run-test.py')
|
|
|
|
|
foreach testcase : asm_testcases
|
|
|
|
|
_gen_name = testcase[0]
|
|
|
|
|
_gen_num = testcase[1]
|
|
|
|
|
_gen_folder = join_paths(meson.current_source_dir(), 'tests',
|
|
|
|
|
_gen_num.replace('gfx', 'gen'))
|
|
|
|
|
test(
|
|
|
|
|
'brw_asm_' + _gen_num, test_runner,
|
|
|
|
|
args : [
|
|
|
|
|
'--brw_asm', brw_asm_tool,
|
|
|
|
|
'--gen_name', _gen_name,
|
|
|
|
|
'--gen_folder', _gen_folder,
|
|
|
|
|
],
|
|
|
|
|
suite : 'intel',
|
|
|
|
|
)
|
|
|
|
|
endforeach
|
|
|
|
|
|
|
|
|
|
brw_disasm_tool = executable(
|
|
|
|
|
'brw_disasm',
|
|
|
|
|
files('brw_disasm_tool.c'),
|
2024-02-28 17:38:04 -08:00
|
|
|
dependencies : [idep_mesautil, dep_thread, idep_intel_dev,
|
|
|
|
|
idep_intel_compiler_brw],
|
2024-02-09 13:55:14 -08:00
|
|
|
include_directories : [inc_include, inc_src, inc_intel],
|
|
|
|
|
c_args : [no_override_init_args],
|
|
|
|
|
gnu_symbol_visibility : 'hidden',
|
|
|
|
|
install : true
|
|
|
|
|
)
|
|
|
|
|
|
|
|
|
|
endif
|
|
|
|
|
|
2025-01-15 11:18:24 -08:00
|
|
|
if with_intel_elk
|
|
|
|
|
subdir('elk')
|
|
|
|
|
else
|
|
|
|
|
idep_intel_compiler_elk = null_dep
|
|
|
|
|
endif
|