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intel/brw: Handle fsign optimization in a NIR algebraic pass
This is a lot less code, and it makes it easier to experiment with other pattern-based optimizations in the future. The results here are nearly identical to the results I got from Ken's "intel/brw: Make fsign (for 16/32-bit) in SSA form"... which are not particularly good. In this commit and in Ken's, all of the shader-db shaders hurt for spills and fills are from Deus Ex Mankind Divided. Each shader has a bunch of texture instructions with a single fsign between the blocks. With the dependency on the flag removed, the scheduler puts all of the texture instructions at the start... and there are a LOT of them. shader-db: All Intel platforms had similar results. (Meteor Lake shown) total instructions in shared programs: 19647060 -> 19650207 (0.02%) instructions in affected programs: 734718 -> 737865 (0.43%) helped: 382 / HURT: 1984 total cycles in shared programs: 823238442 -> 822785913 (-0.05%) cycles in affected programs: 426901157 -> 426448628 (-0.11%) helped: 3408 / HURT: 3671 total spills in shared programs: 3887 -> 3891 (0.10%) spills in affected programs: 256 -> 260 (1.56%) helped: 0 / HURT: 4 total fills in shared programs: 3236 -> 3306 (2.16%) fills in affected programs: 882 -> 952 (7.94%) helped: 0 / HURT: 12 LOST: 37 GAINED: 34 fossil-db: DG2 and Meteor Lake had similar results. (Meteor Lake shown) Totals: Instrs: 154005469 -> 154008294 (+0.00%); split: -0.00%, +0.00% Cycle count: 17551859277 -> 17554293955 (+0.01%); split: -0.02%, +0.04% Spill count: 142078 -> 142090 (+0.01%) Fill count: 266761 -> 266729 (-0.01%); split: -0.02%, +0.01% Max live registers: 32593578 -> 32593858 (+0.00%) Max dispatch width: 5535944 -> 5536816 (+0.02%); split: +0.02%, -0.01% Totals from 5867 (0.93% of 631350) affected shaders: Instrs: 5475544 -> 5478369 (+0.05%); split: -0.04%, +0.09% Cycle count: 1649032029 -> 1651466707 (+0.15%); split: -0.24%, +0.39% Spill count: 26411 -> 26423 (+0.05%) Fill count: 57364 -> 57332 (-0.06%); split: -0.10%, +0.04% Max live registers: 431561 -> 431841 (+0.06%) Max dispatch width: 49784 -> 50656 (+1.75%); split: +2.38%, -0.63% Tiger Lake Totals: Instrs: 149530671 -> 149533588 (+0.00%); split: -0.00%, +0.00% Cycle count: 15261418953 -> 15264764921 (+0.02%); split: -0.00%, +0.03% Spill count: 60317 -> 60316 (-0.00%); split: -0.02%, +0.01% Max live registers: 32249201 -> 32249464 (+0.00%) Max dispatch width: 5540608 -> 5540584 (-0.00%) Totals from 5862 (0.93% of 630309) affected shaders: Instrs: 4740800 -> 4743717 (+0.06%); split: -0.04%, +0.10% Cycle count: 566531248 -> 569877216 (+0.59%); split: -0.13%, +0.72% Spill count: 11709 -> 11708 (-0.01%); split: -0.09%, +0.08% Max live registers: 424560 -> 424823 (+0.06%) Max dispatch width: 50304 -> 50280 (-0.05%) Ice Lake Totals: Instrs: 150499705 -> 150502608 (+0.00%); split: -0.00%, +0.00% Cycle count: 15105629116 -> 15105425880 (-0.00%); split: -0.00%, +0.00% Spill count: 60087 -> 60090 (+0.00%) Fill count: 100542 -> 100541 (-0.00%); split: -0.00%, +0.00% Max live registers: 32605215 -> 32605495 (+0.00%) Max dispatch width: 5617752 -> 5617792 (+0.00%); split: +0.00%, -0.00% Totals from 5882 (0.93% of 634934) affected shaders: Instrs: 4737206 -> 4740109 (+0.06%); split: -0.04%, +0.10% Cycle count: 598882104 -> 598678868 (-0.03%); split: -0.08%, +0.05% Spill count: 10278 -> 10281 (+0.03%) Fill count: 22504 -> 22503 (-0.00%); split: -0.01%, +0.01% Max live registers: 424184 -> 424464 (+0.07%) Max dispatch width: 50216 -> 50256 (+0.08%); split: +0.25%, -0.18% Skylake Totals: Instrs: 139092612 -> 139095257 (+0.00%); split: -0.00%, +0.00% Cycle count: 14533550285 -> 14533544716 (-0.00%); split: -0.00%, +0.00% Spill count: 58176 -> 58172 (-0.01%) Fill count: 95877 -> 95796 (-0.08%) Max live registers: 31924594 -> 31924874 (+0.00%) Max dispatch width: 5484568 -> 5484552 (-0.00%); split: +0.00%, -0.00% Totals from 5789 (0.93% of 625512) affected shaders: Instrs: 4481987 -> 4484632 (+0.06%); split: -0.04%, +0.10% Cycle count: 578310124 -> 578304555 (-0.00%); split: -0.05%, +0.05% Spill count: 9248 -> 9244 (-0.04%) Fill count: 19677 -> 19596 (-0.41%) Max live registers: 415340 -> 415620 (+0.07%) Max dispatch width: 49720 -> 49704 (-0.03%); split: +0.10%, -0.13% Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095>
This commit is contained in:
Ian Romanick
Marge Bot
parent
cd343fb9ac
commit
3f151c03af
5 changed files with 73 additions and 144 deletions
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@ -849,135 +849,6 @@ try_emit_b2fi_of_inot(nir_to_brw_state &ntb, const fs_builder &bld,
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return true;
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}
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/**
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* Emit code for nir_op_fsign possibly fused with a nir_op_fmul
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*
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* If \c instr is not the \c nir_op_fsign, then \c fsign_src is the index of
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* the source of \c instr that is a \c nir_op_fsign.
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*/
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static void
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emit_fsign(nir_to_brw_state &ntb, const fs_builder &bld, const nir_alu_instr *instr,
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fs_reg result, fs_reg *op, unsigned fsign_src)
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{
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const intel_device_info *devinfo = ntb.devinfo;
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fs_inst *inst;
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assert(instr->op == nir_op_fsign || instr->op == nir_op_fmul);
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assert(fsign_src < nir_op_infos[instr->op].num_inputs);
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if (instr->op != nir_op_fsign) {
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const nir_alu_instr *const fsign_instr =
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nir_src_as_alu_instr(instr->src[fsign_src].src);
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/* op[fsign_src] has the nominal result of the fsign, and op[1 -
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* fsign_src] has the other multiply source. This must be rearranged so
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* that op[0] is the source of the fsign op[1] is the other multiply
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* source.
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*/
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if (fsign_src != 0)
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op[1] = op[0];
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op[0] = get_nir_src(ntb, fsign_instr->src[0].src);
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const nir_alu_type t =
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(nir_alu_type)(nir_op_infos[instr->op].input_types[0] |
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nir_src_bit_size(fsign_instr->src[0].src));
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op[0].type = brw_type_for_nir_type(devinfo, t);
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unsigned channel = 0;
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if (nir_op_infos[instr->op].output_size == 0) {
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/* Since NIR is doing the scalarizing for us, we should only ever see
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* vectorized operations with a single channel.
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*/
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nir_component_mask_t write_mask = get_nir_write_mask(instr->def);
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assert(util_bitcount(write_mask) == 1);
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channel = ffs(write_mask) - 1;
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}
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op[0] = offset(op[0], bld, fsign_instr->src[0].swizzle[channel]);
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}
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if (brw_type_size_bytes(op[0].type) == 2) {
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/* AND(val, 0x8000) gives the sign bit.
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*
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* Predicated OR ORs 1.0 (0x3c00) with the sign bit if val is not zero.
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*/
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fs_reg zero = retype(brw_imm_uw(0), BRW_TYPE_HF);
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bld.CMP(bld.null_reg_f(), op[0], zero, BRW_CONDITIONAL_NZ);
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op[0].type = BRW_TYPE_UW;
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result.type = BRW_TYPE_UW;
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bld.AND(result, op[0], brw_imm_uw(0x8000u));
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if (instr->op == nir_op_fsign)
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inst = bld.OR(result, result, brw_imm_uw(0x3c00u));
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else {
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/* Use XOR here to get the result sign correct. */
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inst = bld.XOR(result, result, retype(op[1], BRW_TYPE_UW));
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}
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inst->predicate = BRW_PREDICATE_NORMAL;
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} else if (brw_type_size_bytes(op[0].type) == 4) {
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/* AND(val, 0x80000000) gives the sign bit.
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*
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* Predicated OR ORs 1.0 (0x3f800000) with the sign bit if val is not
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* zero.
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*/
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bld.CMP(bld.null_reg_f(), op[0], brw_imm_f(0.0f), BRW_CONDITIONAL_NZ);
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op[0].type = BRW_TYPE_UD;
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result.type = BRW_TYPE_UD;
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bld.AND(result, op[0], brw_imm_ud(0x80000000u));
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if (instr->op == nir_op_fsign)
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inst = bld.OR(result, result, brw_imm_ud(0x3f800000u));
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else {
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/* Use XOR here to get the result sign correct. */
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inst = bld.XOR(result, result, retype(op[1], BRW_TYPE_UD));
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}
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inst->predicate = BRW_PREDICATE_NORMAL;
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} else {
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unreachable("Should have been lowered by nir_opt_algebraic.");
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}
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}
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/**
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* Determine whether sources of a nir_op_fmul can be fused with a nir_op_fsign
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*
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* Checks the operands of a \c nir_op_fmul to determine whether or not
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* \c emit_fsign could fuse the multiplication with the \c sign() calculation.
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*
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* \param instr The multiplication instruction
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*
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* \param fsign_src The source of \c instr that may or may not be a
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* \c nir_op_fsign
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*/
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static bool
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can_fuse_fmul_fsign(nir_alu_instr *instr, unsigned fsign_src)
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{
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assert(instr->op == nir_op_fmul);
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nir_alu_instr *const fsign_instr =
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nir_src_as_alu_instr(instr->src[fsign_src].src);
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/* Rules:
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*
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* 1. instr->src[fsign_src] must be a nir_op_fsign.
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* 2. The nir_op_fsign can only be used by this multiplication.
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* 3. The source that is the nir_op_fsign does not have source modifiers.
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* \c emit_fsign only examines the source modifiers of the source of the
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* \c nir_op_fsign.
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*
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* The nir_op_fsign must also not have the saturate modifier, but steps
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* have already been taken (in nir_opt_algebraic) to ensure that.
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*/
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return fsign_instr != NULL && fsign_instr->op == nir_op_fsign &&
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is_used_once(fsign_instr);
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}
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static bool
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is_const_zero(const nir_src &src)
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{
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@ -1233,8 +1104,7 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr,
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break;
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case nir_op_fsign:
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emit_fsign(ntb, bld, instr, result, op, 0);
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break;
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unreachable("Should have been lowered by brw_nir_lower_fsign.");
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case nir_op_frcp:
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bld.RCP(result, op[0]);
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@ -1322,17 +1192,6 @@ fs_nir_emit_alu(nir_to_brw_state &ntb, nir_alu_instr *instr,
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}
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case nir_op_fmul:
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for (unsigned i = 0; i < 2; i++) {
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if (can_fuse_fmul_fsign(instr, i)) {
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emit_fsign(ntb, bld, instr, result, op, i);
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return;
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}
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}
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/* We emit the rounding mode after the previous fsign optimization since
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* it won't result in a MUL, but will try to negate the value by other
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* means.
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*/
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if (nir_has_any_rounding_mode_enabled(execution_mode)) {
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brw_rnd_mode rnd =
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brw_rnd_mode_from_execution_mode(execution_mode);
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@ -1711,7 +1711,11 @@ brw_postprocess_nir(nir_shader *nir, const struct brw_compiler *compiler,
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do {
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progress = false;
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if (OPT(nir_opt_algebraic_late)) {
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OPT(nir_opt_algebraic_late);
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OPT(brw_nir_lower_fsign);
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if (progress) {
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OPT(nir_opt_constant_folding);
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OPT(nir_copy_prop);
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OPT(nir_opt_dce);
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@ -195,6 +195,8 @@ bool brw_nir_apply_trig_workarounds(nir_shader *nir);
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bool brw_nir_limit_trig_input_range_workaround(nir_shader *nir);
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bool brw_nir_lower_fsign(nir_shader *nir);
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void brw_nir_apply_key(nir_shader *nir,
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const struct brw_compiler *compiler,
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const struct brw_base_prog_key *key,
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53
src/intel/compiler/brw_nir_lower_fsign.py
Normal file
53
src/intel/compiler/brw_nir_lower_fsign.py
Normal file
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@ -0,0 +1,53 @@
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# Copyright © 2024 Intel Corporation
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# SPDX-License-Identifier: MIT
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import argparse
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import sys
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from math import pi
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a = 'a'
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b = 'b'
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lower_fsign = [
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# This matches the behavior of the old optimization in brw_fs_nir.cpp, but
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# it has some problems.
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#
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# The fmul version passes Vulkan float_controls2 CTS a little bit by
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# luck. The use of fne means that the false path (i.e., fsign(X) == 0) is
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# only taken when X is zero. For OpenCL, this path should also be taken
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# when when X is NaN. This can be handled by using 'fabs(X) > 0', but this
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# fails float_controls2 CTS when the other multiplication operand is NaN.
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#
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# This optimization is additionally problematic when fsign(X) is zero and
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# the other multiplication operand is Inf. This will result in 0, but it
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# should result in NaN. This does not seem to be tested by the CTS.
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#
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# NOTE: fcsel opcodes are currently limited to float32 in NIR.
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(('fmul@32', ('fsign(is_used_once)', a), b), ('fcsel', a , ('ixor', ('iand', a, 0x80000000), b), ('iand', a, 0x80000000))),
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(('fmul@16', ('fsign(is_used_once)', a), b), ('bcsel', ('fneu', a, 0), ('ixor', ('iand', a, 0x8000 ), b), ('iand', a, 0x8000 ))),
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# This is 99.99% strictly correct for OpenCL. It will provide correctly
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# signed zero for ±0 inputs, and it will provide zero for NaN inputs. The
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# only slight deviation is that it can provide -0 for some NaN inputs.
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(('fsign@32', a), ('fcsel_gt', ('fabs', a) , ('ior', ('iand', a, 0x80000000), 0x3f800000), ('iand', a, 0x80000000))),
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(('fsign@16', a), ('bcsel', ('!flt', 0, ('fabs', a)), ('ior', ('iand', a, 0x8000 ), 0x3c00 ), ('iand', a, 0x8000 ))),
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]
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def main():
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parser = argparse.ArgumentParser()
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parser.add_argument('-p', '--import-path', required=True)
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args = parser.parse_args()
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sys.path.insert(0, args.import_path)
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run()
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def run():
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import nir_algebraic # pylint: disable=import-error
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print('#include "brw_nir.h"')
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print(nir_algebraic.AlgebraicPass("brw_nir_lower_fsign", lower_fsign).render())
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if __name__ == '__main__':
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main()
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@ -130,6 +130,17 @@ brw_device_sha1_gen_src = custom_target('brw_device_sha1_gen.c',
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command : [prog_python, '@INPUT0@', '--outdir', meson.current_build_dir()])
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brw_nir_lower_fsign = custom_target(
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'brw_nir_lower_fsign.c',
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input : 'brw_nir_lower_fsign.py',
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output : 'brw_nir_lower_fsign.c',
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command : [
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prog_python, '@INPUT@', '-p', dir_compiler_nir,
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],
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depend_files : nir_algebraic_depends,
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capture : true,
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)
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brw_nir_trig = custom_target(
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'brw_nir_trig_workarounds.c',
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input : 'brw_nir_trig_workarounds.py',
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@ -143,7 +154,7 @@ brw_nir_trig = custom_target(
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libintel_compiler_brw = static_library(
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'intel_compiler',
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[libintel_compiler_brw_files, intel_nir_files, brw_nir_trig, ir_expression_operation_h, [brw_device_sha1_gen_src]],
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[libintel_compiler_brw_files, intel_nir_files, brw_nir_lower_fsign, brw_nir_trig, ir_expression_operation_h, [brw_device_sha1_gen_src]],
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include_directories : [inc_include, inc_src, inc_intel],
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c_args : [no_override_init_args],
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gnu_symbol_visibility : 'hidden',
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