2017-09-14 17:57:17 -07:00
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# Copyright © 2017 Intel Corporation
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2024-06-28 13:16:28 -07:00
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# SPDX-License-Identifier: MIT
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2017-09-14 17:57:17 -07:00
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2023-11-01 12:51:33 -07:00
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intel_nir_files = files(
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'intel_nir.h',
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'intel_nir.c',
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2023-11-01 15:15:43 -07:00
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'intel_nir_blockify_uniform_loads.c',
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'intel_nir_clamp_image_1d_2d_array_sizes.c',
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'intel_nir_clamp_per_vertex_loads.c',
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'intel_nir_lower_conversions.c',
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'intel_nir_lower_non_uniform_barycentric_at_sample.c',
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'intel_nir_lower_non_uniform_resource_intel.c',
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2023-09-05 16:11:56 +03:00
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'intel_nir_lower_printf.c',
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2023-11-01 15:15:43 -07:00
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'intel_nir_lower_shading_rate_output.c',
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'intel_nir_lower_sparse.c',
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'intel_nir_lower_texture.c',
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'intel_nir_opt_peephole_ffma.c',
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'intel_nir_opt_peephole_imul32x16.c',
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'intel_nir_tcs_workarounds.c',
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2023-11-01 12:51:33 -07:00
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)
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2024-02-09 15:37:14 -08:00
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libintel_compiler_brw_files = files(
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2017-09-14 17:57:17 -07:00
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'brw_cfg.cpp',
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'brw_cfg.h',
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2024-07-12 13:52:46 -07:00
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'brw_compile_bs.cpp',
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'brw_compile_cs.cpp',
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'brw_compile_fs.cpp',
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2024-02-14 18:17:59 -08:00
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'brw_compile_gs.cpp',
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2024-07-12 13:52:46 -07:00
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'brw_compile_mesh.cpp',
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2024-02-14 18:17:59 -08:00
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'brw_compile_tcs.cpp',
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2024-07-12 13:52:46 -07:00
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'brw_compile_tes.cpp',
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2024-02-14 18:17:59 -08:00
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'brw_compile_vs.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_compiler.c',
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'brw_compiler.h',
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2019-04-15 21:59:50 -07:00
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'brw_debug_recompile.c',
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2023-11-16 01:16:45 -08:00
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'brw_def_analysis.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_disasm.c',
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2024-02-29 17:53:53 -08:00
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'brw_disasm_info.cpp',
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2017-11-16 11:43:51 -08:00
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'brw_disasm_info.h',
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2022-06-30 01:47:09 -07:00
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'brw_eu.c',
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2017-09-14 17:57:17 -07:00
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'brw_eu_compact.c',
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'brw_eu_defines.h',
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'brw_eu_emit.c',
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'brw_eu.h',
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'brw_eu_validate.c',
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2017-06-15 15:23:57 -07:00
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'brw_fs_bank_conflicts.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_fs_builder.h',
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'brw_fs_cmod_propagation.cpp',
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'brw_fs_combine_constants.cpp',
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'brw_fs_copy_propagation.cpp',
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'brw_fs.cpp',
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'brw_fs_cse.cpp',
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'brw_fs_dead_code_eliminate.cpp',
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'brw_fs_generator.cpp',
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'brw_fs.h',
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'brw_fs_live_variables.cpp',
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'brw_fs_live_variables.h',
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2024-01-04 23:27:04 -08:00
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'brw_fs_lower.cpp',
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2023-10-10 15:35:46 -07:00
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'brw_fs_lower_dpas.cpp',
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2024-01-04 22:07:17 -08:00
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'brw_fs_lower_integer_multiplication.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_fs_lower_pack.cpp',
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2018-12-29 04:00:13 -08:00
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'brw_fs_lower_regioning.cpp',
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2024-01-04 22:33:59 -08:00
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'brw_fs_lower_simd_width.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_fs_nir.cpp',
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2024-01-04 17:31:42 -08:00
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'brw_fs_opt.cpp',
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2024-01-04 23:26:50 -08:00
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'brw_fs_opt_algebraic.cpp',
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2024-01-04 17:54:25 -08:00
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'brw_fs_opt_virtual_grfs.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_fs_reg_allocate.cpp',
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'brw_fs_register_coalesce.cpp',
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'brw_fs_saturate_propagation.cpp',
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2018-11-09 14:13:37 -08:00
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'brw_fs_scoreboard.cpp',
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2022-08-19 12:40:20 -07:00
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'brw_fs_thread_payload.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_fs_validate.cpp',
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'brw_fs_visitor.cpp',
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2024-01-04 22:39:57 -08:00
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'brw_fs_workaround.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_inst.h',
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2016-03-06 18:13:59 -08:00
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'brw_ir.h',
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2017-09-14 17:57:17 -07:00
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'brw_ir_allocator.h',
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2016-03-06 18:11:20 -08:00
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'brw_ir_analysis.h',
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2017-09-14 17:57:17 -07:00
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'brw_ir_fs.h',
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2020-03-26 14:59:02 -07:00
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'brw_ir_performance.h',
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'brw_ir_performance.cpp',
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2022-06-29 14:25:19 -07:00
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'brw_isa_info.h',
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2022-06-27 12:24:58 -07:00
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'brw_lower_logical_sends.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_nir.h',
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'brw_nir.c',
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'brw_nir_analyze_ubo_ranges.c',
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2023-06-13 19:45:49 -07:00
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'brw_nir_lower_cooperative_matrix.c',
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2017-10-06 10:08:11 -07:00
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'brw_nir_lower_cs_intrinsics.c',
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2019-09-27 16:23:46 -07:00
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'brw_nir_lower_alpha_to_coverage.c',
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2020-08-06 16:22:15 -05:00
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'brw_nir_lower_intersection_shader.c',
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2021-06-21 13:44:53 +03:00
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'brw_nir_lower_ray_queries.c',
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2020-08-06 12:59:49 -05:00
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'brw_nir_lower_rt_intrinsics.c',
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2020-08-06 13:53:34 -05:00
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'brw_nir_lower_shader_calls.c',
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2021-02-03 11:34:46 -08:00
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'brw_nir_lower_storage_image.c',
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intel/brw: Move fsat instructions closer to the source
Intel GPUs have a saturate destination modifier, and
brw_fs_opt_saturate_propagation tries to replace explicit saturate
operations with this destination modifier. That pass is limited in
several ways. If the source of the explicit saturate is in a different
block or if the source of the explicit saturate is live after the
explicit saturate, brw_fs_opt_saturate_propagation will be unable to
make progress.
This optimization exists to help brw_fs_opt_saturate_propagation make
more progress. It tries to move NIR fsat instructions to the same block
that contains the definition of its source. It does this only in cases
where it will not create additional live values. It also attempts to do
this only in cases where the explicit saturate will ultimiately be
converted to a destination modifier.
v2: Fix metadata_preserve when theres no progress and use
nir_metadata_control_flow when there is progress. All suggested by
Alyssa.
v3: Fix a typo in the file header comment. Noticed by Ken. Don't
require nir_metadata_instr_index. Use nir_def_rewrite_uses_after instead
of open-coding something slightly more specific. Both suggested by Ken.
shader-db:
All Intel platforms had similar results. (Meteor Lake shown)
total instructions in shared programs: 19733645 -> 19733028 (<.01%)
instructions in affected programs: 193300 -> 192683 (-0.32%)
helped: 246
HURT: 1
helped stats (abs) min: 2 max: 48 x̄: 2.51 x̃: 2
helped stats (rel) min: 0.18% max: 0.39% x̄: 0.33% x̃: 0.34%
HURT stats (abs) min: 1 max: 1 x̄: 1.00 x̃: 1
HURT stats (rel) min: 0.31% max: 0.31% x̄: 0.31% x̃: 0.31%
95% mean confidence interval for instructions value: -2.87 -2.13
95% mean confidence interval for instructions %-change: -0.34% -0.32%
Instructions are helped.
total cycles in shared programs: 916180971 -> 916264656 (<.01%)
cycles in affected programs: 30197180 -> 30280865 (0.28%)
helped: 194
HURT: 142
helped stats (abs) min: 1 max: 21251 x̄: 872.75 x̃: 19
helped stats (rel) min: <.01% max: 23.17% x̄: 2.59% x̃: 0.23%
HURT stats (abs) min: 1 max: 28058 x̄: 1781.68 x̃: 399
HURT stats (rel) min: <.01% max: 37.21% x̄: 4.85% x̃: 1.63%
95% mean confidence interval for cycles value: -196.84 694.97
95% mean confidence interval for cycles %-change: -0.17% 1.27%
Inconclusive result (value mean confidence interval includes 0).
fossil-db:
Meteor Lake, DG2, and Tiger Lake had similar results. (Meteor Lake shown)
Totals:
Instrs: 151512021 -> 151511351 (-0.00%); split: -0.00%, +0.00%
Cycle count: 17209013596 -> 17209840995 (+0.00%); split: -0.02%, +0.02%
Max live registers: 32013312 -> 32013549 (+0.00%)
Max dispatch width: 5512304 -> 5512136 (-0.00%)
Totals from 774 (0.12% of 630172) affected shaders:
Instrs: 1559285 -> 1558615 (-0.04%); split: -0.05%, +0.01%
Cycle count: 1312656268 -> 1313483667 (+0.06%); split: -0.24%, +0.30%
Max live registers: 82195 -> 82432 (+0.29%)
Max dispatch width: 6664 -> 6496 (-2.52%)
Ice Lake
Totals:
Instrs: 151416791 -> 151416137 (-0.00%); split: -0.00%, +0.00%
Cycle count: 15162468885 -> 15163298824 (+0.01%); split: -0.00%, +0.01%
Max live registers: 32471367 -> 32471603 (+0.00%)
Max dispatch width: 5623752 -> 5623712 (-0.00%)
Totals from 733 (0.12% of 635598) affected shaders:
Instrs: 877965 -> 877311 (-0.07%); split: -0.09%, +0.01%
Cycle count: 190763628 -> 191593567 (+0.44%); split: -0.21%, +0.64%
Max live registers: 72067 -> 72303 (+0.33%)
Max dispatch width: 6216 -> 6176 (-0.64%)
Skylake
Totals:
Instrs: 140794845 -> 140794075 (-0.00%); split: -0.00%, +0.00%
Cycle count: 14665159301 -> 14665320514 (+0.00%); split: -0.00%, +0.01%
Max live registers: 31783341 -> 31783662 (+0.00%); split: -0.00%, +0.00%
Totals from 659 (0.11% of 625670) affected shaders:
Instrs: 829061 -> 828291 (-0.09%); split: -0.09%, +0.00%
Cycle count: 185478478 -> 185639691 (+0.09%); split: -0.33%, +0.41%
Max live registers: 67491 -> 67812 (+0.48%); split: -0.01%, +0.48%
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29774>
2024-06-07 13:08:06 -07:00
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'brw_nir_opt_fsat.c',
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2020-08-06 12:59:49 -05:00
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'brw_nir_rt.h',
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2020-08-06 13:20:07 -05:00
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'brw_nir_rt.c',
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2020-08-06 12:44:57 -05:00
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'brw_nir_rt_builder.h',
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2017-09-14 17:57:17 -07:00
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'brw_packed_float.c',
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2024-07-12 16:20:55 -07:00
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'brw_print.cpp',
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2022-06-29 15:19:57 -07:00
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'brw_prim.h',
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2021-10-06 22:37:42 -07:00
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'brw_private.h',
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2017-09-14 17:57:17 -07:00
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'brw_reg.h',
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'brw_reg_type.c',
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'brw_reg_type.h',
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2020-08-06 12:53:47 -05:00
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'brw_rt.h',
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2017-09-14 17:57:17 -07:00
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'brw_schedule_instructions.cpp',
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'brw_shader.cpp',
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2022-11-07 17:35:16 -08:00
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'brw_simd_selection.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_vue_map.c',
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)
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2024-02-09 15:30:57 -08:00
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brw_device_sha1_gen_src = custom_target('brw_device_sha1_gen.c',
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input : ['brw_device_sha1_gen_c.py', '../dev/intel_device_info.py'],
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output : ['brw_device_sha1_gen.c'],
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command : [prog_python, '@INPUT0@', '--outdir', meson.current_build_dir()])
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intel/brw: Handle fsign optimization in a NIR algebraic pass
This is a lot less code, and it makes it easier to experiment with other
pattern-based optimizations in the future.
The results here are nearly identical to the results I got from Ken's
"intel/brw: Make fsign (for 16/32-bit) in SSA form"... which are not
particularly good.
In this commit and in Ken's, all of the shader-db shaders hurt for
spills and fills are from Deus Ex Mankind Divided. Each shader has a
bunch of texture instructions with a single fsign between the
blocks. With the dependency on the flag removed, the scheduler puts all
of the texture instructions at the start... and there are a LOT of them.
shader-db:
All Intel platforms had similar results. (Meteor Lake shown)
total instructions in shared programs: 19647060 -> 19650207 (0.02%)
instructions in affected programs: 734718 -> 737865 (0.43%)
helped: 382 / HURT: 1984
total cycles in shared programs: 823238442 -> 822785913 (-0.05%)
cycles in affected programs: 426901157 -> 426448628 (-0.11%)
helped: 3408 / HURT: 3671
total spills in shared programs: 3887 -> 3891 (0.10%)
spills in affected programs: 256 -> 260 (1.56%)
helped: 0 / HURT: 4
total fills in shared programs: 3236 -> 3306 (2.16%)
fills in affected programs: 882 -> 952 (7.94%)
helped: 0 / HURT: 12
LOST: 37
GAINED: 34
fossil-db:
DG2 and Meteor Lake had similar results. (Meteor Lake shown)
Totals:
Instrs: 154005469 -> 154008294 (+0.00%); split: -0.00%, +0.00%
Cycle count: 17551859277 -> 17554293955 (+0.01%); split: -0.02%, +0.04%
Spill count: 142078 -> 142090 (+0.01%)
Fill count: 266761 -> 266729 (-0.01%); split: -0.02%, +0.01%
Max live registers: 32593578 -> 32593858 (+0.00%)
Max dispatch width: 5535944 -> 5536816 (+0.02%); split: +0.02%, -0.01%
Totals from 5867 (0.93% of 631350) affected shaders:
Instrs: 5475544 -> 5478369 (+0.05%); split: -0.04%, +0.09%
Cycle count: 1649032029 -> 1651466707 (+0.15%); split: -0.24%, +0.39%
Spill count: 26411 -> 26423 (+0.05%)
Fill count: 57364 -> 57332 (-0.06%); split: -0.10%, +0.04%
Max live registers: 431561 -> 431841 (+0.06%)
Max dispatch width: 49784 -> 50656 (+1.75%); split: +2.38%, -0.63%
Tiger Lake
Totals:
Instrs: 149530671 -> 149533588 (+0.00%); split: -0.00%, +0.00%
Cycle count: 15261418953 -> 15264764921 (+0.02%); split: -0.00%, +0.03%
Spill count: 60317 -> 60316 (-0.00%); split: -0.02%, +0.01%
Max live registers: 32249201 -> 32249464 (+0.00%)
Max dispatch width: 5540608 -> 5540584 (-0.00%)
Totals from 5862 (0.93% of 630309) affected shaders:
Instrs: 4740800 -> 4743717 (+0.06%); split: -0.04%, +0.10%
Cycle count: 566531248 -> 569877216 (+0.59%); split: -0.13%, +0.72%
Spill count: 11709 -> 11708 (-0.01%); split: -0.09%, +0.08%
Max live registers: 424560 -> 424823 (+0.06%)
Max dispatch width: 50304 -> 50280 (-0.05%)
Ice Lake
Totals:
Instrs: 150499705 -> 150502608 (+0.00%); split: -0.00%, +0.00%
Cycle count: 15105629116 -> 15105425880 (-0.00%); split: -0.00%, +0.00%
Spill count: 60087 -> 60090 (+0.00%)
Fill count: 100542 -> 100541 (-0.00%); split: -0.00%, +0.00%
Max live registers: 32605215 -> 32605495 (+0.00%)
Max dispatch width: 5617752 -> 5617792 (+0.00%); split: +0.00%, -0.00%
Totals from 5882 (0.93% of 634934) affected shaders:
Instrs: 4737206 -> 4740109 (+0.06%); split: -0.04%, +0.10%
Cycle count: 598882104 -> 598678868 (-0.03%); split: -0.08%, +0.05%
Spill count: 10278 -> 10281 (+0.03%)
Fill count: 22504 -> 22503 (-0.00%); split: -0.01%, +0.01%
Max live registers: 424184 -> 424464 (+0.07%)
Max dispatch width: 50216 -> 50256 (+0.08%); split: +0.25%, -0.18%
Skylake
Totals:
Instrs: 139092612 -> 139095257 (+0.00%); split: -0.00%, +0.00%
Cycle count: 14533550285 -> 14533544716 (-0.00%); split: -0.00%, +0.00%
Spill count: 58176 -> 58172 (-0.01%)
Fill count: 95877 -> 95796 (-0.08%)
Max live registers: 31924594 -> 31924874 (+0.00%)
Max dispatch width: 5484568 -> 5484552 (-0.00%); split: +0.00%, -0.00%
Totals from 5789 (0.93% of 625512) affected shaders:
Instrs: 4481987 -> 4484632 (+0.06%); split: -0.04%, +0.10%
Cycle count: 578310124 -> 578304555 (-0.00%); split: -0.05%, +0.05%
Spill count: 9248 -> 9244 (-0.04%)
Fill count: 19677 -> 19596 (-0.41%)
Max live registers: 415340 -> 415620 (+0.07%)
Max dispatch width: 49720 -> 49704 (-0.03%); split: +0.10%, -0.13%
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095>
2024-05-01 21:02:13 -07:00
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brw_nir_lower_fsign = custom_target(
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'brw_nir_lower_fsign.c',
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input : 'brw_nir_lower_fsign.py',
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output : 'brw_nir_lower_fsign.c',
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command : [
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prog_python, '@INPUT@', '-p', dir_compiler_nir,
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],
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depend_files : nir_algebraic_depends,
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capture : true,
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)
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2017-09-14 17:57:17 -07:00
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brw_nir_trig = custom_target(
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'brw_nir_trig_workarounds.c',
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input : 'brw_nir_trig_workarounds.py',
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output : 'brw_nir_trig_workarounds.c',
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2017-12-11 15:56:08 -08:00
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command : [
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2022-08-10 02:04:51 +03:00
|
|
|
prog_python, '@INPUT@', '-p', dir_compiler_nir,
|
2017-12-11 15:56:08 -08:00
|
|
|
],
|
2022-02-16 14:02:16 -08:00
|
|
|
depend_files : nir_algebraic_depends,
|
2017-09-14 17:57:17 -07:00
|
|
|
capture : true,
|
|
|
|
|
)
|
|
|
|
|
|
2024-02-09 15:37:14 -08:00
|
|
|
libintel_compiler_brw = static_library(
|
2017-09-14 17:57:17 -07:00
|
|
|
'intel_compiler',
|
intel/brw: Handle fsign optimization in a NIR algebraic pass
This is a lot less code, and it makes it easier to experiment with other
pattern-based optimizations in the future.
The results here are nearly identical to the results I got from Ken's
"intel/brw: Make fsign (for 16/32-bit) in SSA form"... which are not
particularly good.
In this commit and in Ken's, all of the shader-db shaders hurt for
spills and fills are from Deus Ex Mankind Divided. Each shader has a
bunch of texture instructions with a single fsign between the
blocks. With the dependency on the flag removed, the scheduler puts all
of the texture instructions at the start... and there are a LOT of them.
shader-db:
All Intel platforms had similar results. (Meteor Lake shown)
total instructions in shared programs: 19647060 -> 19650207 (0.02%)
instructions in affected programs: 734718 -> 737865 (0.43%)
helped: 382 / HURT: 1984
total cycles in shared programs: 823238442 -> 822785913 (-0.05%)
cycles in affected programs: 426901157 -> 426448628 (-0.11%)
helped: 3408 / HURT: 3671
total spills in shared programs: 3887 -> 3891 (0.10%)
spills in affected programs: 256 -> 260 (1.56%)
helped: 0 / HURT: 4
total fills in shared programs: 3236 -> 3306 (2.16%)
fills in affected programs: 882 -> 952 (7.94%)
helped: 0 / HURT: 12
LOST: 37
GAINED: 34
fossil-db:
DG2 and Meteor Lake had similar results. (Meteor Lake shown)
Totals:
Instrs: 154005469 -> 154008294 (+0.00%); split: -0.00%, +0.00%
Cycle count: 17551859277 -> 17554293955 (+0.01%); split: -0.02%, +0.04%
Spill count: 142078 -> 142090 (+0.01%)
Fill count: 266761 -> 266729 (-0.01%); split: -0.02%, +0.01%
Max live registers: 32593578 -> 32593858 (+0.00%)
Max dispatch width: 5535944 -> 5536816 (+0.02%); split: +0.02%, -0.01%
Totals from 5867 (0.93% of 631350) affected shaders:
Instrs: 5475544 -> 5478369 (+0.05%); split: -0.04%, +0.09%
Cycle count: 1649032029 -> 1651466707 (+0.15%); split: -0.24%, +0.39%
Spill count: 26411 -> 26423 (+0.05%)
Fill count: 57364 -> 57332 (-0.06%); split: -0.10%, +0.04%
Max live registers: 431561 -> 431841 (+0.06%)
Max dispatch width: 49784 -> 50656 (+1.75%); split: +2.38%, -0.63%
Tiger Lake
Totals:
Instrs: 149530671 -> 149533588 (+0.00%); split: -0.00%, +0.00%
Cycle count: 15261418953 -> 15264764921 (+0.02%); split: -0.00%, +0.03%
Spill count: 60317 -> 60316 (-0.00%); split: -0.02%, +0.01%
Max live registers: 32249201 -> 32249464 (+0.00%)
Max dispatch width: 5540608 -> 5540584 (-0.00%)
Totals from 5862 (0.93% of 630309) affected shaders:
Instrs: 4740800 -> 4743717 (+0.06%); split: -0.04%, +0.10%
Cycle count: 566531248 -> 569877216 (+0.59%); split: -0.13%, +0.72%
Spill count: 11709 -> 11708 (-0.01%); split: -0.09%, +0.08%
Max live registers: 424560 -> 424823 (+0.06%)
Max dispatch width: 50304 -> 50280 (-0.05%)
Ice Lake
Totals:
Instrs: 150499705 -> 150502608 (+0.00%); split: -0.00%, +0.00%
Cycle count: 15105629116 -> 15105425880 (-0.00%); split: -0.00%, +0.00%
Spill count: 60087 -> 60090 (+0.00%)
Fill count: 100542 -> 100541 (-0.00%); split: -0.00%, +0.00%
Max live registers: 32605215 -> 32605495 (+0.00%)
Max dispatch width: 5617752 -> 5617792 (+0.00%); split: +0.00%, -0.00%
Totals from 5882 (0.93% of 634934) affected shaders:
Instrs: 4737206 -> 4740109 (+0.06%); split: -0.04%, +0.10%
Cycle count: 598882104 -> 598678868 (-0.03%); split: -0.08%, +0.05%
Spill count: 10278 -> 10281 (+0.03%)
Fill count: 22504 -> 22503 (-0.00%); split: -0.01%, +0.01%
Max live registers: 424184 -> 424464 (+0.07%)
Max dispatch width: 50216 -> 50256 (+0.08%); split: +0.25%, -0.18%
Skylake
Totals:
Instrs: 139092612 -> 139095257 (+0.00%); split: -0.00%, +0.00%
Cycle count: 14533550285 -> 14533544716 (-0.00%); split: -0.00%, +0.00%
Spill count: 58176 -> 58172 (-0.01%)
Fill count: 95877 -> 95796 (-0.08%)
Max live registers: 31924594 -> 31924874 (+0.00%)
Max dispatch width: 5484568 -> 5484552 (-0.00%); split: +0.00%, -0.00%
Totals from 5789 (0.93% of 625512) affected shaders:
Instrs: 4481987 -> 4484632 (+0.06%); split: -0.04%, +0.10%
Cycle count: 578310124 -> 578304555 (-0.00%); split: -0.05%, +0.05%
Spill count: 9248 -> 9244 (-0.04%)
Fill count: 19677 -> 19596 (-0.41%)
Max live registers: 415340 -> 415620 (+0.07%)
Max dispatch width: 49720 -> 49704 (-0.03%); split: +0.10%, -0.13%
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095>
2024-05-01 21:02:13 -07:00
|
|
|
[libintel_compiler_brw_files, intel_nir_files, brw_nir_lower_fsign, brw_nir_trig, ir_expression_operation_h, [brw_device_sha1_gen_src]],
|
2023-08-02 19:24:14 +08:00
|
|
|
include_directories : [inc_include, inc_src, inc_intel],
|
2020-04-24 13:10:41 -07:00
|
|
|
c_args : [no_override_init_args],
|
|
|
|
|
gnu_symbol_visibility : 'hidden',
|
2023-02-15 10:09:57 -08:00
|
|
|
dependencies : [idep_nir_headers, idep_mesautil, idep_intel_dev],
|
2017-09-14 17:57:17 -07:00
|
|
|
build_by_default : false,
|
|
|
|
|
)
|
|
|
|
|
|
2024-02-28 17:38:04 -08:00
|
|
|
idep_intel_compiler_brw = declare_dependency(
|
|
|
|
|
link_with : [libintel_compiler_brw],
|
2024-02-28 17:41:46 -08:00
|
|
|
dependencies : [
|
|
|
|
|
idep_nir,
|
2024-06-06 16:09:00 +01:00
|
|
|
idep_mesautil,
|
2024-02-28 17:41:46 -08:00
|
|
|
],
|
2024-02-28 17:38:04 -08:00
|
|
|
)
|
|
|
|
|
|
2021-02-19 10:34:49 -06:00
|
|
|
# For now this tool is only going to be used by Anv
|
2023-08-31 13:16:29 -04:00
|
|
|
if get_option('intel-clc') == 'system'
|
|
|
|
|
prog_intel_clc = find_program('intel_clc', native : true)
|
|
|
|
|
dep_prog_intel_clc = []
|
|
|
|
|
elif with_intel_clc
|
2021-02-19 10:34:49 -06:00
|
|
|
prog_intel_clc = executable(
|
|
|
|
|
'intel_clc',
|
2024-02-14 15:59:45 -08:00
|
|
|
[
|
|
|
|
|
'intel_clc.c',
|
|
|
|
|
'brw_kernel.c',
|
|
|
|
|
|
|
|
|
|
# Use just the nir_options part of ELK instead of fully linking.
|
|
|
|
|
'elk/elk_nir_options.h',
|
|
|
|
|
'elk/elk_nir_options.c',
|
|
|
|
|
],
|
2024-05-10 22:40:52 +03:00
|
|
|
link_with : [libisl],
|
2023-08-02 19:24:14 +08:00
|
|
|
include_directories : [inc_include, inc_src, inc_intel],
|
2021-02-19 10:34:49 -06:00
|
|
|
c_args : [pre_args, no_override_init_args],
|
2022-10-01 00:36:59 -07:00
|
|
|
link_args : [ld_args_build_id],
|
2024-02-28 17:38:04 -08:00
|
|
|
dependencies : [idep_nir, idep_vtn, idep_mesaclc, idep_mesautil, idep_intel_dev,
|
|
|
|
|
idep_intel_compiler_brw],
|
2024-03-07 13:18:46 +02:00
|
|
|
# If we can run host binaries directly, just build intel_clc for the host.
|
|
|
|
|
# Most commonly this happens when doing a cross compile from an x86_64 build
|
|
|
|
|
# machine to an x86 host
|
|
|
|
|
native : not meson.can_run_host_binaries(),
|
2024-02-12 15:06:06 +02:00
|
|
|
install : get_option('install-intel-clc'),
|
2021-02-19 10:34:49 -06:00
|
|
|
)
|
2023-08-31 13:16:29 -04:00
|
|
|
dep_prog_intel_clc = [prog_intel_clc]
|
2021-02-19 10:34:49 -06:00
|
|
|
endif
|
|
|
|
|
|
2017-09-14 17:57:17 -07:00
|
|
|
if with_tests
|
2021-10-11 23:27:53 -07:00
|
|
|
test(
|
2024-02-09 15:37:14 -08:00
|
|
|
'intel_compiler_brw_tests',
|
2021-10-11 23:27:53 -07:00
|
|
|
executable(
|
2024-02-09 15:37:14 -08:00
|
|
|
'intel_compiler_brw_tests',
|
2021-10-11 23:27:53 -07:00
|
|
|
files(
|
|
|
|
|
'test_eu_compact.cpp',
|
|
|
|
|
'test_eu_validate.cpp',
|
|
|
|
|
'test_fs_cmod_propagation.cpp',
|
2024-01-17 18:32:11 -08:00
|
|
|
'test_fs_combine_constants.cpp',
|
2021-10-11 23:27:53 -07:00
|
|
|
'test_fs_copy_propagation.cpp',
|
2024-06-25 14:07:32 -07:00
|
|
|
'test_fs_cse.cpp',
|
2021-10-11 23:27:53 -07:00
|
|
|
'test_fs_saturate_propagation.cpp',
|
|
|
|
|
'test_fs_scoreboard.cpp',
|
2021-10-06 22:37:42 -07:00
|
|
|
'test_simd_selection.cpp',
|
2021-10-11 23:27:53 -07:00
|
|
|
'test_vf_float_conversions.cpp',
|
2018-11-19 13:44:15 -08:00
|
|
|
),
|
2021-10-11 23:27:53 -07:00
|
|
|
ir_expression_operation_h,
|
2023-08-02 19:24:14 +08:00
|
|
|
include_directories : [inc_include, inc_src, inc_intel],
|
2024-05-10 22:40:52 +03:00
|
|
|
link_with : libisl,
|
2024-02-28 17:38:04 -08:00
|
|
|
dependencies : [idep_gtest, idep_nir, idep_mesautil, idep_intel_dev,
|
|
|
|
|
idep_intel_compiler_brw],
|
2021-10-11 23:27:53 -07:00
|
|
|
),
|
|
|
|
|
suite : ['intel'],
|
2023-02-23 10:49:37 +00:00
|
|
|
protocol : 'gtest',
|
2021-10-11 23:27:53 -07:00
|
|
|
)
|
2017-09-14 17:57:17 -07:00
|
|
|
endif
|
2024-02-09 13:55:14 -08:00
|
|
|
|
|
|
|
|
if with_intel_tools
|
|
|
|
|
|
|
|
|
|
bison_command = []
|
|
|
|
|
if yacc_is_bison
|
|
|
|
|
bison_command = [
|
|
|
|
|
prog_bison, '@INPUT@', '--defines=@OUTPUT1@',
|
|
|
|
|
'--output=@OUTPUT0@'
|
|
|
|
|
]
|
|
|
|
|
else
|
|
|
|
|
bison_command = [
|
|
|
|
|
prog_bison, '-H', '@OUTPUT1@',
|
|
|
|
|
'-o', '@OUTPUT0@', '@INPUT@'
|
|
|
|
|
]
|
|
|
|
|
endif
|
|
|
|
|
|
|
|
|
|
brw_gram_tab = custom_target(
|
|
|
|
|
'brw_gram.tab.[ch]',
|
|
|
|
|
input : 'brw_gram.y',
|
|
|
|
|
output : ['brw_gram.tab.c', 'brw_gram.tab.h'],
|
|
|
|
|
command : bison_command
|
|
|
|
|
)
|
|
|
|
|
|
|
|
|
|
brw_lex_yy_c = custom_target(
|
|
|
|
|
'brw_lex.yy.c',
|
|
|
|
|
input : 'brw_lex.l',
|
|
|
|
|
output : 'brw_lex.yy.c',
|
|
|
|
|
command : [prog_flex, '-o', '@OUTPUT@', '@INPUT@']
|
|
|
|
|
)
|
|
|
|
|
|
2024-07-02 11:57:39 -07:00
|
|
|
brw_asm_deps = [
|
|
|
|
|
dep_thread,
|
|
|
|
|
idep_intel_compiler_brw,
|
|
|
|
|
idep_intel_dev,
|
|
|
|
|
idep_mesautil,
|
|
|
|
|
]
|
|
|
|
|
|
|
|
|
|
brw_asm = static_library(
|
|
|
|
|
'brw_asm',
|
|
|
|
|
['brw_asm.c', brw_gram_tab[0], brw_gram_tab[1], brw_lex_yy_c],
|
|
|
|
|
dependencies : brw_asm_deps,
|
|
|
|
|
include_directories : [inc_include, inc_src, inc_intel],
|
|
|
|
|
c_args : [no_override_init_args],
|
|
|
|
|
gnu_symbol_visibility : 'hidden',
|
|
|
|
|
build_by_default : false,
|
|
|
|
|
)
|
|
|
|
|
|
|
|
|
|
idep_brw_asm = declare_dependency(
|
|
|
|
|
link_with : brw_asm,
|
|
|
|
|
dependencies : brw_asm_deps,
|
|
|
|
|
)
|
|
|
|
|
|
2024-02-09 13:55:14 -08:00
|
|
|
brw_asm_tool = executable(
|
|
|
|
|
'brw_asm',
|
2024-07-02 11:57:39 -07:00
|
|
|
['brw_asm_tool.c'],
|
|
|
|
|
dependencies : idep_brw_asm,
|
2024-02-09 13:55:14 -08:00
|
|
|
include_directories : [inc_include, inc_src, inc_intel],
|
|
|
|
|
c_args : [no_override_init_args],
|
|
|
|
|
gnu_symbol_visibility : 'hidden',
|
|
|
|
|
install : true
|
|
|
|
|
)
|
|
|
|
|
|
|
|
|
|
asm_testcases = [
|
|
|
|
|
['skl', 'gfx9'],
|
|
|
|
|
['icl', 'gfx11'],
|
|
|
|
|
['tgl', 'gfx12'],
|
|
|
|
|
['dg2', 'gfx12.5'],
|
|
|
|
|
]
|
|
|
|
|
|
|
|
|
|
test_runner = find_program('tests/run-test.py')
|
|
|
|
|
foreach testcase : asm_testcases
|
|
|
|
|
_gen_name = testcase[0]
|
|
|
|
|
_gen_num = testcase[1]
|
|
|
|
|
_gen_folder = join_paths(meson.current_source_dir(), 'tests',
|
|
|
|
|
_gen_num.replace('gfx', 'gen'))
|
|
|
|
|
test(
|
|
|
|
|
'brw_asm_' + _gen_num, test_runner,
|
|
|
|
|
args : [
|
|
|
|
|
'--brw_asm', brw_asm_tool,
|
|
|
|
|
'--gen_name', _gen_name,
|
|
|
|
|
'--gen_folder', _gen_folder,
|
|
|
|
|
],
|
|
|
|
|
suite : 'intel',
|
|
|
|
|
)
|
|
|
|
|
endforeach
|
|
|
|
|
|
|
|
|
|
brw_disasm_tool = executable(
|
|
|
|
|
'brw_disasm',
|
|
|
|
|
files('brw_disasm_tool.c'),
|
2024-02-28 17:38:04 -08:00
|
|
|
dependencies : [idep_mesautil, dep_thread, idep_intel_dev,
|
|
|
|
|
idep_intel_compiler_brw],
|
2024-02-09 13:55:14 -08:00
|
|
|
include_directories : [inc_include, inc_src, inc_intel],
|
|
|
|
|
c_args : [no_override_init_args],
|
|
|
|
|
gnu_symbol_visibility : 'hidden',
|
|
|
|
|
install : true
|
|
|
|
|
)
|
|
|
|
|
|
|
|
|
|
endif
|
|
|
|
|
|
2024-01-19 11:44:58 -08:00
|
|
|
subdir('elk')
|