2014-11-10 11:16:30 -08:00
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/*
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* Copyright © 2014-2015 Broadcom
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*/
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#ifndef NIR_BUILDER_H
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#define NIR_BUILDER_H
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2015-08-06 07:16:07 -07:00
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#include "nir_control_flow.h"
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2019-03-06 12:27:26 -06:00
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#include "util/bitscan.h"
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2018-10-22 14:08:44 -05:00
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#include "util/half_float.h"
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2015-08-06 07:16:07 -07:00
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2021-11-19 16:24:00 -08:00
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#ifdef __cplusplus
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extern "C" {
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#endif
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2014-11-10 11:16:30 -08:00
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struct exec_list;
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typedef struct nir_builder {
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2015-08-06 07:16:07 -07:00
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nir_cursor cursor;
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2015-03-27 14:18:54 -07:00
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2016-03-17 15:54:26 -07:00
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/* Whether new ALU instructions will be marked "exact" */
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bool exact;
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2020-09-02 11:48:20 +01:00
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/* Whether to run divergence analysis on inserted instructions (loop merge
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* and header phis are not updated). */
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bool update_divergence;
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2014-11-10 11:16:30 -08:00
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nir_shader *shader;
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nir_function_impl *impl;
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} nir_builder;
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2023-06-26 10:20:04 -04:00
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static inline nir_builder
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nir_builder_create(nir_function_impl *impl)
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{
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nir_builder b;
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2023-07-04 17:48:40 +08:00
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memset(&b, 0, sizeof(b));
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b.exact = false;
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b.impl = impl;
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b.shader = impl->function->shader;
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2023-06-26 10:20:04 -04:00
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return b;
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}
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2023-06-27 12:53:06 +02:00
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/* Requires the cursor to be inside a nir_function_impl. */
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static inline nir_builder
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nir_builder_at(nir_cursor cursor)
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{
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nir_cf_node *current_block = &nir_cursor_current_block(cursor)->cf_node;
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2023-07-04 17:48:40 +08:00
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nir_builder b = nir_builder_create(nir_cf_node_get_function(current_block));
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2023-06-27 12:53:06 +02:00
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b.cursor = cursor;
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return b;
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}
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2021-11-19 16:50:03 -08:00
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nir_builder MUST_CHECK PRINTFLIKE(3, 4)
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2020-10-26 11:28:33 -07:00
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nir_builder_init_simple_shader(gl_shader_stage stage,
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2020-10-26 11:37:25 -07:00
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const nir_shader_compiler_options *options,
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2021-11-19 16:50:03 -08:00
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const char *name, ...);
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2015-12-29 09:56:44 -08:00
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2020-08-20 11:43:29 -07:00
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typedef bool (*nir_instr_pass_cb)(struct nir_builder *, nir_instr *, void *);
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/**
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* Iterates over all the instructions in a NIR shader and calls the given pass
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* on them.
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*
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* The pass should return true if it modified the shader. In that case, only
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* the preserved metadata flags will be preserved in the function impl.
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*
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* The builder will be initialized to point at the function impl, but its
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* cursor is unset.
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*/
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static inline bool
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nir_shader_instructions_pass(nir_shader *shader,
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nir_instr_pass_cb pass,
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nir_metadata preserved,
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void *cb_data)
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{
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bool progress = false;
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2023-06-22 13:27:59 -04:00
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nir_foreach_function_impl(impl, shader) {
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2021-08-06 12:14:38 +02:00
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bool func_progress = false;
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2023-06-22 13:27:59 -04:00
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nir_builder b = nir_builder_create(impl);
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2020-08-20 11:43:29 -07:00
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2023-06-22 13:27:59 -04:00
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nir_foreach_block_safe(block, impl) {
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2020-08-20 11:43:29 -07:00
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nir_foreach_instr_safe(instr, block) {
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2021-08-06 12:14:38 +02:00
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func_progress |= pass(&b, instr, cb_data);
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2020-08-20 11:43:29 -07:00
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}
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}
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2021-08-06 12:14:38 +02:00
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if (func_progress) {
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2023-06-22 13:27:59 -04:00
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nir_metadata_preserve(impl, preserved);
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2021-08-06 12:14:38 +02:00
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progress = true;
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2020-08-20 11:43:29 -07:00
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} else {
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2023-06-22 13:27:59 -04:00
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nir_metadata_preserve(impl, nir_metadata_all);
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2020-08-20 11:43:29 -07:00
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}
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}
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return progress;
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}
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2021-11-19 16:50:03 -08:00
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void nir_builder_instr_insert(nir_builder *build, nir_instr *instr);
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2015-03-27 14:18:54 -07:00
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2016-12-10 12:00:12 -08:00
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static inline nir_instr *
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nir_builder_last_instr(nir_builder *build)
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{
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assert(build->cursor.option == nir_cursor_after_instr);
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return build->cursor.instr;
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}
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2021-11-22 11:45:23 -08:00
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/* General nir_build_alu() taking a variable arg count with NULLs for the rest. */
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2021-11-19 16:50:03 -08:00
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nir_ssa_def *
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nir_build_alu(nir_builder *build, nir_op op, nir_ssa_def *src0,
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nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3);
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2017-02-15 08:42:45 -08:00
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2021-11-22 11:45:23 -08:00
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/* Fixed-arg-count variants to reduce size of codegen. */
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nir_ssa_def *
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nir_build_alu1(nir_builder *build, nir_op op, nir_ssa_def *src0);
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nir_ssa_def *
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nir_build_alu2(nir_builder *build, nir_op op, nir_ssa_def *src0,
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nir_ssa_def *src1);
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nir_ssa_def *
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nir_build_alu3(nir_builder *build, nir_op op, nir_ssa_def *src0,
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nir_ssa_def *src1, nir_ssa_def *src2);
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nir_ssa_def *
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nir_build_alu4(nir_builder *build, nir_op op, nir_ssa_def *src0,
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nir_ssa_def *src1, nir_ssa_def *src2, nir_ssa_def *src3);
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2021-11-19 16:50:03 -08:00
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nir_ssa_def *nir_build_alu_src_arr(nir_builder *build, nir_op op, nir_ssa_def **srcs);
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2017-02-15 08:42:45 -08:00
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2022-11-02 13:37:06 -05:00
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nir_ssa_def *
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nir_build_tex_deref_instr(nir_builder *build, nir_texop op,
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nir_deref_instr *texture,
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nir_deref_instr *sampler,
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unsigned num_extra_srcs,
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const nir_tex_src *extra_srcs);
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2021-11-19 16:50:03 -08:00
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nir_instr *nir_builder_last_instr(nir_builder *build);
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2020-04-06 12:52:06 +02:00
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2021-11-19 16:50:03 -08:00
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void nir_builder_cf_insert(nir_builder *build, nir_cf_node *cf);
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2017-02-15 08:42:45 -08:00
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2021-11-19 16:50:03 -08:00
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bool nir_builder_is_inside_cf(nir_builder *build, nir_cf_node *cf_node);
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2017-02-15 08:42:45 -08:00
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2021-11-19 16:50:03 -08:00
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nir_if *
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nir_push_if_src(nir_builder *build, nir_src condition);
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2017-02-15 08:42:45 -08:00
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2021-11-19 16:50:03 -08:00
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nir_if *
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nir_push_if(nir_builder *build, nir_ssa_def *condition);
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2017-02-15 08:42:45 -08:00
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2021-11-19 16:50:03 -08:00
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nir_if *
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nir_push_else(nir_builder *build, nir_if *nif);
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2017-02-15 08:42:45 -08:00
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2021-11-19 16:50:03 -08:00
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void nir_pop_if(nir_builder *build, nir_if *nif);
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2017-02-15 08:42:45 -08:00
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2021-11-19 16:50:03 -08:00
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nir_ssa_def *
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nir_if_phi(nir_builder *build, nir_ssa_def *then_def, nir_ssa_def *else_def);
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2017-02-15 08:42:45 -08:00
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2021-11-19 16:50:03 -08:00
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nir_loop *
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nir_push_loop(nir_builder *build);
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2017-02-15 08:42:45 -08:00
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2021-12-02 12:26:02 +01:00
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nir_loop *
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nir_push_continue(nir_builder *build, nir_loop *loop);
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2021-11-19 16:50:03 -08:00
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void nir_pop_loop(nir_builder *build, nir_loop *loop);
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2017-02-15 08:42:45 -08:00
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2016-03-25 10:43:46 -07:00
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static inline nir_ssa_def *
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nir_ssa_undef(nir_builder *build, unsigned num_components, unsigned bit_size)
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{
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nir_ssa_undef_instr *undef =
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2016-03-23 08:04:09 +01:00
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nir_ssa_undef_instr_create(build->shader, num_components, bit_size);
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2016-03-25 10:43:46 -07:00
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if (!undef)
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return NULL;
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nir_instr_insert(nir_before_cf_list(&build->impl->body), &undef->instr);
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2020-09-02 11:48:20 +01:00
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if (build->update_divergence)
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nir_update_instr_divergence(build->shader, &undef->instr);
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2016-03-25 10:43:46 -07:00
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return &undef->def;
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}
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2015-03-25 02:11:52 -07:00
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static inline nir_ssa_def *
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2016-03-23 10:43:03 +01:00
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nir_build_imm(nir_builder *build, unsigned num_components,
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2019-03-27 00:59:03 +01:00
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unsigned bit_size, const nir_const_value *value)
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2015-03-25 02:11:52 -07:00
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{
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nir_load_const_instr *load_const =
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2016-03-23 10:43:03 +01:00
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nir_load_const_instr_create(build->shader, num_components, bit_size);
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2015-03-25 02:11:52 -07:00
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if (!load_const)
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return NULL;
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2019-03-27 00:59:03 +01:00
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memcpy(load_const->value, value, sizeof(nir_const_value) * num_components);
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2015-03-25 02:11:52 -07:00
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2015-03-27 14:18:54 -07:00
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nir_builder_instr_insert(build, &load_const->instr);
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2015-03-25 02:11:52 -07:00
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return &load_const->def;
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}
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2019-04-01 21:31:26 -05:00
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static inline nir_ssa_def *
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nir_imm_zero(nir_builder *build, unsigned num_components, unsigned bit_size)
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{
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nir_load_const_instr *load_const =
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nir_load_const_instr_create(build->shader, num_components, bit_size);
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/* nir_load_const_instr_create uses rzalloc so it's already zero */
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nir_builder_instr_insert(build, &load_const->instr);
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return &load_const->def;
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}
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2018-10-19 09:35:49 -05:00
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static inline nir_ssa_def *
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2019-06-24 18:23:29 -05:00
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nir_imm_boolN_t(nir_builder *build, bool x, unsigned bit_size)
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2018-10-19 09:35:49 -05:00
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{
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2019-06-24 18:23:29 -05:00
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nir_const_value v = nir_const_value_for_bool(x, bit_size);
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return nir_build_imm(build, 1, bit_size, &v);
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}
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2018-10-19 09:35:49 -05:00
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2019-06-24 18:23:29 -05:00
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static inline nir_ssa_def *
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nir_imm_bool(nir_builder *build, bool x)
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{
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return nir_imm_boolN_t(build, x, 1);
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2018-10-19 09:35:49 -05:00
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}
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static inline nir_ssa_def *
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nir_imm_true(nir_builder *build)
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{
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return nir_imm_bool(build, true);
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}
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static inline nir_ssa_def *
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nir_imm_false(nir_builder *build)
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{
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return nir_imm_bool(build, false);
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}
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2018-10-22 14:08:44 -05:00
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static inline nir_ssa_def *
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2019-06-24 18:23:29 -05:00
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nir_imm_floatN_t(nir_builder *build, double x, unsigned bit_size)
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2018-10-22 14:08:44 -05:00
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{
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2019-06-24 18:23:29 -05:00
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nir_const_value v = nir_const_value_for_float(x, bit_size);
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return nir_build_imm(build, 1, bit_size, &v);
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2018-10-22 14:08:44 -05:00
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}
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2015-03-25 02:11:52 -07:00
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static inline nir_ssa_def *
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2019-06-24 18:23:29 -05:00
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nir_imm_float16(nir_builder *build, float x)
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2015-03-25 02:11:52 -07:00
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{
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2019-06-24 18:23:29 -05:00
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return nir_imm_floatN_t(build, x, 16);
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2015-03-25 02:11:52 -07:00
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}
|
|
|
|
|
|
2015-07-31 10:52:04 -07:00
|
|
|
static inline nir_ssa_def *
|
2019-06-24 18:23:29 -05:00
|
|
|
nir_imm_float(nir_builder *build, float x)
|
2015-07-31 10:52:04 -07:00
|
|
|
{
|
2019-06-24 18:23:29 -05:00
|
|
|
return nir_imm_floatN_t(build, x, 32);
|
2015-07-31 10:52:04 -07:00
|
|
|
}
|
|
|
|
|
|
2018-03-21 20:34:37 +01:00
|
|
|
static inline nir_ssa_def *
|
2019-06-24 18:23:29 -05:00
|
|
|
nir_imm_double(nir_builder *build, double x)
|
2018-03-21 20:34:37 +01:00
|
|
|
{
|
2019-06-24 18:23:29 -05:00
|
|
|
return nir_imm_floatN_t(build, x, 64);
|
2018-03-21 20:34:37 +01:00
|
|
|
}
|
|
|
|
|
|
2019-03-30 00:53:42 +01:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_imm_vec2(nir_builder *build, float x, float y)
|
|
|
|
|
{
|
2019-06-24 18:23:29 -05:00
|
|
|
nir_const_value v[2] = {
|
|
|
|
|
nir_const_value_for_float(x, 32),
|
|
|
|
|
nir_const_value_for_float(y, 32),
|
|
|
|
|
};
|
2019-03-30 00:53:42 +01:00
|
|
|
return nir_build_imm(build, 2, 32, v);
|
|
|
|
|
}
|
|
|
|
|
|
2015-03-25 02:11:52 -07:00
|
|
|
static inline nir_ssa_def *
|
2021-08-06 14:47:37 -04:00
|
|
|
nir_imm_vec3(nir_builder *build, float x, float y, float z)
|
|
|
|
|
{
|
|
|
|
|
nir_const_value v[3] = {
|
|
|
|
|
nir_const_value_for_float(x, 32),
|
|
|
|
|
nir_const_value_for_float(y, 32),
|
|
|
|
|
nir_const_value_for_float(z, 32),
|
|
|
|
|
};
|
|
|
|
|
return nir_build_imm(build, 3, 32, v);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
2015-03-25 02:11:52 -07:00
|
|
|
nir_imm_vec4(nir_builder *build, float x, float y, float z, float w)
|
|
|
|
|
{
|
2019-06-24 18:23:29 -05:00
|
|
|
nir_const_value v[4] = {
|
|
|
|
|
nir_const_value_for_float(x, 32),
|
|
|
|
|
nir_const_value_for_float(y, 32),
|
|
|
|
|
nir_const_value_for_float(z, 32),
|
|
|
|
|
nir_const_value_for_float(w, 32),
|
|
|
|
|
};
|
2015-09-21 08:22:12 -07:00
|
|
|
|
2016-03-23 10:43:03 +01:00
|
|
|
return nir_build_imm(build, 4, 32, v);
|
2015-03-25 02:11:52 -07:00
|
|
|
}
|
|
|
|
|
|
2019-07-03 13:00:14 -07:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_imm_vec4_16(nir_builder *build, float x, float y, float z, float w)
|
|
|
|
|
{
|
2019-06-24 18:23:29 -05:00
|
|
|
nir_const_value v[4] = {
|
|
|
|
|
nir_const_value_for_float(x, 16),
|
|
|
|
|
nir_const_value_for_float(y, 16),
|
|
|
|
|
nir_const_value_for_float(z, 16),
|
|
|
|
|
nir_const_value_for_float(w, 16),
|
|
|
|
|
};
|
2019-07-03 13:00:14 -07:00
|
|
|
|
|
|
|
|
return nir_build_imm(build, 4, 16, v);
|
|
|
|
|
}
|
|
|
|
|
|
2015-03-25 02:11:52 -07:00
|
|
|
static inline nir_ssa_def *
|
2019-06-24 18:23:29 -05:00
|
|
|
nir_imm_intN_t(nir_builder *build, uint64_t x, unsigned bit_size)
|
2018-10-10 17:14:34 -07:00
|
|
|
{
|
2019-06-24 18:23:29 -05:00
|
|
|
nir_const_value v = nir_const_value_for_raw_uint(x, bit_size);
|
|
|
|
|
return nir_build_imm(build, 1, bit_size, &v);
|
2018-10-10 17:14:34 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
2015-03-25 02:11:52 -07:00
|
|
|
nir_imm_int(nir_builder *build, int x)
|
|
|
|
|
{
|
2019-06-24 18:23:29 -05:00
|
|
|
return nir_imm_intN_t(build, x, 32);
|
2015-03-25 02:11:52 -07:00
|
|
|
}
|
2014-11-10 11:16:30 -08:00
|
|
|
|
2017-02-23 21:35:00 -08:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_imm_int64(nir_builder *build, int64_t x)
|
|
|
|
|
{
|
2019-06-24 18:23:29 -05:00
|
|
|
return nir_imm_intN_t(build, x, 64);
|
2017-02-23 21:35:00 -08:00
|
|
|
}
|
|
|
|
|
|
2017-10-31 14:42:33 -07:00
|
|
|
static inline nir_ssa_def *
|
2019-06-24 18:23:29 -05:00
|
|
|
nir_imm_ivec2(nir_builder *build, int x, int y)
|
2017-10-31 14:42:33 -07:00
|
|
|
{
|
2019-06-24 18:23:29 -05:00
|
|
|
nir_const_value v[2] = {
|
|
|
|
|
nir_const_value_for_int(x, 32),
|
|
|
|
|
nir_const_value_for_int(y, 32),
|
|
|
|
|
};
|
2017-10-31 14:42:33 -07:00
|
|
|
|
2019-06-24 18:23:29 -05:00
|
|
|
return nir_build_imm(build, 2, 32, v);
|
2017-10-31 14:42:33 -07:00
|
|
|
}
|
|
|
|
|
|
2021-07-20 12:07:48 -04:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_imm_ivec3(nir_builder *build, int x, int y, int z)
|
|
|
|
|
{
|
|
|
|
|
nir_const_value v[3] = {
|
|
|
|
|
nir_const_value_for_int(x, 32),
|
|
|
|
|
nir_const_value_for_int(y, 32),
|
|
|
|
|
nir_const_value_for_int(z, 32),
|
|
|
|
|
};
|
|
|
|
|
|
|
|
|
|
return nir_build_imm(build, 3, 32, v);
|
|
|
|
|
}
|
|
|
|
|
|
2016-01-13 13:32:44 -08:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_imm_ivec4(nir_builder *build, int x, int y, int z, int w)
|
|
|
|
|
{
|
2019-06-24 18:23:29 -05:00
|
|
|
nir_const_value v[4] = {
|
|
|
|
|
nir_const_value_for_int(x, 32),
|
|
|
|
|
nir_const_value_for_int(y, 32),
|
|
|
|
|
nir_const_value_for_int(z, 32),
|
|
|
|
|
nir_const_value_for_int(w, 32),
|
|
|
|
|
};
|
2016-01-13 13:32:44 -08:00
|
|
|
|
2016-03-23 10:43:03 +01:00
|
|
|
return nir_build_imm(build, 4, 32, v);
|
2016-01-13 13:32:44 -08:00
|
|
|
}
|
|
|
|
|
|
2021-11-19 16:24:00 -08:00
|
|
|
nir_ssa_def *
|
|
|
|
|
nir_builder_alu_instr_finish_and_insert(nir_builder *build, nir_alu_instr *instr);
|
2014-11-10 11:16:30 -08:00
|
|
|
|
2019-03-20 18:09:20 +01:00
|
|
|
/* for the couple special cases with more than 4 src args: */
|
2021-11-19 16:50:03 -08:00
|
|
|
nir_ssa_def *
|
|
|
|
|
nir_build_alu_src_arr(nir_builder *build, nir_op op, nir_ssa_def **srcs);
|
2019-03-20 18:09:20 +01:00
|
|
|
|
2020-09-14 19:56:48 +01:00
|
|
|
/* Generic builder for system values. */
|
2021-11-19 16:50:03 -08:00
|
|
|
nir_ssa_def *
|
2020-09-14 19:56:48 +01:00
|
|
|
nir_load_system_value(nir_builder *build, nir_intrinsic_op op, int index,
|
2021-11-19 16:50:03 -08:00
|
|
|
unsigned num_components, unsigned bit_size);
|
2020-09-14 19:56:48 +01:00
|
|
|
|
2014-11-10 11:16:30 -08:00
|
|
|
#include "nir_builder_opcodes.h"
|
2020-09-07 13:55:38 +01:00
|
|
|
#undef nir_deref_mode_is
|
2014-11-10 11:16:30 -08:00
|
|
|
|
2022-11-29 12:56:37 -06:00
|
|
|
nir_ssa_def *
|
|
|
|
|
nir_type_convert(nir_builder *b,
|
|
|
|
|
nir_ssa_def *src,
|
|
|
|
|
nir_alu_type src_type,
|
2022-11-01 16:38:26 -07:00
|
|
|
nir_alu_type dest_type,
|
|
|
|
|
nir_rounding_mode rnd);
|
2022-11-29 12:56:37 -06:00
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_convert_to_bit_size(nir_builder *b,
|
|
|
|
|
nir_ssa_def *src,
|
|
|
|
|
nir_alu_type type,
|
|
|
|
|
unsigned bit_size)
|
|
|
|
|
{
|
2022-11-01 16:38:26 -07:00
|
|
|
return nir_type_convert(b, src, type, (nir_alu_type) (type | bit_size),
|
|
|
|
|
nir_rounding_mode_undef);
|
2022-11-29 12:56:37 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_i2iN(nir_builder *b, nir_ssa_def *src, unsigned bit_size)
|
|
|
|
|
{
|
|
|
|
|
return nir_convert_to_bit_size(b, src, nir_type_int, bit_size);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_u2uN(nir_builder *b, nir_ssa_def *src, unsigned bit_size)
|
|
|
|
|
{
|
|
|
|
|
return nir_convert_to_bit_size(b, src, nir_type_uint, bit_size);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_b2bN(nir_builder *b, nir_ssa_def *src, unsigned bit_size)
|
|
|
|
|
{
|
|
|
|
|
return nir_convert_to_bit_size(b, src, nir_type_bool, bit_size);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_f2fN(nir_builder *b, nir_ssa_def *src, unsigned bit_size)
|
|
|
|
|
{
|
|
|
|
|
return nir_convert_to_bit_size(b, src, nir_type_float, bit_size);
|
|
|
|
|
}
|
|
|
|
|
|
2022-11-29 13:10:42 -06:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_i2b(nir_builder *b, nir_ssa_def *src)
|
|
|
|
|
{
|
2023-05-08 14:00:41 +02:00
|
|
|
return nir_ine_imm(b, src, 0);
|
2022-11-29 13:10:42 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_b2iN(nir_builder *b, nir_ssa_def *src, uint32_t bit_size)
|
|
|
|
|
{
|
|
|
|
|
return nir_type_convert(b, src, nir_type_bool,
|
2022-11-01 16:38:26 -07:00
|
|
|
(nir_alu_type) (nir_type_int | bit_size),
|
|
|
|
|
nir_rounding_mode_undef);
|
2022-11-29 13:10:42 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_b2fN(nir_builder *b, nir_ssa_def *src, uint32_t bit_size)
|
|
|
|
|
{
|
|
|
|
|
return nir_type_convert(b, src, nir_type_bool,
|
2022-11-01 16:38:26 -07:00
|
|
|
(nir_alu_type) (nir_type_float | bit_size),
|
|
|
|
|
nir_rounding_mode_undef);
|
2022-11-29 13:10:42 -06:00
|
|
|
}
|
|
|
|
|
|
2022-11-29 12:56:37 -06:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_i2fN(nir_builder *b, nir_ssa_def *src, unsigned bit_size)
|
|
|
|
|
{
|
|
|
|
|
return nir_type_convert(b, src, nir_type_int,
|
2022-11-01 16:38:26 -07:00
|
|
|
(nir_alu_type) (nir_type_float | bit_size),
|
|
|
|
|
nir_rounding_mode_undef);
|
2022-11-29 12:56:37 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_u2fN(nir_builder *b, nir_ssa_def *src, unsigned bit_size)
|
|
|
|
|
{
|
|
|
|
|
return nir_type_convert(b, src, nir_type_uint,
|
2022-11-01 16:38:26 -07:00
|
|
|
(nir_alu_type) (nir_type_float | bit_size),
|
|
|
|
|
nir_rounding_mode_undef);
|
2022-11-29 12:56:37 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_f2uN(nir_builder *b, nir_ssa_def *src, unsigned bit_size)
|
|
|
|
|
{
|
|
|
|
|
return nir_type_convert(b, src, nir_type_float,
|
2022-11-01 16:38:26 -07:00
|
|
|
(nir_alu_type) (nir_type_uint | bit_size),
|
|
|
|
|
nir_rounding_mode_undef);
|
2022-11-29 12:56:37 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_f2iN(nir_builder *b, nir_ssa_def *src, unsigned bit_size)
|
|
|
|
|
{
|
|
|
|
|
return nir_type_convert(b, src, nir_type_float,
|
2022-11-01 16:38:26 -07:00
|
|
|
(nir_alu_type) (nir_type_int | bit_size),
|
|
|
|
|
nir_rounding_mode_undef);
|
2022-11-29 12:56:37 -06:00
|
|
|
}
|
|
|
|
|
|
2015-09-18 13:23:36 -04:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_vec(nir_builder *build, nir_ssa_def **comp, unsigned num_components)
|
|
|
|
|
{
|
2019-03-20 18:11:20 +01:00
|
|
|
return nir_build_alu_src_arr(build, nir_op_vec(num_components), comp);
|
2015-09-18 13:23:36 -04:00
|
|
|
}
|
|
|
|
|
|
2022-02-03 11:11:00 -08:00
|
|
|
nir_ssa_def *
|
|
|
|
|
nir_vec_scalars(nir_builder *build, nir_ssa_scalar *comp, unsigned num_components);
|
|
|
|
|
|
2015-03-25 14:51:02 -07:00
|
|
|
static inline nir_ssa_def *
|
2019-05-06 11:26:27 -05:00
|
|
|
nir_mov_alu(nir_builder *build, nir_alu_src src, unsigned num_components)
|
2015-03-25 14:51:02 -07:00
|
|
|
{
|
2019-05-06 11:26:27 -05:00
|
|
|
assert(!src.abs && !src.negate);
|
2019-09-16 14:34:20 -07:00
|
|
|
if (src.src.is_ssa && src.src.ssa->num_components == num_components) {
|
|
|
|
|
bool any_swizzles = false;
|
|
|
|
|
for (unsigned i = 0; i < num_components; i++) {
|
|
|
|
|
if (src.swizzle[i] != i)
|
|
|
|
|
any_swizzles = true;
|
|
|
|
|
}
|
|
|
|
|
if (!any_swizzles)
|
|
|
|
|
return src.src.ssa;
|
|
|
|
|
}
|
|
|
|
|
|
2019-05-06 11:45:46 -05:00
|
|
|
nir_alu_instr *mov = nir_alu_instr_create(build->shader, nir_op_mov);
|
2015-11-17 13:57:54 +01:00
|
|
|
nir_ssa_dest_init(&mov->instr, &mov->dest.dest, num_components,
|
nir: Drop unused name from nir_ssa_dest_init
Since 624e799cc34 ("nir: Drop nir_ssa_def::name and nir_register::name"), SSA
defs don't have names, making the name argument unused. Drop it from the
signature and fix the call sites. This was done with the help of the following
Coccinelle semantic patch:
@@
expression A, B, C, D, E;
@@
-nir_ssa_dest_init(A, B, C, D, E);
+nir_ssa_dest_init(A, B, C, D);
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23078>
2023-05-17 09:08:22 -04:00
|
|
|
nir_src_bit_size(src.src));
|
2016-03-17 15:54:26 -07:00
|
|
|
mov->exact = build->exact;
|
2015-03-25 14:51:02 -07:00
|
|
|
mov->dest.write_mask = (1 << num_components) - 1;
|
|
|
|
|
mov->src[0] = src;
|
2015-03-27 14:18:54 -07:00
|
|
|
nir_builder_instr_insert(build, &mov->instr);
|
2015-03-25 14:51:02 -07:00
|
|
|
|
|
|
|
|
return &mov->dest.dest.ssa;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
2021-04-16 19:40:14 -04:00
|
|
|
* Construct a mov that reswizzles the source's components.
|
2015-03-25 14:51:02 -07:00
|
|
|
*/
|
|
|
|
|
static inline nir_ssa_def *
|
2018-07-13 03:33:22 +02:00
|
|
|
nir_swizzle(nir_builder *build, nir_ssa_def *src, const unsigned *swiz,
|
2019-05-06 10:23:26 -05:00
|
|
|
unsigned num_components)
|
2015-03-25 14:51:02 -07:00
|
|
|
{
|
2018-07-12 03:40:23 +02:00
|
|
|
assert(num_components <= NIR_MAX_VEC_COMPONENTS);
|
2015-04-21 18:00:21 -07:00
|
|
|
nir_alu_src alu_src = { NIR_SRC_INIT };
|
2015-03-25 14:51:02 -07:00
|
|
|
alu_src.src = nir_src_for_ssa(src);
|
2019-02-22 17:06:39 -06:00
|
|
|
|
|
|
|
|
bool is_identity_swizzle = true;
|
|
|
|
|
for (unsigned i = 0; i < num_components && i < NIR_MAX_VEC_COMPONENTS; i++) {
|
|
|
|
|
if (swiz[i] != i)
|
|
|
|
|
is_identity_swizzle = false;
|
2015-03-25 14:51:02 -07:00
|
|
|
alu_src.swizzle[i] = swiz[i];
|
2019-02-22 17:06:39 -06:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (num_components == src->num_components && is_identity_swizzle)
|
|
|
|
|
return src;
|
2015-03-25 14:51:02 -07:00
|
|
|
|
2019-05-06 11:26:27 -05:00
|
|
|
return nir_mov_alu(build, alu_src, num_components);
|
2015-03-25 14:51:02 -07:00
|
|
|
}
|
|
|
|
|
|
2016-03-25 10:34:17 -07:00
|
|
|
/* Selects the right fdot given the number of components in each source. */
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_fdot(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
|
|
|
|
|
{
|
|
|
|
|
assert(src0->num_components == src1->num_components);
|
|
|
|
|
switch (src0->num_components) {
|
|
|
|
|
case 1: return nir_fmul(build, src0, src1);
|
|
|
|
|
case 2: return nir_fdot2(build, src0, src1);
|
|
|
|
|
case 3: return nir_fdot3(build, src0, src1);
|
|
|
|
|
case 4: return nir_fdot4(build, src0, src1);
|
2020-11-23 13:05:58 +00:00
|
|
|
case 5: return nir_fdot5(build, src0, src1);
|
2020-06-22 16:48:43 -07:00
|
|
|
case 8: return nir_fdot8(build, src0, src1);
|
|
|
|
|
case 16: return nir_fdot16(build, src0, src1);
|
2016-03-25 10:34:17 -07:00
|
|
|
default:
|
|
|
|
|
unreachable("bad component size");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return NULL;
|
|
|
|
|
}
|
|
|
|
|
|
2019-05-31 13:48:34 -07:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_ball_iequal(nir_builder *b, nir_ssa_def *src0, nir_ssa_def *src1)
|
|
|
|
|
{
|
|
|
|
|
switch (src0->num_components) {
|
|
|
|
|
case 1: return nir_ieq(b, src0, src1);
|
|
|
|
|
case 2: return nir_ball_iequal2(b, src0, src1);
|
|
|
|
|
case 3: return nir_ball_iequal3(b, src0, src1);
|
|
|
|
|
case 4: return nir_ball_iequal4(b, src0, src1);
|
2020-11-23 13:05:58 +00:00
|
|
|
case 5: return nir_ball_iequal5(b, src0, src1);
|
2020-06-22 16:48:43 -07:00
|
|
|
case 8: return nir_ball_iequal8(b, src0, src1);
|
|
|
|
|
case 16: return nir_ball_iequal16(b, src0, src1);
|
2019-05-31 13:48:34 -07:00
|
|
|
default:
|
|
|
|
|
unreachable("bad component size");
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2020-05-28 23:00:21 -05:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_ball(nir_builder *b, nir_ssa_def *src)
|
|
|
|
|
{
|
|
|
|
|
return nir_ball_iequal(b, src, nir_imm_true(b));
|
|
|
|
|
}
|
|
|
|
|
|
2016-08-17 05:03:29 -07:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_bany_inequal(nir_builder *b, nir_ssa_def *src0, nir_ssa_def *src1)
|
|
|
|
|
{
|
|
|
|
|
switch (src0->num_components) {
|
|
|
|
|
case 1: return nir_ine(b, src0, src1);
|
|
|
|
|
case 2: return nir_bany_inequal2(b, src0, src1);
|
|
|
|
|
case 3: return nir_bany_inequal3(b, src0, src1);
|
|
|
|
|
case 4: return nir_bany_inequal4(b, src0, src1);
|
2020-11-23 13:05:58 +00:00
|
|
|
case 5: return nir_bany_inequal5(b, src0, src1);
|
2020-06-22 16:48:43 -07:00
|
|
|
case 8: return nir_bany_inequal8(b, src0, src1);
|
|
|
|
|
case 16: return nir_bany_inequal16(b, src0, src1);
|
2016-08-17 05:03:29 -07:00
|
|
|
default:
|
|
|
|
|
unreachable("bad component size");
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_bany(nir_builder *b, nir_ssa_def *src)
|
|
|
|
|
{
|
2018-10-19 09:35:49 -05:00
|
|
|
return nir_bany_inequal(b, src, nir_imm_false(b));
|
2016-08-17 05:03:29 -07:00
|
|
|
}
|
|
|
|
|
|
2015-09-10 16:06:05 -04:00
|
|
|
static inline nir_ssa_def *
|
2015-09-17 21:07:41 -04:00
|
|
|
nir_channel(nir_builder *b, nir_ssa_def *def, unsigned c)
|
2015-09-10 16:06:05 -04:00
|
|
|
{
|
2019-05-06 10:23:26 -05:00
|
|
|
return nir_swizzle(b, def, &c, 1);
|
2015-09-10 16:06:05 -04:00
|
|
|
}
|
|
|
|
|
|
2016-05-02 16:29:05 -07:00
|
|
|
static inline nir_ssa_def *
|
2018-07-12 03:40:23 +02:00
|
|
|
nir_channels(nir_builder *b, nir_ssa_def *def, nir_component_mask_t mask)
|
2016-05-02 16:29:05 -07:00
|
|
|
{
|
2018-07-12 03:40:23 +02:00
|
|
|
unsigned num_channels = 0, swizzle[NIR_MAX_VEC_COMPONENTS] = { 0 };
|
2016-05-02 16:29:05 -07:00
|
|
|
|
2018-07-12 03:40:23 +02:00
|
|
|
for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++) {
|
2016-05-02 16:29:05 -07:00
|
|
|
if ((mask & (1 << i)) == 0)
|
|
|
|
|
continue;
|
|
|
|
|
swizzle[num_channels++] = i;
|
|
|
|
|
}
|
|
|
|
|
|
2019-05-06 10:23:26 -05:00
|
|
|
return nir_swizzle(b, def, swizzle, num_channels);
|
2016-05-02 16:29:05 -07:00
|
|
|
}
|
|
|
|
|
|
2019-03-11 18:58:24 -05:00
|
|
|
static inline nir_ssa_def *
|
2020-06-18 12:46:01 -05:00
|
|
|
_nir_select_from_array_helper(nir_builder *b, nir_ssa_def **arr,
|
|
|
|
|
nir_ssa_def *idx,
|
|
|
|
|
unsigned start, unsigned end)
|
2019-03-11 18:58:24 -05:00
|
|
|
{
|
|
|
|
|
if (start == end - 1) {
|
2020-06-18 12:46:01 -05:00
|
|
|
return arr[start];
|
2019-03-11 18:58:24 -05:00
|
|
|
} else {
|
|
|
|
|
unsigned mid = start + (end - start) / 2;
|
2023-05-08 14:00:41 +02:00
|
|
|
return nir_bcsel(b, nir_ilt_imm(b, idx, mid),
|
2020-06-18 12:46:01 -05:00
|
|
|
_nir_select_from_array_helper(b, arr, idx, start, mid),
|
|
|
|
|
_nir_select_from_array_helper(b, arr, idx, mid, end));
|
2019-03-11 18:58:24 -05:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2020-06-18 12:46:01 -05:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_select_from_ssa_def_array(nir_builder *b, nir_ssa_def **arr,
|
|
|
|
|
unsigned arr_len, nir_ssa_def *idx)
|
|
|
|
|
{
|
|
|
|
|
return _nir_select_from_array_helper(b, arr, idx, 0, arr_len);
|
|
|
|
|
}
|
|
|
|
|
|
2019-03-11 18:58:24 -05:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_vector_extract(nir_builder *b, nir_ssa_def *vec, nir_ssa_def *c)
|
|
|
|
|
{
|
|
|
|
|
nir_src c_src = nir_src_for_ssa(c);
|
|
|
|
|
if (nir_src_is_const(c_src)) {
|
2020-04-17 09:52:25 -05:00
|
|
|
uint64_t c_const = nir_src_as_uint(c_src);
|
2019-03-11 18:58:24 -05:00
|
|
|
if (c_const < vec->num_components)
|
|
|
|
|
return nir_channel(b, vec, c_const);
|
|
|
|
|
else
|
|
|
|
|
return nir_ssa_undef(b, 1, vec->bit_size);
|
|
|
|
|
} else {
|
2020-06-18 12:46:01 -05:00
|
|
|
nir_ssa_def *comps[NIR_MAX_VEC_COMPONENTS];
|
|
|
|
|
for (unsigned i = 0; i < vec->num_components; i++)
|
|
|
|
|
comps[i] = nir_channel(b, vec, i);
|
|
|
|
|
return nir_select_from_ssa_def_array(b, comps, vec->num_components, c);
|
2019-03-11 18:58:24 -05:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2020-04-09 17:09:10 -05:00
|
|
|
/** Replaces the component of `vec` specified by `c` with `scalar` */
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_vector_insert_imm(nir_builder *b, nir_ssa_def *vec,
|
|
|
|
|
nir_ssa_def *scalar, unsigned c)
|
|
|
|
|
{
|
|
|
|
|
assert(scalar->num_components == 1);
|
|
|
|
|
assert(c < vec->num_components);
|
|
|
|
|
|
|
|
|
|
nir_op vec_op = nir_op_vec(vec->num_components);
|
|
|
|
|
nir_alu_instr *vec_instr = nir_alu_instr_create(b->shader, vec_op);
|
|
|
|
|
|
|
|
|
|
for (unsigned i = 0; i < vec->num_components; i++) {
|
|
|
|
|
if (i == c) {
|
|
|
|
|
vec_instr->src[i].src = nir_src_for_ssa(scalar);
|
|
|
|
|
vec_instr->src[i].swizzle[0] = 0;
|
|
|
|
|
} else {
|
|
|
|
|
vec_instr->src[i].src = nir_src_for_ssa(vec);
|
|
|
|
|
vec_instr->src[i].swizzle[0] = i;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
return nir_builder_alu_instr_finish_and_insert(b, vec_instr);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/** Replaces the component of `vec` specified by `c` with `scalar` */
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_vector_insert(nir_builder *b, nir_ssa_def *vec, nir_ssa_def *scalar,
|
|
|
|
|
nir_ssa_def *c)
|
|
|
|
|
{
|
|
|
|
|
assert(scalar->num_components == 1);
|
|
|
|
|
assert(c->num_components == 1);
|
|
|
|
|
|
|
|
|
|
nir_src c_src = nir_src_for_ssa(c);
|
|
|
|
|
if (nir_src_is_const(c_src)) {
|
|
|
|
|
uint64_t c_const = nir_src_as_uint(c_src);
|
|
|
|
|
if (c_const < vec->num_components)
|
|
|
|
|
return nir_vector_insert_imm(b, vec, scalar, c_const);
|
|
|
|
|
else
|
|
|
|
|
return vec;
|
|
|
|
|
} else {
|
|
|
|
|
nir_const_value per_comp_idx_const[NIR_MAX_VEC_COMPONENTS];
|
|
|
|
|
for (unsigned i = 0; i < NIR_MAX_VEC_COMPONENTS; i++)
|
|
|
|
|
per_comp_idx_const[i] = nir_const_value_for_int(i, c->bit_size);
|
|
|
|
|
nir_ssa_def *per_comp_idx =
|
|
|
|
|
nir_build_imm(b, vec->num_components,
|
|
|
|
|
c->bit_size, per_comp_idx_const);
|
|
|
|
|
|
|
|
|
|
/* nir_builder will automatically splat out scalars to vectors so an
|
|
|
|
|
* insert is as simple as "if I'm the channel, replace me with the
|
|
|
|
|
* scalar."
|
|
|
|
|
*/
|
|
|
|
|
return nir_bcsel(b, nir_ieq(b, c, per_comp_idx), scalar, vec);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2023-05-26 11:10:58 -04:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_replicate(nir_builder *b, nir_ssa_def *scalar, unsigned num_components)
|
|
|
|
|
{
|
|
|
|
|
assert(scalar->num_components == 1);
|
|
|
|
|
assert(num_components < NIR_MAX_VEC_COMPONENTS);
|
|
|
|
|
|
|
|
|
|
nir_ssa_def *copies[NIR_MAX_VEC_COMPONENTS] = {NULL};
|
|
|
|
|
for (unsigned i = 0; i < num_components; ++i)
|
|
|
|
|
copies[i] = scalar;
|
|
|
|
|
|
|
|
|
|
return nir_vec(b, copies, num_components);
|
|
|
|
|
}
|
|
|
|
|
|
2018-11-12 15:58:18 -06:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_iadd_imm(nir_builder *build, nir_ssa_def *x, uint64_t y)
|
|
|
|
|
{
|
2019-03-06 12:27:26 -06:00
|
|
|
assert(x->bit_size <= 64);
|
2020-08-21 11:15:24 -07:00
|
|
|
y &= BITFIELD64_MASK(x->bit_size);
|
2019-03-06 12:27:26 -06:00
|
|
|
|
|
|
|
|
if (y == 0) {
|
|
|
|
|
return x;
|
|
|
|
|
} else {
|
|
|
|
|
return nir_iadd(build, x, nir_imm_intN_t(build, y, x->bit_size));
|
|
|
|
|
}
|
2018-11-12 15:58:18 -06:00
|
|
|
}
|
|
|
|
|
|
2021-02-16 18:18:52 +01:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_iadd_imm_nuw(nir_builder *b, nir_ssa_def *x, uint64_t y)
|
|
|
|
|
{
|
|
|
|
|
nir_ssa_def *d = nir_iadd_imm(b, x, y);
|
|
|
|
|
if (d != x && d->parent_instr->type == nir_instr_type_alu)
|
|
|
|
|
nir_instr_as_alu(d->parent_instr)->no_unsigned_wrap = true;
|
|
|
|
|
return d;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_iadd_nuw(nir_builder *b, nir_ssa_def *x, nir_ssa_def *y)
|
|
|
|
|
{
|
|
|
|
|
nir_ssa_def *d = nir_iadd(b, x, y);
|
|
|
|
|
nir_instr_as_alu(d->parent_instr)->no_unsigned_wrap = true;
|
|
|
|
|
return d;
|
|
|
|
|
}
|
2020-08-15 00:11:27 -05:00
|
|
|
|
2023-06-05 10:19:58 +02:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_fgt_imm(nir_builder *build, nir_ssa_def *src1, double src2)
|
|
|
|
|
{
|
|
|
|
|
return nir_flt(build, nir_imm_floatN_t(build, src2, src1->bit_size), src1);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_fle_imm(nir_builder *build, nir_ssa_def *src1, double src2)
|
|
|
|
|
{
|
|
|
|
|
return nir_fge(build, nir_imm_floatN_t(build, src2, src1->bit_size), src1);
|
|
|
|
|
}
|
|
|
|
|
|
2021-05-05 14:14:13 -04:00
|
|
|
/* Use nir_iadd(x, -y) for reversing parameter ordering */
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_isub_imm(nir_builder *build, uint64_t y, nir_ssa_def *x)
|
|
|
|
|
{
|
|
|
|
|
return nir_isub(build, nir_imm_intN_t(build, y, x->bit_size), x);
|
|
|
|
|
}
|
|
|
|
|
|
2018-11-12 15:58:18 -06:00
|
|
|
static inline nir_ssa_def *
|
2019-09-26 10:32:00 -07:00
|
|
|
_nir_mul_imm(nir_builder *build, nir_ssa_def *x, uint64_t y, bool amul)
|
2018-11-12 15:58:18 -06:00
|
|
|
{
|
2019-03-06 12:27:26 -06:00
|
|
|
assert(x->bit_size <= 64);
|
2020-08-21 11:15:24 -07:00
|
|
|
y &= BITFIELD64_MASK(x->bit_size);
|
2019-03-06 12:27:26 -06:00
|
|
|
|
|
|
|
|
if (y == 0) {
|
|
|
|
|
return nir_imm_intN_t(build, 0, x->bit_size);
|
|
|
|
|
} else if (y == 1) {
|
|
|
|
|
return x;
|
2020-01-22 20:29:50 -08:00
|
|
|
} else if (!build->shader->options->lower_bitops &&
|
|
|
|
|
util_is_power_of_two_or_zero64(y)) {
|
2019-03-06 12:27:26 -06:00
|
|
|
return nir_ishl(build, x, nir_imm_int(build, ffsll(y) - 1));
|
2019-09-26 10:32:00 -07:00
|
|
|
} else if (amul) {
|
|
|
|
|
return nir_amul(build, x, nir_imm_intN_t(build, y, x->bit_size));
|
2019-03-06 12:27:26 -06:00
|
|
|
} else {
|
|
|
|
|
return nir_imul(build, x, nir_imm_intN_t(build, y, x->bit_size));
|
|
|
|
|
}
|
2018-11-12 15:58:18 -06:00
|
|
|
}
|
|
|
|
|
|
2019-09-26 10:32:00 -07:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_imul_imm(nir_builder *build, nir_ssa_def *x, uint64_t y)
|
|
|
|
|
{
|
|
|
|
|
return _nir_mul_imm(build, x, y, false);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_amul_imm(nir_builder *build, nir_ssa_def *x, uint64_t y)
|
|
|
|
|
{
|
|
|
|
|
return _nir_mul_imm(build, x, y, true);
|
|
|
|
|
}
|
|
|
|
|
|
2018-12-14 09:28:56 +01:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_fadd_imm(nir_builder *build, nir_ssa_def *x, double y)
|
|
|
|
|
{
|
|
|
|
|
return nir_fadd(build, x, nir_imm_floatN_t(build, y, x->bit_size));
|
|
|
|
|
}
|
|
|
|
|
|
2023-05-08 09:07:53 +02:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_fsub_imm(nir_builder *build, double x, nir_ssa_def *y)
|
|
|
|
|
{
|
|
|
|
|
return nir_fsub(build, nir_imm_floatN_t(build, x, y->bit_size), y);
|
|
|
|
|
}
|
|
|
|
|
|
2018-12-14 09:28:56 +01:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_fmul_imm(nir_builder *build, nir_ssa_def *x, double y)
|
|
|
|
|
{
|
|
|
|
|
return nir_fmul(build, x, nir_imm_floatN_t(build, y, x->bit_size));
|
|
|
|
|
}
|
|
|
|
|
|
2020-06-11 17:32:11 -05:00
|
|
|
static inline nir_ssa_def *
|
2023-06-05 15:15:21 +02:00
|
|
|
nir_fdiv_imm(nir_builder *build, nir_ssa_def *x, double y)
|
|
|
|
|
{
|
|
|
|
|
return nir_fdiv(build, x, nir_imm_floatN_t(build, y, x->bit_size));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
2020-06-11 17:32:11 -05:00
|
|
|
nir_iand_imm(nir_builder *build, nir_ssa_def *x, uint64_t y)
|
|
|
|
|
{
|
2020-08-21 11:15:24 -07:00
|
|
|
assert(x->bit_size <= 64);
|
2020-06-11 17:32:11 -05:00
|
|
|
y &= BITFIELD64_MASK(x->bit_size);
|
|
|
|
|
|
|
|
|
|
if (y == 0) {
|
|
|
|
|
return nir_imm_intN_t(build, 0, x->bit_size);
|
|
|
|
|
} else if (y == BITFIELD64_MASK(x->bit_size)) {
|
|
|
|
|
return x;
|
|
|
|
|
} else {
|
|
|
|
|
return nir_iand(build, x, nir_imm_intN_t(build, y, x->bit_size));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2022-06-24 21:12:41 +02:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_test_mask(nir_builder *build, nir_ssa_def *x, uint64_t mask)
|
|
|
|
|
{
|
|
|
|
|
assert(mask <= BITFIELD64_MASK(x->bit_size));
|
|
|
|
|
return nir_ine_imm(build, nir_iand_imm(build, x, mask), 0);
|
|
|
|
|
}
|
|
|
|
|
|
2021-10-22 16:10:20 +03:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_ior_imm(nir_builder *build, nir_ssa_def *x, uint64_t y)
|
|
|
|
|
{
|
|
|
|
|
assert(x->bit_size <= 64);
|
|
|
|
|
y &= BITFIELD64_MASK(x->bit_size);
|
|
|
|
|
|
|
|
|
|
if (y == 0) {
|
|
|
|
|
return x;
|
|
|
|
|
} else if (y == BITFIELD64_MASK(x->bit_size)) {
|
|
|
|
|
return nir_imm_intN_t(build, y, x->bit_size);
|
|
|
|
|
} else
|
|
|
|
|
return nir_ior(build, x, nir_imm_intN_t(build, y, x->bit_size));
|
|
|
|
|
}
|
|
|
|
|
|
2021-11-23 10:13:42 +02:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_ishl_imm(nir_builder *build, nir_ssa_def *x, uint32_t y)
|
|
|
|
|
{
|
|
|
|
|
if (y == 0) {
|
|
|
|
|
return x;
|
|
|
|
|
} else {
|
2023-03-05 23:12:36 +02:00
|
|
|
assert (y < x->bit_size);
|
2021-11-23 10:13:42 +02:00
|
|
|
return nir_ishl(build, x, nir_imm_int(build, y));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2020-08-21 11:21:33 -07:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_ishr_imm(nir_builder *build, nir_ssa_def *x, uint32_t y)
|
|
|
|
|
{
|
|
|
|
|
if (y == 0) {
|
|
|
|
|
return x;
|
|
|
|
|
} else {
|
|
|
|
|
return nir_ishr(build, x, nir_imm_int(build, y));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_ushr_imm(nir_builder *build, nir_ssa_def *x, uint32_t y)
|
|
|
|
|
{
|
|
|
|
|
if (y == 0) {
|
|
|
|
|
return x;
|
|
|
|
|
} else {
|
|
|
|
|
return nir_ushr(build, x, nir_imm_int(build, y));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2023-06-05 15:31:47 +02:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_imod_imm(nir_builder *build, nir_ssa_def *x, uint64_t y)
|
|
|
|
|
{
|
|
|
|
|
return nir_imod(build, x, nir_imm_intN_t(build, y, x->bit_size));
|
|
|
|
|
}
|
|
|
|
|
|
2020-08-21 11:21:33 -07:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_udiv_imm(nir_builder *build, nir_ssa_def *x, uint64_t y)
|
|
|
|
|
{
|
|
|
|
|
assert(x->bit_size <= 64);
|
|
|
|
|
y &= BITFIELD64_MASK(x->bit_size);
|
|
|
|
|
|
|
|
|
|
if (y == 1) {
|
|
|
|
|
return x;
|
|
|
|
|
} else if (util_is_power_of_two_nonzero(y)) {
|
|
|
|
|
return nir_ushr_imm(build, x, ffsll(y) - 1);
|
|
|
|
|
} else {
|
|
|
|
|
return nir_udiv(build, x, nir_imm_intN_t(build, y, x->bit_size));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2023-03-17 22:57:06 -04:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_umod_imm(nir_builder *build, nir_ssa_def *x, uint64_t y)
|
|
|
|
|
{
|
|
|
|
|
assert(y > 0 && y <= u_uintN_max(x->bit_size));
|
|
|
|
|
|
|
|
|
|
if (util_is_power_of_two_nonzero(y)) {
|
|
|
|
|
return nir_iand_imm(build, x, y - 1);
|
|
|
|
|
} else {
|
|
|
|
|
return nir_umod(build, x, nir_imm_intN_t(build, y, x->bit_size));
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2022-03-29 20:16:54 +01:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_ibfe_imm(nir_builder *build, nir_ssa_def *x, uint32_t offset, uint32_t size)
|
|
|
|
|
{
|
|
|
|
|
return nir_ibfe(build, x, nir_imm_int(build, offset), nir_imm_int(build, size));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_ubfe_imm(nir_builder *build, nir_ssa_def *x, uint32_t offset, uint32_t size)
|
|
|
|
|
{
|
|
|
|
|
return nir_ubfe(build, x, nir_imm_int(build, offset), nir_imm_int(build, size));
|
|
|
|
|
}
|
|
|
|
|
|
2023-05-20 23:01:45 -04:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_ubitfield_extract_imm(nir_builder *build, nir_ssa_def *x, uint32_t offset, uint32_t size)
|
|
|
|
|
{
|
|
|
|
|
return nir_ubitfield_extract(build, x, nir_imm_int(build, offset), nir_imm_int(build, size));
|
|
|
|
|
}
|
|
|
|
|
|
2018-11-12 18:38:24 -06:00
|
|
|
static inline nir_ssa_def *
|
2021-05-04 13:59:54 -05:00
|
|
|
nir_fclamp(nir_builder *b,
|
|
|
|
|
nir_ssa_def *x, nir_ssa_def *min_val, nir_ssa_def *max_val)
|
|
|
|
|
{
|
|
|
|
|
return nir_fmin(b, nir_fmax(b, x, min_val), max_val);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_iclamp(nir_builder *b,
|
|
|
|
|
nir_ssa_def *x, nir_ssa_def *min_val, nir_ssa_def *max_val)
|
|
|
|
|
{
|
|
|
|
|
return nir_imin(b, nir_imax(b, x, min_val), max_val);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_uclamp(nir_builder *b,
|
|
|
|
|
nir_ssa_def *x, nir_ssa_def *min_val, nir_ssa_def *max_val)
|
|
|
|
|
{
|
|
|
|
|
return nir_umin(b, nir_umax(b, x, min_val), max_val);
|
|
|
|
|
}
|
|
|
|
|
|
2021-06-02 15:14:41 +01:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_ffma_imm12(nir_builder *build, nir_ssa_def *src0, double src1, double src2)
|
|
|
|
|
{
|
|
|
|
|
if (build->shader->options->avoid_ternary_with_two_constants)
|
|
|
|
|
return nir_fadd_imm(build, nir_fmul_imm(build, src0, src1), src2);
|
|
|
|
|
else
|
|
|
|
|
return nir_ffma(build, src0, nir_imm_floatN_t(build, src1, src0->bit_size),
|
|
|
|
|
nir_imm_floatN_t(build, src2, src0->bit_size));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_ffma_imm1(nir_builder *build, nir_ssa_def *src0, double src1, nir_ssa_def *src2)
|
|
|
|
|
{
|
|
|
|
|
return nir_ffma(build, src0, nir_imm_floatN_t(build, src1, src0->bit_size), src2);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_ffma_imm2(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1, double src2)
|
|
|
|
|
{
|
|
|
|
|
return nir_ffma(build, src0, src1, nir_imm_floatN_t(build, src2, src0->bit_size));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_a_minus_bc(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1,
|
|
|
|
|
nir_ssa_def *src2)
|
|
|
|
|
{
|
|
|
|
|
return nir_ffma(build, nir_fneg(build, src1), src2, src0);
|
|
|
|
|
}
|
|
|
|
|
|
2021-05-04 13:59:54 -05:00
|
|
|
static inline nir_ssa_def *
|
2018-11-12 18:38:24 -06:00
|
|
|
nir_pack_bits(nir_builder *b, nir_ssa_def *src, unsigned dest_bit_size)
|
|
|
|
|
{
|
|
|
|
|
assert(src->num_components * src->bit_size == dest_bit_size);
|
|
|
|
|
|
|
|
|
|
switch (dest_bit_size) {
|
|
|
|
|
case 64:
|
|
|
|
|
switch (src->bit_size) {
|
|
|
|
|
case 32: return nir_pack_64_2x32(b, src);
|
|
|
|
|
case 16: return nir_pack_64_4x16(b, src);
|
|
|
|
|
default: break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 32:
|
|
|
|
|
if (src->bit_size == 16)
|
|
|
|
|
return nir_pack_32_2x16(b, src);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* If we got here, we have no dedicated unpack opcode. */
|
|
|
|
|
nir_ssa_def *dest = nir_imm_intN_t(b, 0, dest_bit_size);
|
|
|
|
|
for (unsigned i = 0; i < src->num_components; i++) {
|
2022-11-29 12:54:21 -06:00
|
|
|
nir_ssa_def *val = nir_u2uN(b, nir_channel(b, src, i), dest_bit_size);
|
2018-11-12 18:38:24 -06:00
|
|
|
val = nir_ishl(b, val, nir_imm_int(b, i * src->bit_size));
|
|
|
|
|
dest = nir_ior(b, dest, val);
|
|
|
|
|
}
|
|
|
|
|
return dest;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_unpack_bits(nir_builder *b, nir_ssa_def *src, unsigned dest_bit_size)
|
|
|
|
|
{
|
|
|
|
|
assert(src->num_components == 1);
|
|
|
|
|
assert(src->bit_size > dest_bit_size);
|
|
|
|
|
const unsigned dest_num_components = src->bit_size / dest_bit_size;
|
|
|
|
|
assert(dest_num_components <= NIR_MAX_VEC_COMPONENTS);
|
|
|
|
|
|
|
|
|
|
switch (src->bit_size) {
|
|
|
|
|
case 64:
|
|
|
|
|
switch (dest_bit_size) {
|
|
|
|
|
case 32: return nir_unpack_64_2x32(b, src);
|
|
|
|
|
case 16: return nir_unpack_64_4x16(b, src);
|
|
|
|
|
default: break;
|
|
|
|
|
}
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case 32:
|
|
|
|
|
if (dest_bit_size == 16)
|
|
|
|
|
return nir_unpack_32_2x16(b, src);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* If we got here, we have no dedicated unpack opcode. */
|
|
|
|
|
nir_ssa_def *dest_comps[NIR_MAX_VEC_COMPONENTS];
|
|
|
|
|
for (unsigned i = 0; i < dest_num_components; i++) {
|
2020-08-21 11:21:33 -07:00
|
|
|
nir_ssa_def *val = nir_ushr_imm(b, src, i * dest_bit_size);
|
2022-11-29 12:54:21 -06:00
|
|
|
dest_comps[i] = nir_u2uN(b, val, dest_bit_size);
|
2018-11-12 18:38:24 -06:00
|
|
|
}
|
|
|
|
|
return nir_vec(b, dest_comps, dest_num_components);
|
|
|
|
|
}
|
|
|
|
|
|
2019-11-06 12:09:56 -06:00
|
|
|
/**
|
|
|
|
|
* Treats srcs as if it's one big blob of bits and extracts the range of bits
|
|
|
|
|
* given by
|
|
|
|
|
*
|
|
|
|
|
* [first_bit, first_bit + dest_num_components * dest_bit_size)
|
|
|
|
|
*
|
|
|
|
|
* The range can have any alignment or size as long as it's an integer number
|
|
|
|
|
* of destination components and fits inside the concatenated sources.
|
|
|
|
|
*
|
|
|
|
|
* TODO: The one caveat here is that we can't handle byte alignment if 64-bit
|
|
|
|
|
* values are involved because that would require pack/unpack to/from a vec8
|
|
|
|
|
* which NIR currently does not support.
|
|
|
|
|
*/
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_extract_bits(nir_builder *b, nir_ssa_def **srcs, unsigned num_srcs,
|
|
|
|
|
unsigned first_bit,
|
|
|
|
|
unsigned dest_num_components, unsigned dest_bit_size)
|
|
|
|
|
{
|
|
|
|
|
const unsigned num_bits = dest_num_components * dest_bit_size;
|
|
|
|
|
|
|
|
|
|
/* Figure out the common bit size */
|
|
|
|
|
unsigned common_bit_size = dest_bit_size;
|
|
|
|
|
for (unsigned i = 0; i < num_srcs; i++)
|
|
|
|
|
common_bit_size = MIN2(common_bit_size, srcs[i]->bit_size);
|
|
|
|
|
if (first_bit > 0)
|
2019-11-11 16:43:45 -07:00
|
|
|
common_bit_size = MIN2(common_bit_size, (1u << (ffs(first_bit) - 1)));
|
2019-11-06 12:09:56 -06:00
|
|
|
|
|
|
|
|
/* We don't want to have to deal with 1-bit values */
|
|
|
|
|
assert(common_bit_size >= 8);
|
|
|
|
|
|
|
|
|
|
nir_ssa_def *common_comps[NIR_MAX_VEC_COMPONENTS * sizeof(uint64_t)];
|
|
|
|
|
assert(num_bits / common_bit_size <= ARRAY_SIZE(common_comps));
|
|
|
|
|
|
|
|
|
|
/* First, unpack to the common bit size and select the components from the
|
|
|
|
|
* source.
|
|
|
|
|
*/
|
|
|
|
|
int src_idx = -1;
|
|
|
|
|
unsigned src_start_bit = 0;
|
|
|
|
|
unsigned src_end_bit = 0;
|
|
|
|
|
for (unsigned i = 0; i < num_bits / common_bit_size; i++) {
|
|
|
|
|
const unsigned bit = first_bit + (i * common_bit_size);
|
|
|
|
|
while (bit >= src_end_bit) {
|
|
|
|
|
src_idx++;
|
2019-11-11 16:43:45 -07:00
|
|
|
assert(src_idx < (int) num_srcs);
|
2019-11-06 12:09:56 -06:00
|
|
|
src_start_bit = src_end_bit;
|
|
|
|
|
src_end_bit += srcs[src_idx]->bit_size *
|
|
|
|
|
srcs[src_idx]->num_components;
|
|
|
|
|
}
|
|
|
|
|
assert(bit >= src_start_bit);
|
|
|
|
|
assert(bit + common_bit_size <= src_end_bit);
|
|
|
|
|
const unsigned rel_bit = bit - src_start_bit;
|
|
|
|
|
const unsigned src_bit_size = srcs[src_idx]->bit_size;
|
|
|
|
|
|
|
|
|
|
nir_ssa_def *comp = nir_channel(b, srcs[src_idx],
|
|
|
|
|
rel_bit / src_bit_size);
|
|
|
|
|
if (srcs[src_idx]->bit_size > common_bit_size) {
|
|
|
|
|
nir_ssa_def *unpacked = nir_unpack_bits(b, comp, common_bit_size);
|
|
|
|
|
comp = nir_channel(b, unpacked, (rel_bit % src_bit_size) /
|
|
|
|
|
common_bit_size);
|
|
|
|
|
}
|
|
|
|
|
common_comps[i] = comp;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Now, re-pack the destination if we have to */
|
|
|
|
|
if (dest_bit_size > common_bit_size) {
|
|
|
|
|
unsigned common_per_dest = dest_bit_size / common_bit_size;
|
|
|
|
|
nir_ssa_def *dest_comps[NIR_MAX_VEC_COMPONENTS];
|
|
|
|
|
for (unsigned i = 0; i < dest_num_components; i++) {
|
|
|
|
|
nir_ssa_def *unpacked = nir_vec(b, common_comps + i * common_per_dest,
|
|
|
|
|
common_per_dest);
|
|
|
|
|
dest_comps[i] = nir_pack_bits(b, unpacked, dest_bit_size);
|
|
|
|
|
}
|
|
|
|
|
return nir_vec(b, dest_comps, dest_num_components);
|
|
|
|
|
} else {
|
|
|
|
|
assert(dest_bit_size == common_bit_size);
|
|
|
|
|
return nir_vec(b, common_comps, dest_num_components);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2018-11-12 18:38:24 -06:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_bitcast_vector(nir_builder *b, nir_ssa_def *src, unsigned dest_bit_size)
|
|
|
|
|
{
|
|
|
|
|
assert((src->bit_size * src->num_components) % dest_bit_size == 0);
|
|
|
|
|
const unsigned dest_num_components =
|
|
|
|
|
(src->bit_size * src->num_components) / dest_bit_size;
|
|
|
|
|
assert(dest_num_components <= NIR_MAX_VEC_COMPONENTS);
|
|
|
|
|
|
2019-11-06 12:09:56 -06:00
|
|
|
return nir_extract_bits(b, &src, 1, 0, dest_num_components, dest_bit_size);
|
2018-11-12 18:38:24 -06:00
|
|
|
}
|
|
|
|
|
|
2022-05-09 12:15:44 -05:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_trim_vector(nir_builder *b, nir_ssa_def *src, unsigned num_components)
|
|
|
|
|
{
|
|
|
|
|
assert(src->num_components >= num_components);
|
|
|
|
|
if (src->num_components == num_components)
|
|
|
|
|
return src;
|
|
|
|
|
|
|
|
|
|
return nir_channels(b, src, nir_component_mask(num_components));
|
|
|
|
|
}
|
|
|
|
|
|
2021-05-04 14:26:46 -04:00
|
|
|
/**
|
|
|
|
|
* Pad a value to N components with undefs of matching bit size.
|
|
|
|
|
* If the value already contains >= num_components, it is returned without change.
|
|
|
|
|
*/
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_pad_vector(nir_builder *b, nir_ssa_def *src, unsigned num_components)
|
|
|
|
|
{
|
|
|
|
|
assert(src->num_components <= num_components);
|
|
|
|
|
if (src->num_components == num_components)
|
|
|
|
|
return src;
|
|
|
|
|
|
2022-02-03 12:23:34 -08:00
|
|
|
nir_ssa_scalar components[NIR_MAX_VEC_COMPONENTS];
|
|
|
|
|
nir_ssa_scalar undef = nir_get_ssa_scalar(nir_ssa_undef(b, 1, src->bit_size), 0);
|
2021-05-04 14:26:46 -04:00
|
|
|
unsigned i = 0;
|
|
|
|
|
for (; i < src->num_components; i++)
|
2022-02-03 12:23:34 -08:00
|
|
|
components[i] = nir_get_ssa_scalar(src, i);
|
2021-05-04 14:26:46 -04:00
|
|
|
for (; i < num_components; i++)
|
|
|
|
|
components[i] = undef;
|
|
|
|
|
|
2022-02-03 12:23:34 -08:00
|
|
|
return nir_vec_scalars(b, components, num_components);
|
2021-05-04 14:26:46 -04:00
|
|
|
}
|
|
|
|
|
|
2020-09-10 18:48:04 +02:00
|
|
|
/**
|
|
|
|
|
* Pad a value to N components with copies of the given immediate of matching
|
|
|
|
|
* bit size. If the value already contains >= num_components, it is returned
|
|
|
|
|
* without change.
|
|
|
|
|
*/
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_pad_vector_imm_int(nir_builder *b, nir_ssa_def *src, uint64_t imm_val,
|
|
|
|
|
unsigned num_components)
|
|
|
|
|
{
|
|
|
|
|
assert(src->num_components <= num_components);
|
|
|
|
|
if (src->num_components == num_components)
|
|
|
|
|
return src;
|
|
|
|
|
|
2022-02-03 12:23:34 -08:00
|
|
|
nir_ssa_scalar components[NIR_MAX_VEC_COMPONENTS];
|
|
|
|
|
nir_ssa_scalar imm = nir_get_ssa_scalar(nir_imm_intN_t(b, imm_val, src->bit_size), 0);
|
2020-09-10 18:48:04 +02:00
|
|
|
unsigned i = 0;
|
|
|
|
|
for (; i < src->num_components; i++)
|
2022-02-03 12:23:34 -08:00
|
|
|
components[i] = nir_get_ssa_scalar(src, i);
|
2020-09-10 18:48:04 +02:00
|
|
|
for (; i < num_components; i++)
|
|
|
|
|
components[i] = imm;
|
|
|
|
|
|
2022-02-03 12:23:34 -08:00
|
|
|
return nir_vec_scalars(b, components, num_components);
|
2020-09-10 18:48:04 +02:00
|
|
|
}
|
|
|
|
|
|
2021-05-04 14:26:46 -04:00
|
|
|
/**
|
|
|
|
|
* Pad a value to 4 components with undefs of matching bit size.
|
|
|
|
|
* If the value already contains >= 4 components, it is returned without change.
|
|
|
|
|
*/
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_pad_vec4(nir_builder *b, nir_ssa_def *src)
|
|
|
|
|
{
|
|
|
|
|
return nir_pad_vector(b, src, 4);
|
|
|
|
|
}
|
|
|
|
|
|
2022-05-09 15:16:16 -05:00
|
|
|
/**
|
|
|
|
|
* Resizes a vector by either trimming off components or adding undef
|
|
|
|
|
* components, as needed. Only use this helper if it's actually what you
|
|
|
|
|
* need. Prefer nir_pad_vector() or nir_trim_vector() instead if you know a
|
|
|
|
|
* priori which direction you're resizing.
|
|
|
|
|
*/
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_resize_vector(nir_builder *b, nir_ssa_def *src, unsigned num_components)
|
|
|
|
|
{
|
|
|
|
|
if (src->num_components < num_components)
|
|
|
|
|
return nir_pad_vector(b, src, num_components);
|
|
|
|
|
else
|
|
|
|
|
return nir_trim_vector(b, src, num_components);
|
|
|
|
|
}
|
|
|
|
|
|
2021-11-19 16:50:03 -08:00
|
|
|
nir_ssa_def *
|
|
|
|
|
nir_ssa_for_src(nir_builder *build, nir_src src, int num_components);
|
2019-07-25 13:37:28 -07:00
|
|
|
|
2021-11-19 16:50:03 -08:00
|
|
|
nir_ssa_def *
|
|
|
|
|
nir_ssa_for_alu_src(nir_builder *build, nir_alu_instr *instr, unsigned srcn);
|
2015-03-27 14:19:46 -07:00
|
|
|
|
2019-01-31 01:56:25 +01:00
|
|
|
static inline unsigned
|
2020-08-14 21:19:07 -05:00
|
|
|
nir_get_ptr_bitsize(nir_shader *shader)
|
2019-01-31 01:56:25 +01:00
|
|
|
{
|
2020-08-14 21:19:07 -05:00
|
|
|
if (shader->info.stage == MESA_SHADER_KERNEL)
|
|
|
|
|
return shader->info.cs.ptr_size;
|
2019-01-31 01:56:25 +01:00
|
|
|
return 32;
|
|
|
|
|
}
|
|
|
|
|
|
2018-03-15 07:57:58 -07:00
|
|
|
static inline nir_deref_instr *
|
|
|
|
|
nir_build_deref_var(nir_builder *build, nir_variable *var)
|
|
|
|
|
{
|
|
|
|
|
nir_deref_instr *deref =
|
|
|
|
|
nir_deref_instr_create(build->shader, nir_deref_type_var);
|
|
|
|
|
|
2020-10-30 12:14:05 -05:00
|
|
|
deref->modes = (nir_variable_mode)var->data.mode;
|
2018-03-15 07:57:58 -07:00
|
|
|
deref->type = var->type;
|
|
|
|
|
deref->var = var;
|
|
|
|
|
|
2019-01-31 01:56:25 +01:00
|
|
|
nir_ssa_dest_init(&deref->instr, &deref->dest, 1,
|
nir: Drop unused name from nir_ssa_dest_init
Since 624e799cc34 ("nir: Drop nir_ssa_def::name and nir_register::name"), SSA
defs don't have names, making the name argument unused. Drop it from the
signature and fix the call sites. This was done with the help of the following
Coccinelle semantic patch:
@@
expression A, B, C, D, E;
@@
-nir_ssa_dest_init(A, B, C, D, E);
+nir_ssa_dest_init(A, B, C, D);
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23078>
2023-05-17 09:08:22 -04:00
|
|
|
nir_get_ptr_bitsize(build->shader));
|
2018-03-15 07:57:58 -07:00
|
|
|
|
|
|
|
|
nir_builder_instr_insert(build, &deref->instr);
|
|
|
|
|
|
|
|
|
|
return deref;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_deref_instr *
|
|
|
|
|
nir_build_deref_array(nir_builder *build, nir_deref_instr *parent,
|
|
|
|
|
nir_ssa_def *index)
|
|
|
|
|
{
|
|
|
|
|
assert(glsl_type_is_array(parent->type) ||
|
|
|
|
|
glsl_type_is_matrix(parent->type) ||
|
|
|
|
|
glsl_type_is_vector(parent->type));
|
|
|
|
|
|
2019-03-05 16:06:31 -06:00
|
|
|
assert(index->bit_size == parent->dest.ssa.bit_size);
|
|
|
|
|
|
2018-03-15 07:57:58 -07:00
|
|
|
nir_deref_instr *deref =
|
|
|
|
|
nir_deref_instr_create(build->shader, nir_deref_type_array);
|
|
|
|
|
|
2020-10-30 12:14:05 -05:00
|
|
|
deref->modes = parent->modes;
|
2018-03-15 07:57:58 -07:00
|
|
|
deref->type = glsl_get_array_element(parent->type);
|
|
|
|
|
deref->parent = nir_src_for_ssa(&parent->dest.ssa);
|
|
|
|
|
deref->arr.index = nir_src_for_ssa(index);
|
|
|
|
|
|
|
|
|
|
nir_ssa_dest_init(&deref->instr, &deref->dest,
|
|
|
|
|
parent->dest.ssa.num_components,
|
nir: Drop unused name from nir_ssa_dest_init
Since 624e799cc34 ("nir: Drop nir_ssa_def::name and nir_register::name"), SSA
defs don't have names, making the name argument unused. Drop it from the
signature and fix the call sites. This was done with the help of the following
Coccinelle semantic patch:
@@
expression A, B, C, D, E;
@@
-nir_ssa_dest_init(A, B, C, D, E);
+nir_ssa_dest_init(A, B, C, D);
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23078>
2023-05-17 09:08:22 -04:00
|
|
|
parent->dest.ssa.bit_size);
|
2018-03-15 07:57:58 -07:00
|
|
|
|
|
|
|
|
nir_builder_instr_insert(build, &deref->instr);
|
|
|
|
|
|
|
|
|
|
return deref;
|
|
|
|
|
}
|
|
|
|
|
|
2019-03-07 11:45:13 -06:00
|
|
|
static inline nir_deref_instr *
|
|
|
|
|
nir_build_deref_array_imm(nir_builder *build, nir_deref_instr *parent,
|
|
|
|
|
int64_t index)
|
|
|
|
|
{
|
|
|
|
|
assert(parent->dest.is_ssa);
|
|
|
|
|
nir_ssa_def *idx_ssa = nir_imm_intN_t(build, index,
|
|
|
|
|
parent->dest.ssa.bit_size);
|
|
|
|
|
|
|
|
|
|
return nir_build_deref_array(build, parent, idx_ssa);
|
|
|
|
|
}
|
|
|
|
|
|
2018-11-28 12:26:52 -06:00
|
|
|
static inline nir_deref_instr *
|
|
|
|
|
nir_build_deref_ptr_as_array(nir_builder *build, nir_deref_instr *parent,
|
|
|
|
|
nir_ssa_def *index)
|
|
|
|
|
{
|
|
|
|
|
assert(parent->deref_type == nir_deref_type_array ||
|
|
|
|
|
parent->deref_type == nir_deref_type_ptr_as_array ||
|
|
|
|
|
parent->deref_type == nir_deref_type_cast);
|
|
|
|
|
|
2019-03-05 16:06:31 -06:00
|
|
|
assert(index->bit_size == parent->dest.ssa.bit_size);
|
|
|
|
|
|
2018-11-28 12:26:52 -06:00
|
|
|
nir_deref_instr *deref =
|
|
|
|
|
nir_deref_instr_create(build->shader, nir_deref_type_ptr_as_array);
|
|
|
|
|
|
2020-10-30 12:14:05 -05:00
|
|
|
deref->modes = parent->modes;
|
2018-11-28 12:26:52 -06:00
|
|
|
deref->type = parent->type;
|
|
|
|
|
deref->parent = nir_src_for_ssa(&parent->dest.ssa);
|
|
|
|
|
deref->arr.index = nir_src_for_ssa(index);
|
|
|
|
|
|
|
|
|
|
nir_ssa_dest_init(&deref->instr, &deref->dest,
|
|
|
|
|
parent->dest.ssa.num_components,
|
nir: Drop unused name from nir_ssa_dest_init
Since 624e799cc34 ("nir: Drop nir_ssa_def::name and nir_register::name"), SSA
defs don't have names, making the name argument unused. Drop it from the
signature and fix the call sites. This was done with the help of the following
Coccinelle semantic patch:
@@
expression A, B, C, D, E;
@@
-nir_ssa_dest_init(A, B, C, D, E);
+nir_ssa_dest_init(A, B, C, D);
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23078>
2023-05-17 09:08:22 -04:00
|
|
|
parent->dest.ssa.bit_size);
|
2018-11-28 12:26:52 -06:00
|
|
|
|
|
|
|
|
nir_builder_instr_insert(build, &deref->instr);
|
|
|
|
|
|
|
|
|
|
return deref;
|
|
|
|
|
}
|
|
|
|
|
|
2018-03-15 07:57:58 -07:00
|
|
|
static inline nir_deref_instr *
|
|
|
|
|
nir_build_deref_array_wildcard(nir_builder *build, nir_deref_instr *parent)
|
|
|
|
|
{
|
|
|
|
|
assert(glsl_type_is_array(parent->type) ||
|
|
|
|
|
glsl_type_is_matrix(parent->type));
|
|
|
|
|
|
|
|
|
|
nir_deref_instr *deref =
|
|
|
|
|
nir_deref_instr_create(build->shader, nir_deref_type_array_wildcard);
|
|
|
|
|
|
2020-10-30 12:14:05 -05:00
|
|
|
deref->modes = parent->modes;
|
2018-03-15 07:57:58 -07:00
|
|
|
deref->type = glsl_get_array_element(parent->type);
|
|
|
|
|
deref->parent = nir_src_for_ssa(&parent->dest.ssa);
|
|
|
|
|
|
|
|
|
|
nir_ssa_dest_init(&deref->instr, &deref->dest,
|
|
|
|
|
parent->dest.ssa.num_components,
|
nir: Drop unused name from nir_ssa_dest_init
Since 624e799cc34 ("nir: Drop nir_ssa_def::name and nir_register::name"), SSA
defs don't have names, making the name argument unused. Drop it from the
signature and fix the call sites. This was done with the help of the following
Coccinelle semantic patch:
@@
expression A, B, C, D, E;
@@
-nir_ssa_dest_init(A, B, C, D, E);
+nir_ssa_dest_init(A, B, C, D);
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23078>
2023-05-17 09:08:22 -04:00
|
|
|
parent->dest.ssa.bit_size);
|
2018-03-15 07:57:58 -07:00
|
|
|
|
|
|
|
|
nir_builder_instr_insert(build, &deref->instr);
|
|
|
|
|
|
|
|
|
|
return deref;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_deref_instr *
|
|
|
|
|
nir_build_deref_struct(nir_builder *build, nir_deref_instr *parent,
|
|
|
|
|
unsigned index)
|
|
|
|
|
{
|
2019-03-05 16:07:12 +11:00
|
|
|
assert(glsl_type_is_struct_or_ifc(parent->type));
|
2018-03-15 07:57:58 -07:00
|
|
|
|
|
|
|
|
nir_deref_instr *deref =
|
|
|
|
|
nir_deref_instr_create(build->shader, nir_deref_type_struct);
|
|
|
|
|
|
2020-10-30 12:14:05 -05:00
|
|
|
deref->modes = parent->modes;
|
2018-03-15 07:57:58 -07:00
|
|
|
deref->type = glsl_get_struct_field(parent->type, index);
|
|
|
|
|
deref->parent = nir_src_for_ssa(&parent->dest.ssa);
|
|
|
|
|
deref->strct.index = index;
|
|
|
|
|
|
|
|
|
|
nir_ssa_dest_init(&deref->instr, &deref->dest,
|
|
|
|
|
parent->dest.ssa.num_components,
|
nir: Drop unused name from nir_ssa_dest_init
Since 624e799cc34 ("nir: Drop nir_ssa_def::name and nir_register::name"), SSA
defs don't have names, making the name argument unused. Drop it from the
signature and fix the call sites. This was done with the help of the following
Coccinelle semantic patch:
@@
expression A, B, C, D, E;
@@
-nir_ssa_dest_init(A, B, C, D, E);
+nir_ssa_dest_init(A, B, C, D);
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23078>
2023-05-17 09:08:22 -04:00
|
|
|
parent->dest.ssa.bit_size);
|
2018-03-15 07:57:58 -07:00
|
|
|
|
|
|
|
|
nir_builder_instr_insert(build, &deref->instr);
|
|
|
|
|
|
|
|
|
|
return deref;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_deref_instr *
|
|
|
|
|
nir_build_deref_cast(nir_builder *build, nir_ssa_def *parent,
|
2020-10-30 12:14:05 -05:00
|
|
|
nir_variable_mode modes, const struct glsl_type *type,
|
2018-11-28 12:26:52 -06:00
|
|
|
unsigned ptr_stride)
|
2018-03-15 07:57:58 -07:00
|
|
|
{
|
|
|
|
|
nir_deref_instr *deref =
|
|
|
|
|
nir_deref_instr_create(build->shader, nir_deref_type_cast);
|
|
|
|
|
|
2020-10-30 12:14:05 -05:00
|
|
|
deref->modes = modes;
|
2018-03-15 07:57:58 -07:00
|
|
|
deref->type = type;
|
|
|
|
|
deref->parent = nir_src_for_ssa(parent);
|
2018-11-28 12:26:52 -06:00
|
|
|
deref->cast.ptr_stride = ptr_stride;
|
2018-03-15 07:57:58 -07:00
|
|
|
|
nir: Drop unused name from nir_ssa_dest_init
Since 624e799cc34 ("nir: Drop nir_ssa_def::name and nir_register::name"), SSA
defs don't have names, making the name argument unused. Drop it from the
signature and fix the call sites. This was done with the help of the following
Coccinelle semantic patch:
@@
expression A, B, C, D, E;
@@
-nir_ssa_dest_init(A, B, C, D, E);
+nir_ssa_dest_init(A, B, C, D);
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23078>
2023-05-17 09:08:22 -04:00
|
|
|
nir_ssa_dest_init(&deref->instr, &deref->dest, parent->num_components,
|
|
|
|
|
parent->bit_size);
|
2018-03-15 07:57:58 -07:00
|
|
|
|
|
|
|
|
nir_builder_instr_insert(build, &deref->instr);
|
|
|
|
|
|
|
|
|
|
return deref;
|
|
|
|
|
}
|
|
|
|
|
|
2020-08-27 18:34:50 -05:00
|
|
|
static inline nir_deref_instr *
|
|
|
|
|
nir_alignment_deref_cast(nir_builder *build, nir_deref_instr *parent,
|
|
|
|
|
uint32_t align_mul, uint32_t align_offset)
|
|
|
|
|
{
|
|
|
|
|
nir_deref_instr *deref =
|
|
|
|
|
nir_deref_instr_create(build->shader, nir_deref_type_cast);
|
|
|
|
|
|
2020-10-30 12:14:05 -05:00
|
|
|
deref->modes = parent->modes;
|
2020-08-27 18:34:50 -05:00
|
|
|
deref->type = parent->type;
|
|
|
|
|
deref->parent = nir_src_for_ssa(&parent->dest.ssa);
|
|
|
|
|
deref->cast.ptr_stride = nir_deref_instr_array_stride(deref);
|
|
|
|
|
deref->cast.align_mul = align_mul;
|
|
|
|
|
deref->cast.align_offset = align_offset;
|
|
|
|
|
|
|
|
|
|
nir_ssa_dest_init(&deref->instr, &deref->dest,
|
|
|
|
|
parent->dest.ssa.num_components,
|
nir: Drop unused name from nir_ssa_dest_init
Since 624e799cc34 ("nir: Drop nir_ssa_def::name and nir_register::name"), SSA
defs don't have names, making the name argument unused. Drop it from the
signature and fix the call sites. This was done with the help of the following
Coccinelle semantic patch:
@@
expression A, B, C, D, E;
@@
-nir_ssa_dest_init(A, B, C, D, E);
+nir_ssa_dest_init(A, B, C, D);
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23078>
2023-05-17 09:08:22 -04:00
|
|
|
parent->dest.ssa.bit_size);
|
2020-08-27 18:34:50 -05:00
|
|
|
|
|
|
|
|
nir_builder_instr_insert(build, &deref->instr);
|
|
|
|
|
|
|
|
|
|
return deref;
|
|
|
|
|
}
|
|
|
|
|
|
2018-03-16 00:20:57 -07:00
|
|
|
/** Returns a deref that follows another but starting from the given parent
|
|
|
|
|
*
|
|
|
|
|
* The new deref will be the same type and take the same array or struct index
|
|
|
|
|
* as the leader deref but it may have a different parent. This is very
|
|
|
|
|
* useful for walking deref paths.
|
|
|
|
|
*/
|
|
|
|
|
static inline nir_deref_instr *
|
|
|
|
|
nir_build_deref_follower(nir_builder *b, nir_deref_instr *parent,
|
|
|
|
|
nir_deref_instr *leader)
|
|
|
|
|
{
|
|
|
|
|
/* If the derefs would have the same parent, don't make a new one */
|
|
|
|
|
assert(leader->parent.is_ssa);
|
|
|
|
|
if (leader->parent.ssa == &parent->dest.ssa)
|
|
|
|
|
return leader;
|
|
|
|
|
|
|
|
|
|
UNUSED nir_deref_instr *leader_parent = nir_src_as_deref(leader->parent);
|
|
|
|
|
|
|
|
|
|
switch (leader->deref_type) {
|
|
|
|
|
case nir_deref_type_var:
|
|
|
|
|
unreachable("A var dereference cannot have a parent");
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case nir_deref_type_array:
|
|
|
|
|
case nir_deref_type_array_wildcard:
|
|
|
|
|
assert(glsl_type_is_matrix(parent->type) ||
|
2019-01-14 16:10:44 -08:00
|
|
|
glsl_type_is_array(parent->type) ||
|
|
|
|
|
(leader->deref_type == nir_deref_type_array &&
|
|
|
|
|
glsl_type_is_vector(parent->type)));
|
2018-03-16 00:20:57 -07:00
|
|
|
assert(glsl_get_length(parent->type) ==
|
|
|
|
|
glsl_get_length(leader_parent->type));
|
|
|
|
|
|
|
|
|
|
if (leader->deref_type == nir_deref_type_array) {
|
|
|
|
|
assert(leader->arr.index.is_ssa);
|
2022-11-29 12:54:21 -06:00
|
|
|
nir_ssa_def *index = nir_i2iN(b, leader->arr.index.ssa,
|
2019-03-05 16:06:31 -06:00
|
|
|
parent->dest.ssa.bit_size);
|
|
|
|
|
return nir_build_deref_array(b, parent, index);
|
2018-03-16 00:20:57 -07:00
|
|
|
} else {
|
|
|
|
|
return nir_build_deref_array_wildcard(b, parent);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
case nir_deref_type_struct:
|
2019-03-05 16:07:12 +11:00
|
|
|
assert(glsl_type_is_struct_or_ifc(parent->type));
|
2018-03-16 00:20:57 -07:00
|
|
|
assert(glsl_get_length(parent->type) ==
|
|
|
|
|
glsl_get_length(leader_parent->type));
|
|
|
|
|
|
|
|
|
|
return nir_build_deref_struct(b, parent, leader->strct.index);
|
|
|
|
|
|
|
|
|
|
default:
|
|
|
|
|
unreachable("Invalid deref instruction type");
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2018-03-19 13:43:35 -07:00
|
|
|
static inline nir_ssa_def *
|
2023-05-23 16:12:51 -04:00
|
|
|
nir_load_register(nir_builder *build, nir_register *reg)
|
2018-03-19 13:43:35 -07:00
|
|
|
{
|
|
|
|
|
return nir_ssa_for_src(build, nir_src_for_reg(reg), reg->num_components);
|
|
|
|
|
}
|
|
|
|
|
|
2020-05-18 18:40:58 -05:00
|
|
|
static inline void
|
2023-05-23 16:12:51 -04:00
|
|
|
nir_store_register(nir_builder *build, nir_register *reg,
|
|
|
|
|
nir_ssa_def *def, nir_component_mask_t write_mask)
|
2020-05-18 18:40:58 -05:00
|
|
|
{
|
|
|
|
|
assert(reg->num_components == def->num_components);
|
|
|
|
|
assert(reg->bit_size == def->bit_size);
|
|
|
|
|
|
|
|
|
|
nir_alu_instr *mov = nir_alu_instr_create(build->shader, nir_op_mov);
|
|
|
|
|
mov->src[0].src = nir_src_for_ssa(def);
|
|
|
|
|
mov->dest.dest = nir_dest_for_reg(reg);
|
|
|
|
|
mov->dest.write_mask = write_mask & BITFIELD_MASK(reg->num_components);
|
|
|
|
|
nir_builder_instr_insert(build, &mov->instr);
|
|
|
|
|
}
|
|
|
|
|
|
2018-03-15 14:56:43 -07:00
|
|
|
static inline nir_ssa_def *
|
2019-03-26 23:06:53 +01:00
|
|
|
nir_load_deref_with_access(nir_builder *build, nir_deref_instr *deref,
|
|
|
|
|
enum gl_access_qualifier access)
|
2018-03-15 14:56:43 -07:00
|
|
|
{
|
2020-09-07 13:55:38 +01:00
|
|
|
return nir_build_load_deref(build, glsl_get_vector_elements(deref->type),
|
|
|
|
|
glsl_get_bit_size(deref->type), &deref->dest.ssa,
|
|
|
|
|
access);
|
2018-03-15 14:56:43 -07:00
|
|
|
}
|
|
|
|
|
|
2020-09-07 13:55:38 +01:00
|
|
|
#undef nir_load_deref
|
2019-03-26 23:06:53 +01:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_load_deref(nir_builder *build, nir_deref_instr *deref)
|
|
|
|
|
{
|
|
|
|
|
return nir_load_deref_with_access(build, deref, (enum gl_access_qualifier)0);
|
|
|
|
|
}
|
|
|
|
|
|
2018-03-15 14:56:43 -07:00
|
|
|
static inline void
|
2019-03-26 23:06:53 +01:00
|
|
|
nir_store_deref_with_access(nir_builder *build, nir_deref_instr *deref,
|
|
|
|
|
nir_ssa_def *value, unsigned writemask,
|
|
|
|
|
enum gl_access_qualifier access)
|
2018-03-15 14:56:43 -07:00
|
|
|
{
|
2020-09-07 13:55:38 +01:00
|
|
|
writemask &= (1u << value->num_components) - 1u;
|
|
|
|
|
nir_build_store_deref(build, &deref->dest.ssa, value, writemask, access);
|
2018-03-15 14:56:43 -07:00
|
|
|
}
|
|
|
|
|
|
2020-09-07 13:55:38 +01:00
|
|
|
#undef nir_store_deref
|
2019-03-26 23:06:53 +01:00
|
|
|
static inline void
|
|
|
|
|
nir_store_deref(nir_builder *build, nir_deref_instr *deref,
|
|
|
|
|
nir_ssa_def *value, unsigned writemask)
|
|
|
|
|
{
|
|
|
|
|
nir_store_deref_with_access(build, deref, value, writemask,
|
|
|
|
|
(enum gl_access_qualifier)0);
|
|
|
|
|
}
|
|
|
|
|
|
2018-03-15 14:56:43 -07:00
|
|
|
static inline void
|
2019-06-04 11:40:14 +02:00
|
|
|
nir_copy_deref_with_access(nir_builder *build, nir_deref_instr *dest,
|
|
|
|
|
nir_deref_instr *src,
|
|
|
|
|
enum gl_access_qualifier dest_access,
|
|
|
|
|
enum gl_access_qualifier src_access)
|
2018-03-15 14:56:43 -07:00
|
|
|
{
|
2020-09-07 13:55:38 +01:00
|
|
|
nir_build_copy_deref(build, &dest->dest.ssa, &src->dest.ssa, dest_access, src_access);
|
2018-03-15 14:56:43 -07:00
|
|
|
}
|
|
|
|
|
|
2020-09-07 13:55:38 +01:00
|
|
|
#undef nir_copy_deref
|
2019-06-04 11:40:14 +02:00
|
|
|
static inline void
|
|
|
|
|
nir_copy_deref(nir_builder *build, nir_deref_instr *dest, nir_deref_instr *src)
|
|
|
|
|
{
|
|
|
|
|
nir_copy_deref_with_access(build, dest, src,
|
|
|
|
|
(enum gl_access_qualifier) 0,
|
|
|
|
|
(enum gl_access_qualifier) 0);
|
|
|
|
|
}
|
|
|
|
|
|
2020-09-14 15:21:47 -05:00
|
|
|
static inline void
|
|
|
|
|
nir_memcpy_deref_with_access(nir_builder *build, nir_deref_instr *dest,
|
|
|
|
|
nir_deref_instr *src, nir_ssa_def *size,
|
|
|
|
|
enum gl_access_qualifier dest_access,
|
|
|
|
|
enum gl_access_qualifier src_access)
|
|
|
|
|
{
|
2020-09-07 13:55:38 +01:00
|
|
|
nir_build_memcpy_deref(build, &dest->dest.ssa, &src->dest.ssa,
|
|
|
|
|
size, dest_access, src_access);
|
2020-09-14 15:21:47 -05:00
|
|
|
}
|
|
|
|
|
|
2020-09-07 13:55:38 +01:00
|
|
|
#undef nir_memcpy_deref
|
2020-09-14 15:21:47 -05:00
|
|
|
static inline void
|
|
|
|
|
nir_memcpy_deref(nir_builder *build, nir_deref_instr *dest,
|
|
|
|
|
nir_deref_instr *src, nir_ssa_def *size)
|
|
|
|
|
{
|
|
|
|
|
nir_memcpy_deref_with_access(build, dest, src, size,
|
|
|
|
|
(enum gl_access_qualifier)0,
|
|
|
|
|
(enum gl_access_qualifier)0);
|
|
|
|
|
}
|
|
|
|
|
|
2015-05-12 01:53:24 -07:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_load_var(nir_builder *build, nir_variable *var)
|
|
|
|
|
{
|
2018-03-26 14:35:05 -07:00
|
|
|
return nir_load_deref(build, nir_build_deref_var(build, var));
|
2015-05-12 01:53:24 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void
|
nir: Add a writemask to store intrinsics.
Tessellation control shaders need to be careful when writing outputs.
Because multiple threads can concurrently write the same output
variables, we need to only write the exact components we were told.
Traditionally, for sub-vector writes, we've read the whole vector,
updated the temporary, and written the whole vector back. This breaks
down with concurrent access.
This patch prepares the way for a solution by adding a writemask field
to store_var intrinsics, as well as the other store intrinsics. It then
updates all produces to emit a writemask of "all channels enabled". It
updates nir_lower_io to copy the writemask to output store intrinsics.
Finally, it updates nir_lower_vars_to_ssa to handle partial writemasks
by doing a read-modify-write cycle (which is safe, because local
variables are specific to a single thread).
This should have no functional change, since no one actually emits
partial writemasks yet.
v2: Make nir_validate momentarily assert that writemasks cover the
complete value - we shouldn't have partial writemasks yet
(requested by Jason Ekstrand).
v3: Fix accidental SSBO change that arose from merge conflicts.
v4: Don't try to handle writemasks in ir3_compiler_nir - my code
for indirects was likely wrong, and TTN doesn't generate partial
writemasks today anyway. Change them to asserts as requested by
Rob Clark.
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Jason Ekstrand <jason.ekstrand@intel.com> [v3]
2015-11-17 00:26:37 -08:00
|
|
|
nir_store_var(nir_builder *build, nir_variable *var, nir_ssa_def *value,
|
|
|
|
|
unsigned writemask)
|
2015-05-12 01:53:24 -07:00
|
|
|
{
|
2018-03-26 14:35:05 -07:00
|
|
|
nir_store_deref(build, nir_build_deref_var(build, var), value, writemask);
|
2015-05-12 01:53:24 -07:00
|
|
|
}
|
|
|
|
|
|
2015-12-26 10:48:14 -08:00
|
|
|
static inline void
|
|
|
|
|
nir_copy_var(nir_builder *build, nir_variable *dest, nir_variable *src)
|
|
|
|
|
{
|
2018-03-26 14:35:05 -07:00
|
|
|
nir_copy_deref(build, nir_build_deref_var(build, dest),
|
|
|
|
|
nir_build_deref_var(build, src));
|
2015-12-26 10:48:14 -08:00
|
|
|
}
|
|
|
|
|
|
2022-03-19 21:05:33 +08:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_load_array_var(nir_builder *build, nir_variable *var, nir_ssa_def *index)
|
|
|
|
|
{
|
|
|
|
|
nir_deref_instr *deref =
|
|
|
|
|
nir_build_deref_array(build, nir_build_deref_var(build, var), index);
|
|
|
|
|
return nir_load_deref(build, deref);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_load_array_var_imm(nir_builder *build, nir_variable *var, int64_t index)
|
|
|
|
|
{
|
|
|
|
|
nir_deref_instr *deref =
|
|
|
|
|
nir_build_deref_array_imm(build, nir_build_deref_var(build, var), index);
|
|
|
|
|
return nir_load_deref(build, deref);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void
|
|
|
|
|
nir_store_array_var(nir_builder *build, nir_variable *var, nir_ssa_def *index,
|
|
|
|
|
nir_ssa_def *value, unsigned writemask)
|
|
|
|
|
{
|
|
|
|
|
nir_deref_instr *deref =
|
|
|
|
|
nir_build_deref_array(build, nir_build_deref_var(build, var), index);
|
|
|
|
|
nir_store_deref(build, deref, value, writemask);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void
|
|
|
|
|
nir_store_array_var_imm(nir_builder *build, nir_variable *var, int64_t index,
|
|
|
|
|
nir_ssa_def *value, unsigned writemask)
|
|
|
|
|
{
|
|
|
|
|
nir_deref_instr *deref =
|
|
|
|
|
nir_build_deref_array_imm(build, nir_build_deref_var(build, var), index);
|
|
|
|
|
nir_store_deref(build, deref, value, writemask);
|
|
|
|
|
}
|
|
|
|
|
|
2020-09-07 13:55:38 +01:00
|
|
|
#undef nir_load_global
|
2020-05-19 13:53:41 -05:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_load_global(nir_builder *build, nir_ssa_def *addr, unsigned align,
|
|
|
|
|
unsigned num_components, unsigned bit_size)
|
|
|
|
|
{
|
2020-11-27 09:56:50 +00:00
|
|
|
nir_intrinsic_instr *load =
|
|
|
|
|
nir_intrinsic_instr_create(build->shader, nir_intrinsic_load_global);
|
|
|
|
|
load->num_components = num_components;
|
|
|
|
|
load->src[0] = nir_src_for_ssa(addr);
|
|
|
|
|
nir_intrinsic_set_align(load, align, 0);
|
nir: Drop unused name from nir_ssa_dest_init
Since 624e799cc34 ("nir: Drop nir_ssa_def::name and nir_register::name"), SSA
defs don't have names, making the name argument unused. Drop it from the
signature and fix the call sites. This was done with the help of the following
Coccinelle semantic patch:
@@
expression A, B, C, D, E;
@@
-nir_ssa_dest_init(A, B, C, D, E);
+nir_ssa_dest_init(A, B, C, D);
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23078>
2023-05-17 09:08:22 -04:00
|
|
|
nir_ssa_dest_init(&load->instr, &load->dest, num_components, bit_size);
|
2020-11-27 09:56:50 +00:00
|
|
|
nir_builder_instr_insert(build, &load->instr);
|
|
|
|
|
return &load->dest.ssa;
|
2020-05-19 13:53:41 -05:00
|
|
|
}
|
|
|
|
|
|
2020-09-07 13:55:38 +01:00
|
|
|
#undef nir_store_global
|
2020-05-19 13:53:41 -05:00
|
|
|
static inline void
|
|
|
|
|
nir_store_global(nir_builder *build, nir_ssa_def *addr, unsigned align,
|
|
|
|
|
nir_ssa_def *value, nir_component_mask_t write_mask)
|
|
|
|
|
{
|
2020-11-27 09:56:50 +00:00
|
|
|
nir_intrinsic_instr *store =
|
|
|
|
|
nir_intrinsic_instr_create(build->shader, nir_intrinsic_store_global);
|
|
|
|
|
store->num_components = value->num_components;
|
|
|
|
|
store->src[0] = nir_src_for_ssa(value);
|
|
|
|
|
store->src[1] = nir_src_for_ssa(addr);
|
|
|
|
|
nir_intrinsic_set_write_mask(store,
|
|
|
|
|
write_mask & BITFIELD_MASK(value->num_components));
|
|
|
|
|
nir_intrinsic_set_align(store, align, 0);
|
|
|
|
|
nir_builder_instr_insert(build, &store->instr);
|
2020-05-19 13:53:41 -05:00
|
|
|
}
|
|
|
|
|
|
2020-09-07 13:55:38 +01:00
|
|
|
#undef nir_load_global_constant
|
2018-03-22 16:41:18 -07:00
|
|
|
static inline nir_ssa_def *
|
2020-08-06 22:17:17 -05:00
|
|
|
nir_load_global_constant(nir_builder *build, nir_ssa_def *addr, unsigned align,
|
|
|
|
|
unsigned num_components, unsigned bit_size)
|
|
|
|
|
{
|
2020-11-27 09:56:50 +00:00
|
|
|
nir_intrinsic_instr *load =
|
|
|
|
|
nir_intrinsic_instr_create(build->shader, nir_intrinsic_load_global_constant);
|
|
|
|
|
load->num_components = num_components;
|
|
|
|
|
load->src[0] = nir_src_for_ssa(addr);
|
|
|
|
|
nir_intrinsic_set_align(load, align, 0);
|
nir: Drop unused name from nir_ssa_dest_init
Since 624e799cc34 ("nir: Drop nir_ssa_def::name and nir_register::name"), SSA
defs don't have names, making the name argument unused. Drop it from the
signature and fix the call sites. This was done with the help of the following
Coccinelle semantic patch:
@@
expression A, B, C, D, E;
@@
-nir_ssa_dest_init(A, B, C, D, E);
+nir_ssa_dest_init(A, B, C, D);
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23078>
2023-05-17 09:08:22 -04:00
|
|
|
nir_ssa_dest_init(&load->instr, &load->dest, num_components, bit_size);
|
2020-11-27 09:56:50 +00:00
|
|
|
nir_builder_instr_insert(build, &load->instr);
|
|
|
|
|
return &load->dest.ssa;
|
2020-08-06 22:17:17 -05:00
|
|
|
}
|
|
|
|
|
|
2020-09-07 13:55:38 +01:00
|
|
|
#undef nir_load_param
|
2020-08-06 22:17:17 -05:00
|
|
|
static inline nir_ssa_def *
|
2018-03-22 16:41:18 -07:00
|
|
|
nir_load_param(nir_builder *build, uint32_t param_idx)
|
|
|
|
|
{
|
|
|
|
|
assert(param_idx < build->impl->function->num_params);
|
|
|
|
|
nir_parameter *param = &build->impl->function->params[param_idx];
|
2020-09-07 13:55:38 +01:00
|
|
|
return nir_build_load_param(build, param->num_components, param->bit_size, param_idx);
|
2018-03-22 16:41:18 -07:00
|
|
|
}
|
|
|
|
|
|
nir: Add intrinsics for register access
Note the writemask handling is chosen for consistency with the rest of NIR. In
every other instance, writemask=w requires a vec4 source. This is hardcoded into
nir_validate and nir_print as what it means to have a writemask.
More importantly, consistency with how register writemasks currently work.
nir_print hides it, but r0.w = fneg ssa_1.x is actually a vec4 instruction with
source ssa_1.xxxx. As a silly example nir_dest_num_components(that) = 4 in the
old model. I realize this is quite strange coming from a scalar ISA, but it's
perfectly natural for the class of vec4 hardware for which this was designed. In
that hardware, conceptually all instructions are vec4`, so the sequence "fneg
ssa_1 and write to channel w" is implemented as "fneg a vec4 with ssa_1.x in the
last component and write that vec4 out but mask to write only the w channel".
Isn't this inefficient? It can be. To save power, Midgard has scalar ALUs in
addition to vec4 ALUs. Those details are confined to the backend VLIW scheduler;
the instruction selection is still done as vec4. This mechanism has little in
common with AMD's SALUs. Midgard has a wave size of 1, with special hacks for
derivatives.
As a result, all backends consuming register writemasks are expecting this
pattern of code. Changing the store to take a vec1 instead of a vec4 would
require changing every backend to reswizzle the sources to resurrect the vec4. I
started typing a branch to do this yesterday, but it made a mess of both Midgard
and nir-to-tgsi. Without any good reason to think it'd actually help
performance, I abandoned the idea. Getting all 15 backends converted to the
helpers is enough of a challenge without forcing 10 backends to reswizzle their
sources too.
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Faith Ekstrand <faith.ekstrand@collabora.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23089>
2023-05-16 11:19:49 -04:00
|
|
|
#undef nir_decl_reg
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_decl_reg(nir_builder *b, unsigned num_components, unsigned bit_size,
|
|
|
|
|
unsigned num_array_elems)
|
|
|
|
|
{
|
|
|
|
|
nir_intrinsic_instr *decl =
|
|
|
|
|
nir_intrinsic_instr_create(b->shader, nir_intrinsic_decl_reg);
|
|
|
|
|
nir_intrinsic_set_num_components(decl, num_components);
|
|
|
|
|
nir_intrinsic_set_bit_size(decl, bit_size);
|
|
|
|
|
nir_intrinsic_set_num_array_elems(decl, num_array_elems);
|
|
|
|
|
nir_ssa_dest_init(&decl->instr, &decl->dest, 1, 32);
|
|
|
|
|
|
|
|
|
|
nir_instr_insert(nir_before_cf_list(&b->impl->body), &decl->instr);
|
|
|
|
|
|
|
|
|
|
return &decl->dest.ssa;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#undef nir_load_reg
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_load_reg(nir_builder *b, nir_ssa_def *reg)
|
|
|
|
|
{
|
|
|
|
|
nir_intrinsic_instr *decl = nir_reg_get_decl(reg);
|
|
|
|
|
unsigned num_components = nir_intrinsic_num_components(decl);
|
|
|
|
|
unsigned bit_size = nir_intrinsic_bit_size(decl);
|
|
|
|
|
|
|
|
|
|
return nir_build_load_reg(b, num_components, bit_size, reg);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#undef nir_store_reg
|
|
|
|
|
static inline void
|
|
|
|
|
nir_store_reg(nir_builder *b, nir_ssa_def *value, nir_ssa_def *reg)
|
|
|
|
|
{
|
|
|
|
|
ASSERTED nir_intrinsic_instr *decl = nir_reg_get_decl(reg);
|
|
|
|
|
ASSERTED unsigned num_components = nir_intrinsic_num_components(decl);
|
|
|
|
|
ASSERTED unsigned bit_size = nir_intrinsic_bit_size(decl);
|
|
|
|
|
|
|
|
|
|
assert(value->num_components == num_components);
|
|
|
|
|
assert(value->bit_size == bit_size);
|
|
|
|
|
|
|
|
|
|
nir_build_store_reg(b, value, reg);
|
|
|
|
|
}
|
|
|
|
|
|
2023-05-25 16:51:33 -04:00
|
|
|
static inline nir_tex_src
|
|
|
|
|
nir_tex_src_for_ssa(nir_tex_src_type src_type, nir_ssa_def *def)
|
|
|
|
|
{
|
|
|
|
|
nir_tex_src src;
|
|
|
|
|
src.src = nir_src_for_ssa(def);
|
|
|
|
|
src.src_type = src_type;
|
|
|
|
|
return src;
|
|
|
|
|
}
|
|
|
|
|
|
2023-06-07 17:55:10 -04:00
|
|
|
/*
|
|
|
|
|
* Find a texture source, remove it, and return its nir_ssa_def. If the texture
|
|
|
|
|
* source does not exist, return NULL. This is useful for texture lowering pass
|
|
|
|
|
* that consume their input sources and produce a new lowered source.
|
|
|
|
|
*/
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_steal_tex_src(nir_tex_instr *tex, nir_tex_src_type type_)
|
|
|
|
|
{
|
|
|
|
|
int idx = nir_tex_instr_src_index(tex, type_);
|
|
|
|
|
if (idx < 0)
|
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
|
|
assert(tex->src[idx].src.is_ssa);
|
|
|
|
|
nir_ssa_def *ssa = tex->src[idx].src.ssa;
|
|
|
|
|
nir_tex_instr_remove_src(tex, idx);
|
|
|
|
|
return ssa;
|
|
|
|
|
}
|
|
|
|
|
|
2022-11-02 13:37:06 -05:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_tex_deref(nir_builder *b, nir_deref_instr *t, nir_deref_instr *s,
|
|
|
|
|
nir_ssa_def *coord)
|
|
|
|
|
{
|
2023-05-25 16:51:33 -04:00
|
|
|
nir_tex_src srcs[] = {nir_tex_src_for_ssa(nir_tex_src_coord, coord)};
|
2022-11-02 13:37:06 -05:00
|
|
|
|
|
|
|
|
return nir_build_tex_deref_instr(b, nir_texop_tex, t, s,
|
|
|
|
|
ARRAY_SIZE(srcs), srcs);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_txl_deref(nir_builder *b, nir_deref_instr *t, nir_deref_instr *s,
|
|
|
|
|
nir_ssa_def *coord, nir_ssa_def *lod)
|
|
|
|
|
{
|
2023-05-25 16:51:33 -04:00
|
|
|
nir_tex_src srcs[] = {
|
|
|
|
|
nir_tex_src_for_ssa(nir_tex_src_coord, coord),
|
|
|
|
|
nir_tex_src_for_ssa(nir_tex_src_lod, lod),
|
|
|
|
|
};
|
2022-11-02 13:37:06 -05:00
|
|
|
|
|
|
|
|
return nir_build_tex_deref_instr(b, nir_texop_txl, t, s,
|
|
|
|
|
ARRAY_SIZE(srcs), srcs);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_txl_zero_deref(nir_builder *b, nir_deref_instr *t, nir_deref_instr *s,
|
|
|
|
|
nir_ssa_def *coord)
|
|
|
|
|
{
|
|
|
|
|
return nir_txl_deref(b, t, s, coord, nir_imm_float(b, 0));
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_txf_deref(nir_builder *b, nir_deref_instr *t,
|
|
|
|
|
nir_ssa_def *coord, nir_ssa_def *lod)
|
|
|
|
|
{
|
|
|
|
|
nir_tex_src srcs[2];
|
|
|
|
|
unsigned num_srcs = 0;
|
|
|
|
|
|
2023-05-25 16:51:33 -04:00
|
|
|
srcs[num_srcs++] = nir_tex_src_for_ssa(nir_tex_src_coord, coord);
|
2022-11-02 13:37:06 -05:00
|
|
|
|
|
|
|
|
if (lod == NULL) {
|
|
|
|
|
switch (glsl_get_sampler_dim(t->type)) {
|
|
|
|
|
case GLSL_SAMPLER_DIM_1D:
|
|
|
|
|
case GLSL_SAMPLER_DIM_2D:
|
|
|
|
|
case GLSL_SAMPLER_DIM_3D:
|
|
|
|
|
case GLSL_SAMPLER_DIM_CUBE:
|
|
|
|
|
lod = nir_imm_int(b, 0);
|
|
|
|
|
break;
|
|
|
|
|
default:
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2023-05-25 16:51:33 -04:00
|
|
|
if (lod != NULL)
|
|
|
|
|
srcs[num_srcs++] = nir_tex_src_for_ssa(nir_tex_src_lod, lod);
|
2022-11-02 13:37:06 -05:00
|
|
|
|
|
|
|
|
return nir_build_tex_deref_instr(b, nir_texop_txf, t, NULL,
|
|
|
|
|
num_srcs, srcs);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_txf_ms_deref(nir_builder *b, nir_deref_instr *t,
|
|
|
|
|
nir_ssa_def *coord, nir_ssa_def *ms_index)
|
|
|
|
|
{
|
2023-05-25 16:51:33 -04:00
|
|
|
nir_tex_src srcs[] = {
|
|
|
|
|
nir_tex_src_for_ssa(nir_tex_src_coord, coord),
|
|
|
|
|
nir_tex_src_for_ssa(nir_tex_src_ms_index, ms_index),
|
|
|
|
|
};
|
2022-11-02 13:37:06 -05:00
|
|
|
|
|
|
|
|
return nir_build_tex_deref_instr(b, nir_texop_txf_ms, t, NULL,
|
|
|
|
|
ARRAY_SIZE(srcs), srcs);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_samples_identical_deref(nir_builder *b, nir_deref_instr *t,
|
|
|
|
|
nir_ssa_def *coord)
|
|
|
|
|
{
|
2023-05-25 16:51:33 -04:00
|
|
|
nir_tex_src srcs[] = {nir_tex_src_for_ssa(nir_tex_src_coord, coord)};
|
2022-11-02 13:37:06 -05:00
|
|
|
|
|
|
|
|
return nir_build_tex_deref_instr(b, nir_texop_samples_identical, t, NULL,
|
|
|
|
|
ARRAY_SIZE(srcs), srcs);
|
|
|
|
|
}
|
|
|
|
|
|
2021-05-04 10:24:03 -04:00
|
|
|
/* calculate a `(1 << value) - 1` in ssa without overflows */
|
|
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_mask(nir_builder *b, nir_ssa_def *bits, unsigned dst_bit_size)
|
|
|
|
|
{
|
|
|
|
|
return nir_ushr(b, nir_imm_intN_t(b, -1, dst_bit_size),
|
|
|
|
|
nir_isub_imm(b, dst_bit_size, nir_u2u32(b, bits)));
|
|
|
|
|
}
|
|
|
|
|
|
nir: Add new intrinsics for fragment shader input interpolation.
Backends can normally handle shader inputs solely by looking at
load_input intrinsics, and ignore the nir_variables in nir->inputs.
One exception is fragment shader inputs. load_input doesn't capture
the necessary interpolation information - flat, smooth, noperspective
mode, and centroid, sample, or pixel for the location. This means
that backends have to interpolate based on the nir_variables, then
associate those with the load_input intrinsics (say, by storing a
map of which variables are at which locations).
With GL_ARB_enhanced_layouts, we're going to have multiple varyings
packed into a single vec4 location. The intrinsics make this easy:
simply load N components from location <loc, component>. However,
working with variables and correlating the two is very awkward; we'd
much rather have intrinsics capture all the necessary information.
Fragment shader input interpolation typically works by producing a
set of barycentric coordinates, then using those to do a linear
interpolation between the values at the triangle's corners.
We represent this by introducing five new load_barycentric_* intrinsics:
- load_barycentric_pixel (ordinary variable)
- load_barycentric_centroid (centroid qualified variable)
- load_barycentric_sample (sample qualified variable)
- load_barycentric_at_sample (ARB_gpu_shader5's interpolateAtSample())
- load_barycentric_at_offset (ARB_gpu_shader5's interpolateAtOffset())
Each of these take the interpolation mode (smooth or noperspective only)
as a const_index, and produce a vec2. The last two also take a sample
or offset source.
We then introduce a new load_interpolated_input intrinsic, which
is like a normal load_input intrinsic, but with an additional
barycentric coordinate source.
The intention is that flat inputs will still use regular load_input
intrinsics. This makes them distinguishable from normal inputs that
need fancy interpolation, while also providing all the necessary data.
This nicely unifies regular inputs and interpolateAt functions.
Qualifiers and variables become irrelevant; there are just
load_barycentric intrinsics that determine the interpolation.
v2: Document the interp_mode const_index value, define a new
BARYCENTRIC() helper rather than using SYSTEM_VALUE() for
some of them (requested by Jason Ekstrand).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-07-12 01:46:43 -07:00
|
|
|
static inline nir_ssa_def *
|
|
|
|
|
nir_load_barycentric(nir_builder *build, nir_intrinsic_op op,
|
|
|
|
|
unsigned interp_mode)
|
|
|
|
|
{
|
2020-01-24 11:36:37 +01:00
|
|
|
unsigned num_components = op == nir_intrinsic_load_barycentric_model ? 3 : 2;
|
nir: Add new intrinsics for fragment shader input interpolation.
Backends can normally handle shader inputs solely by looking at
load_input intrinsics, and ignore the nir_variables in nir->inputs.
One exception is fragment shader inputs. load_input doesn't capture
the necessary interpolation information - flat, smooth, noperspective
mode, and centroid, sample, or pixel for the location. This means
that backends have to interpolate based on the nir_variables, then
associate those with the load_input intrinsics (say, by storing a
map of which variables are at which locations).
With GL_ARB_enhanced_layouts, we're going to have multiple varyings
packed into a single vec4 location. The intrinsics make this easy:
simply load N components from location <loc, component>. However,
working with variables and correlating the two is very awkward; we'd
much rather have intrinsics capture all the necessary information.
Fragment shader input interpolation typically works by producing a
set of barycentric coordinates, then using those to do a linear
interpolation between the values at the triangle's corners.
We represent this by introducing five new load_barycentric_* intrinsics:
- load_barycentric_pixel (ordinary variable)
- load_barycentric_centroid (centroid qualified variable)
- load_barycentric_sample (sample qualified variable)
- load_barycentric_at_sample (ARB_gpu_shader5's interpolateAtSample())
- load_barycentric_at_offset (ARB_gpu_shader5's interpolateAtOffset())
Each of these take the interpolation mode (smooth or noperspective only)
as a const_index, and produce a vec2. The last two also take a sample
or offset source.
We then introduce a new load_interpolated_input intrinsic, which
is like a normal load_input intrinsic, but with an additional
barycentric coordinate source.
The intention is that flat inputs will still use regular load_input
intrinsics. This makes them distinguishable from normal inputs that
need fancy interpolation, while also providing all the necessary data.
This nicely unifies regular inputs and interpolateAt functions.
Qualifiers and variables become irrelevant; there are just
load_barycentric intrinsics that determine the interpolation.
v2: Document the interp_mode const_index value, define a new
BARYCENTRIC() helper rather than using SYSTEM_VALUE() for
some of them (requested by Jason Ekstrand).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-07-12 01:46:43 -07:00
|
|
|
nir_intrinsic_instr *bary = nir_intrinsic_instr_create(build->shader, op);
|
nir: Drop unused name from nir_ssa_dest_init
Since 624e799cc34 ("nir: Drop nir_ssa_def::name and nir_register::name"), SSA
defs don't have names, making the name argument unused. Drop it from the
signature and fix the call sites. This was done with the help of the following
Coccinelle semantic patch:
@@
expression A, B, C, D, E;
@@
-nir_ssa_dest_init(A, B, C, D, E);
+nir_ssa_dest_init(A, B, C, D);
Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Timur Kristóf <timur.kristof@gmail.com>
Reviewed-by: Emma Anholt <emma@anholt.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/23078>
2023-05-17 09:08:22 -04:00
|
|
|
nir_ssa_dest_init(&bary->instr, &bary->dest, num_components, 32);
|
nir: Add new intrinsics for fragment shader input interpolation.
Backends can normally handle shader inputs solely by looking at
load_input intrinsics, and ignore the nir_variables in nir->inputs.
One exception is fragment shader inputs. load_input doesn't capture
the necessary interpolation information - flat, smooth, noperspective
mode, and centroid, sample, or pixel for the location. This means
that backends have to interpolate based on the nir_variables, then
associate those with the load_input intrinsics (say, by storing a
map of which variables are at which locations).
With GL_ARB_enhanced_layouts, we're going to have multiple varyings
packed into a single vec4 location. The intrinsics make this easy:
simply load N components from location <loc, component>. However,
working with variables and correlating the two is very awkward; we'd
much rather have intrinsics capture all the necessary information.
Fragment shader input interpolation typically works by producing a
set of barycentric coordinates, then using those to do a linear
interpolation between the values at the triangle's corners.
We represent this by introducing five new load_barycentric_* intrinsics:
- load_barycentric_pixel (ordinary variable)
- load_barycentric_centroid (centroid qualified variable)
- load_barycentric_sample (sample qualified variable)
- load_barycentric_at_sample (ARB_gpu_shader5's interpolateAtSample())
- load_barycentric_at_offset (ARB_gpu_shader5's interpolateAtOffset())
Each of these take the interpolation mode (smooth or noperspective only)
as a const_index, and produce a vec2. The last two also take a sample
or offset source.
We then introduce a new load_interpolated_input intrinsic, which
is like a normal load_input intrinsic, but with an additional
barycentric coordinate source.
The intention is that flat inputs will still use regular load_input
intrinsics. This makes them distinguishable from normal inputs that
need fancy interpolation, while also providing all the necessary data.
This nicely unifies regular inputs and interpolateAt functions.
Qualifiers and variables become irrelevant; there are just
load_barycentric intrinsics that determine the interpolation.
v2: Document the interp_mode const_index value, define a new
BARYCENTRIC() helper rather than using SYSTEM_VALUE() for
some of them (requested by Jason Ekstrand).
Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Reviewed-by: Chris Forbes <chrisforbes@google.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-07-12 01:46:43 -07:00
|
|
|
nir_intrinsic_set_interp_mode(bary, interp_mode);
|
|
|
|
|
nir_builder_instr_insert(build, &bary->instr);
|
|
|
|
|
return &bary->dest.ssa;
|
|
|
|
|
}
|
|
|
|
|
|
2016-02-13 17:14:27 -08:00
|
|
|
static inline void
|
|
|
|
|
nir_jump(nir_builder *build, nir_jump_type jump_type)
|
|
|
|
|
{
|
2020-07-02 14:32:04 +02:00
|
|
|
assert(jump_type != nir_jump_goto && jump_type != nir_jump_goto_if);
|
2016-02-13 17:14:27 -08:00
|
|
|
nir_jump_instr *jump = nir_jump_instr_create(build->shader, jump_type);
|
|
|
|
|
nir_builder_instr_insert(build, &jump->instr);
|
|
|
|
|
}
|
|
|
|
|
|
2020-07-02 14:32:04 +02:00
|
|
|
static inline void
|
|
|
|
|
nir_goto(nir_builder *build, struct nir_block *target)
|
|
|
|
|
{
|
|
|
|
|
assert(!build->impl->structured);
|
|
|
|
|
nir_jump_instr *jump = nir_jump_instr_create(build->shader, nir_jump_goto);
|
|
|
|
|
jump->target = target;
|
|
|
|
|
nir_builder_instr_insert(build, &jump->instr);
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
static inline void
|
|
|
|
|
nir_goto_if(nir_builder *build, struct nir_block *target, nir_src cond,
|
|
|
|
|
struct nir_block *else_target)
|
|
|
|
|
{
|
|
|
|
|
assert(!build->impl->structured);
|
|
|
|
|
nir_jump_instr *jump = nir_jump_instr_create(build->shader, nir_jump_goto_if);
|
|
|
|
|
jump->condition = cond;
|
|
|
|
|
jump->target = target;
|
|
|
|
|
jump->else_target = else_target;
|
|
|
|
|
nir_builder_instr_insert(build, &jump->instr);
|
|
|
|
|
}
|
|
|
|
|
|
2021-11-19 16:50:03 -08:00
|
|
|
nir_ssa_def *
|
2017-02-22 16:53:18 -08:00
|
|
|
nir_compare_func(nir_builder *b, enum compare_func func,
|
2021-11-19 16:50:03 -08:00
|
|
|
nir_ssa_def *src0, nir_ssa_def *src1);
|
2017-02-22 16:53:18 -08:00
|
|
|
|
2020-01-09 10:01:53 -08:00
|
|
|
static inline void
|
|
|
|
|
nir_scoped_memory_barrier(nir_builder *b,
|
2023-05-30 12:05:30 -07:00
|
|
|
mesa_scope scope,
|
2020-01-09 10:01:53 -08:00
|
|
|
nir_memory_semantics semantics,
|
|
|
|
|
nir_variable_mode modes)
|
|
|
|
|
{
|
2023-05-30 12:05:30 -07:00
|
|
|
nir_scoped_barrier(b, SCOPE_NONE, scope, semantics, modes);
|
2020-01-09 10:01:53 -08:00
|
|
|
}
|
|
|
|
|
|
2022-07-14 11:09:38 +02:00
|
|
|
nir_ssa_def *
|
|
|
|
|
nir_gen_rect_vertices(nir_builder *b, nir_ssa_def *z, nir_ssa_def *w);
|
|
|
|
|
|
2021-11-19 16:24:00 -08:00
|
|
|
#ifdef __cplusplus
|
|
|
|
|
} /* extern "C" */
|
|
|
|
|
#endif
|
|
|
|
|
|
2014-11-10 11:16:30 -08:00
|
|
|
#endif /* NIR_BUILDER_H */
|