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nir: allow 5 component vectors

Browse source 
These will be useful for sparse texture instructions and image load
intrinsics.

Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/7774>
This commit is contained in:
Rhys Perry 2020-11-23 13:05:58 +00:00 • committed by Marge Bot
parent ba4a73a502
commit 95819663b7
10 changed files with 29 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

4
src/compiler/nir/nir.h
View file

@ -72,7 +72,7 @@ static inline bool
nir_num_components_valid(unsigned num_components)
{
return (num_components >= 1 &&
num_components <= 4) ||
num_components <= 5) ||
num_components == 8 ||
num_components == 16;
}
@ -1210,6 +1210,7 @@ nir_op_vec(unsigned components)
case 2: return nir_op_vec2;
case 3: return nir_op_vec3;
case 4: return nir_op_vec4;
case 5: return nir_op_vec5;
case 8: return nir_op_vec8;
case 16: return nir_op_vec16;
default: unreachable("bad component count");
@ -1224,6 +1225,7 @@ nir_op_is_vec(nir_op op)
case nir_op_vec2:
case nir_op_vec3:
case nir_op_vec4:
case nir_op_vec5:
case nir_op_vec8:
case nir_op_vec16:
return true;

3
src/compiler/nir/nir_builder.h
View file

@ -603,6 +603,7 @@ nir_fdot(nir_builder *build, nir_ssa_def *src0, nir_ssa_def *src1)
case 2: return nir_fdot2(build, src0, src1);
case 3: return nir_fdot3(build, src0, src1);
case 4: return nir_fdot4(build, src0, src1);
case 5: return nir_fdot5(build, src0, src1);
case 8: return nir_fdot8(build, src0, src1);
case 16: return nir_fdot16(build, src0, src1);
default:
@ -620,6 +621,7 @@ nir_ball_iequal(nir_builder *b, nir_ssa_def *src0, nir_ssa_def *src1)
case 2: return nir_ball_iequal2(b, src0, src1);
case 3: return nir_ball_iequal3(b, src0, src1);
case 4: return nir_ball_iequal4(b, src0, src1);
case 5: return nir_ball_iequal5(b, src0, src1);
case 8: return nir_ball_iequal8(b, src0, src1);
case 16: return nir_ball_iequal16(b, src0, src1);
default:
@ -641,6 +643,7 @@ nir_bany_inequal(nir_builder *b, nir_ssa_def *src0, nir_ssa_def *src1)
case 2: return nir_bany_inequal2(b, src0, src1);
case 3: return nir_bany_inequal3(b, src0, src1);
case 4: return nir_bany_inequal4(b, src0, src1);
case 5: return nir_bany_inequal5(b, src0, src1);
case 8: return nir_bany_inequal8(b, src0, src1);
case 16: return nir_bany_inequal16(b, src0, src1);
default:

1
src/compiler/nir/nir_gather_ssa_types.c
View file

@ -112,6 +112,7 @@ nir_gather_ssa_types(nir_function_impl *impl,
case nir_op_vec2:
case nir_op_vec3:
case nir_op_vec4:
case nir_op_vec5:
case nir_op_vec8:
case nir_op_vec16:
for (unsigned i = 0; i < info->num_inputs; i++) {

1
src/compiler/nir/nir_lower_alu_to_scalar.c
View file

@ -121,6 +121,7 @@ lower_alu_instr_scalar(nir_builder *b, nir_instr *instr, void *_data)
switch (alu->op) {
case nir_op_vec16:
case nir_op_vec8:
case nir_op_vec5:
case nir_op_vec4:
case nir_op_vec3:
case nir_op_vec2:

2
src/compiler/nir/nir_lower_bool_to_bitsize.c
View file

@ -103,6 +103,7 @@ lower_alu_instr(nir_builder *b, nir_alu_instr *alu)
case nir_op_vec2:
case nir_op_vec3:
case nir_op_vec4:
case nir_op_vec5:
case nir_op_vec8:
case nir_op_vec16:
case nir_op_inot:
@ -152,6 +153,7 @@ lower_alu_instr(nir_builder *b, nir_alu_instr *alu)
case nir_op_vec2:
case nir_op_vec3:
case nir_op_vec4:
case nir_op_vec5:
case nir_op_vec8:
case nir_op_vec16:
case nir_op_inot:

1
src/compiler/nir/nir_lower_bool_to_float.c
View file

@ -56,6 +56,7 @@ lower_alu_instr(nir_builder *b, nir_alu_instr *alu)
case nir_op_vec2:
case nir_op_vec3:
case nir_op_vec4:
case nir_op_vec5:
case nir_op_vec8:
case nir_op_vec16:
if (alu->dest.dest.ssa.bit_size != 1)

1
src/compiler/nir/nir_lower_bool_to_int32.c
View file

@ -53,6 +53,7 @@ lower_alu_instr(nir_alu_instr *alu)
case nir_op_vec2:
case nir_op_vec3:
case nir_op_vec4:
case nir_op_vec5:
case nir_op_vec8:
case nir_op_vec16:
case nir_op_inot:

17
src/compiler/nir/nir_opcodes.py
View file

@ -75,9 +75,9 @@ class Opcode(object):
assert isinstance(algebraic_properties, str)
assert isinstance(const_expr, str)
assert len(input_sizes) == len(input_types)
assert 0 <= output_size <= 4 or (output_size == 8) or (output_size == 16)
assert 0 <= output_size <= 5 or (output_size == 8) or (output_size == 16)
for size in input_sizes:
assert 0 <= size <= 4 or (size == 8) or (size == 16)
assert 0 <= size <= 5 or (size == 8) or (size == 16)
if output_size != 0:
assert size != 0
self.name = name
@ -575,6 +575,9 @@ def binop_reduce(name, output_size, output_type, src_type, prereduce_expr,
opcode(name + "3" + suffix, output_size, output_type,
[3, 3], [src_type, src_type], False, _2src_commutative,
final(reduce_(reduce_(srcs[2], srcs[1]), srcs[0])))
opcode(name + "5" + suffix, output_size, output_type,
[5, 5], [src_type, src_type], False, _2src_commutative,
final(reduce_(srcs[4], reduce_(reduce_(srcs[3], srcs[2]), reduce_(srcs[1], srcs[0])))))
def binop_reduce_all_sizes(name, output_size, src_type, prereduce_expr,
reduce_expr, final_expr):
@ -1094,6 +1097,16 @@ dst.z = src2.x;
dst.w = src3.x;
""")
opcode("vec5", 5, tuint,
[1] * 5, [tuint] * 5,
False, "", """
dst.x = src0.x;
dst.y = src1.x;
dst.z = src2.x;
dst.w = src3.x;
dst.e = src4.x;
""")
opcode("vec8", 8, tuint,
[1] * 8, [tuint] * 8,
False, "", """

1
src/compiler/nir/nir_opt_peephole_select.c
View file

@ -143,6 +143,7 @@ block_check_for_allowed_instrs(nir_block *block, unsigned *count,
case nir_op_vec2:
case nir_op_vec3:
case nir_op_vec4:
case nir_op_vec5:
case nir_op_vec8:
case nir_op_vec16:
movelike = true;

2
src/compiler/nir/nir_print.c
View file

@ -87,7 +87,7 @@ print_register(nir_register *reg, print_state *state)
}
static const char *sizes[] = { "error", "vec1", "vec2", "vec3", "vec4",
"error", "error", "error", "vec8",
"vec5", "error", "error", "vec8",
"error", "error", "error", "error",
"error", "error", "error", "vec16"};