2014-12-12 11:28:05 -08:00
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/*
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* Mesa 3-D graphics library
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*
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* Copyright 2012 Intel Corporation
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* Copyright 2013 Google
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the
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* "Software"), to deal in the Software without restriction, including
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* without limitation the rights to use, copy, modify, merge, publish,
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2015-08-19 16:36:35 -07:00
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* distribute, sublicense, and/or sell copies of the Software, and to
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2014-12-12 11:28:05 -08:00
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* permit persons to whom the Software is furnished to do so, subject to
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* the following conditions:
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*
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* The above copyright notice and this permission notice (including the
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* next paragraph) shall be included in all copies or substantial portions
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* of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
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* OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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2015-08-19 16:36:35 -07:00
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
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2014-12-12 11:28:05 -08:00
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* IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
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* ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
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* TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
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* SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Chad Versace <chad.versace@linux.intel.com>
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* Frank Henigman <fjhenigman@google.com>
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*/
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#include <string.h>
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#include "util/macros.h"
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2021-12-07 17:20:31 +10:00
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#include "util/u_math.h"
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#include "util/rounding.h"
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2018-12-17 14:17:15 +02:00
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#include "isl_priv.h"
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2014-12-12 11:28:05 -08:00
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2016-01-29 03:18:36 +01:00
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#if defined(__SSSE3__)
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2014-12-12 11:28:05 -08:00
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#include <tmmintrin.h>
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2016-01-29 03:18:36 +01:00
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#elif defined(__SSE2__)
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#include <emmintrin.h>
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2014-12-12 11:28:05 -08:00
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#endif
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#define FILE_DEBUG_FLAG DEBUG_TEXTURE
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#define ALIGN_DOWN(a, b) ROUND_DOWN_TO(a, b)
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#define ALIGN_UP(a, b) ALIGN(a, b)
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/* Tile dimensions. Width and span are in bytes, height is in pixels (i.e.
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* unitless). A "span" is the most number of bytes we can copy from linear
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* to tiled without needing to calculate a new destination address.
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*/
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static const uint32_t xtile_width = 512;
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static const uint32_t xtile_height = 8;
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static const uint32_t xtile_span = 64;
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static const uint32_t ytile_width = 128;
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static const uint32_t ytile_height = 32;
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static const uint32_t ytile_span = 16;
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2016-04-08 15:30:30 -07:00
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static inline uint32_t
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ror(uint32_t n, uint32_t d)
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{
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return (n >> d) | (n << (32 - d));
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}
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2018-05-27 00:36:30 +03:00
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// bswap32 already exists as a macro on some platforms (FreeBSD)
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#ifndef bswap32
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2016-04-19 12:31:20 +10:00
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static inline uint32_t
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bswap32(uint32_t n)
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{
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#if defined(HAVE___BUILTIN_BSWAP32)
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return __builtin_bswap32(n);
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#else
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return (n >> 24) |
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((n >> 8) & 0x0000ff00) |
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((n << 8) & 0x00ff0000) |
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(n << 24);
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#endif
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}
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2018-05-27 00:36:30 +03:00
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#endif
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2016-04-19 12:31:20 +10:00
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2016-04-07 11:21:19 -07:00
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/**
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* Copy RGBA to BGRA - swap R and B.
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*/
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static inline void *
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rgba8_copy(void *dst, const void *src, size_t bytes)
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{
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2016-04-08 15:30:30 -07:00
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uint32_t *d = dst;
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uint32_t const *s = src;
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2016-04-07 11:21:19 -07:00
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assert(bytes % 4 == 0);
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while (bytes >= 4) {
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2016-04-19 12:31:20 +10:00
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*d = ror(bswap32(*s), 8);
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2016-04-08 15:30:30 -07:00
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d += 1;
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s += 1;
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2016-04-07 11:21:19 -07:00
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bytes -= 4;
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}
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return dst;
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}
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2016-02-02 15:45:59 +01:00
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#ifdef __SSSE3__
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2014-12-12 11:28:05 -08:00
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static const uint8_t rgba8_permutation[16] =
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{ 2,1,0,3, 6,5,4,7, 10,9,8,11, 14,13,12,15 };
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2016-04-11 11:47:21 -07:00
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static inline void
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rgba8_copy_16_aligned_dst(void *dst, const void *src)
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{
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_mm_store_si128(dst,
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_mm_shuffle_epi8(_mm_loadu_si128(src),
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*(__m128i *)rgba8_permutation));
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}
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static inline void
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rgba8_copy_16_aligned_src(void *dst, const void *src)
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{
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_mm_storeu_si128(dst,
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_mm_shuffle_epi8(_mm_load_si128(src),
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*(__m128i *)rgba8_permutation));
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}
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2016-01-29 03:18:36 +01:00
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#elif defined(__SSE2__)
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static inline void
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rgba8_copy_16_aligned_dst(void *dst, const void *src)
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{
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__m128i srcreg, dstreg, agmask, ag, rb, br;
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agmask = _mm_set1_epi32(0xFF00FF00);
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srcreg = _mm_loadu_si128((__m128i *)src);
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rb = _mm_andnot_si128(agmask, srcreg);
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ag = _mm_and_si128(agmask, srcreg);
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br = _mm_shufflehi_epi16(_mm_shufflelo_epi16(rb, _MM_SHUFFLE(2, 3, 0, 1)),
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_MM_SHUFFLE(2, 3, 0, 1));
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dstreg = _mm_or_si128(ag, br);
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_mm_store_si128((__m128i *)dst, dstreg);
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}
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static inline void
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rgba8_copy_16_aligned_src(void *dst, const void *src)
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{
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__m128i srcreg, dstreg, agmask, ag, rb, br;
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agmask = _mm_set1_epi32(0xFF00FF00);
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srcreg = _mm_load_si128((__m128i *)src);
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rb = _mm_andnot_si128(agmask, srcreg);
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ag = _mm_and_si128(agmask, srcreg);
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br = _mm_shufflehi_epi16(_mm_shufflelo_epi16(rb, _MM_SHUFFLE(2, 3, 0, 1)),
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_MM_SHUFFLE(2, 3, 0, 1));
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dstreg = _mm_or_si128(ag, br);
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_mm_storeu_si128((__m128i *)dst, dstreg);
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}
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2014-12-12 11:28:05 -08:00
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#endif
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/**
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2015-03-04 15:21:53 -08:00
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* Copy RGBA to BGRA - swap R and B, with the destination 16-byte aligned.
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2014-12-12 11:28:05 -08:00
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*/
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static inline void *
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2015-03-04 15:21:53 -08:00
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rgba8_copy_aligned_dst(void *dst, const void *src, size_t bytes)
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2014-12-12 11:28:05 -08:00
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{
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2016-04-07 11:21:19 -07:00
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assert(bytes == 0 || !(((uintptr_t)dst) & 0xf));
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2014-12-12 11:28:05 -08:00
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2016-01-29 03:18:36 +01:00
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#if defined(__SSSE3__) || defined(__SSE2__)
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2016-04-11 11:59:59 -07:00
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if (bytes == 64) {
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rgba8_copy_16_aligned_dst(dst + 0, src + 0);
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rgba8_copy_16_aligned_dst(dst + 16, src + 16);
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rgba8_copy_16_aligned_dst(dst + 32, src + 32);
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rgba8_copy_16_aligned_dst(dst + 48, src + 48);
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return dst;
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}
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2016-04-07 11:21:19 -07:00
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while (bytes >= 16) {
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2016-04-11 11:47:21 -07:00
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rgba8_copy_16_aligned_dst(dst, src);
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src += 16;
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dst += 16;
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2016-04-07 11:21:19 -07:00
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bytes -= 16;
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2015-03-04 15:21:53 -08:00
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}
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#endif
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2016-04-11 11:47:21 -07:00
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rgba8_copy(dst, src, bytes);
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2016-04-07 11:21:19 -07:00
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2015-03-04 15:21:53 -08:00
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return dst;
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}
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/**
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* Copy RGBA to BGRA - swap R and B, with the source 16-byte aligned.
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*/
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static inline void *
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rgba8_copy_aligned_src(void *dst, const void *src, size_t bytes)
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{
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2016-04-07 11:21:19 -07:00
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assert(bytes == 0 || !(((uintptr_t)src) & 0xf));
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2015-03-04 15:21:53 -08:00
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2016-01-29 03:18:36 +01:00
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#if defined(__SSSE3__) || defined(__SSE2__)
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2016-04-11 11:59:59 -07:00
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if (bytes == 64) {
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2016-04-12 15:23:17 -07:00
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rgba8_copy_16_aligned_src(dst + 0, src + 0);
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rgba8_copy_16_aligned_src(dst + 16, src + 16);
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rgba8_copy_16_aligned_src(dst + 32, src + 32);
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rgba8_copy_16_aligned_src(dst + 48, src + 48);
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2016-04-11 11:59:59 -07:00
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return dst;
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}
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2016-04-07 11:21:19 -07:00
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while (bytes >= 16) {
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2016-04-11 11:47:21 -07:00
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rgba8_copy_16_aligned_src(dst, src);
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src += 16;
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dst += 16;
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2016-04-07 11:21:19 -07:00
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bytes -= 16;
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2014-12-12 11:28:05 -08:00
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}
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#endif
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2016-04-11 11:47:21 -07:00
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rgba8_copy(dst, src, bytes);
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2016-04-07 11:21:19 -07:00
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2014-12-12 11:28:05 -08:00
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return dst;
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}
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/**
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* Each row from y0 to y1 is copied in three parts: [x0,x1), [x1,x2), [x2,x3).
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* These ranges are in bytes, i.e. pixels * bytes-per-pixel.
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* The first and last ranges must be shorter than a "span" (the longest linear
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* stretch within a tile) and the middle must equal a whole number of spans.
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* Ranges may be empty. The region copied must land entirely within one tile.
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* 'dst' is the start of the tile and 'src' is the corresponding
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* address to copy from, though copying begins at (x0, y0).
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* To enable swizzling 'swizzle_bit' must be 1<<6, otherwise zero.
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* Swizzling flips bit 6 in the copy destination offset, when certain other
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* bits are set in it.
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*/
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typedef void (*tile_copy_fn)(uint32_t x0, uint32_t x1, uint32_t x2, uint32_t x3,
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uint32_t y0, uint32_t y1,
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char *dst, const char *src,
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2015-01-28 03:30:32 -08:00
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int32_t linear_pitch,
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2014-12-12 11:28:05 -08:00
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uint32_t swizzle_bit,
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2018-12-17 14:17:15 +02:00
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isl_memcpy_type copy_type);
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2014-12-12 11:28:05 -08:00
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/**
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* Copy texture data from linear to X tile layout.
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*
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* \copydoc tile_copy_fn
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2016-04-07 10:52:28 -07:00
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*
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* The mem_copy parameters allow the user to specify an alternative mem_copy
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* function that, for instance, may do RGBA -> BGRA swizzling. The first
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* function must handle any memory alignment while the second function must
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* only handle 16-byte alignment in whichever side (source or destination) is
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* tiled.
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2014-12-12 11:28:05 -08:00
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*/
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static inline void
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linear_to_xtiled(uint32_t x0, uint32_t x1, uint32_t x2, uint32_t x3,
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uint32_t y0, uint32_t y1,
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char *dst, const char *src,
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2015-01-28 03:30:32 -08:00
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int32_t src_pitch,
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2014-12-12 11:28:05 -08:00
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uint32_t swizzle_bit,
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2018-12-17 14:17:15 +02:00
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isl_mem_copy_fn mem_copy,
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isl_mem_copy_fn mem_copy_align16)
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2014-12-12 11:28:05 -08:00
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{
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/* The copy destination offset for each range copied is the sum of
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* an X offset 'x0' or 'xo' and a Y offset 'yo.'
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*/
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uint32_t xo, yo;
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2015-01-28 03:30:32 -08:00
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src += (ptrdiff_t)y0 * src_pitch;
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2014-12-12 11:28:05 -08:00
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for (yo = y0 * xtile_width; yo < y1 * xtile_width; yo += xtile_width) {
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/* Bits 9 and 10 of the copy destination offset control swizzling.
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* Only 'yo' contributes to those bits in the total offset,
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* so calculate 'swizzle' just once per row.
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* Move bits 9 and 10 three and four places respectively down
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* to bit 6 and xor them.
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*/
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uint32_t swizzle = ((yo >> 3) ^ (yo >> 4)) & swizzle_bit;
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mem_copy(dst + ((x0 + yo) ^ swizzle), src + x0, x1 - x0);
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for (xo = x1; xo < x2; xo += xtile_span) {
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2016-04-07 10:52:28 -07:00
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mem_copy_align16(dst + ((xo + yo) ^ swizzle), src + xo, xtile_span);
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2014-12-12 11:28:05 -08:00
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|
|
}
|
|
|
|
|
|
2016-04-07 10:52:28 -07:00
|
|
|
mem_copy_align16(dst + ((xo + yo) ^ swizzle), src + x2, x3 - x2);
|
2014-12-12 11:28:05 -08:00
|
|
|
|
|
|
|
|
src += src_pitch;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* Copy texture data from linear to Y tile layout.
|
|
|
|
|
*
|
|
|
|
|
* \copydoc tile_copy_fn
|
|
|
|
|
*/
|
|
|
|
|
static inline void
|
|
|
|
|
linear_to_ytiled(uint32_t x0, uint32_t x1, uint32_t x2, uint32_t x3,
|
2018-01-26 16:07:15 -08:00
|
|
|
uint32_t y0, uint32_t y3,
|
2014-12-12 11:28:05 -08:00
|
|
|
char *dst, const char *src,
|
2015-01-28 03:30:32 -08:00
|
|
|
int32_t src_pitch,
|
2014-12-12 11:28:05 -08:00
|
|
|
uint32_t swizzle_bit,
|
2018-12-17 14:17:15 +02:00
|
|
|
isl_mem_copy_fn mem_copy,
|
|
|
|
|
isl_mem_copy_fn mem_copy_align16)
|
2014-12-12 11:28:05 -08:00
|
|
|
{
|
|
|
|
|
/* Y tiles consist of columns that are 'ytile_span' wide (and the same height
|
|
|
|
|
* as the tile). Thus the destination offset for (x,y) is the sum of:
|
|
|
|
|
* (x % column_width) // position within column
|
|
|
|
|
* (x / column_width) * bytes_per_column // column number * bytes per column
|
|
|
|
|
* y * column_width
|
|
|
|
|
*
|
|
|
|
|
* The copy destination offset for each range copied is the sum of
|
|
|
|
|
* an X offset 'xo0' or 'xo' and a Y offset 'yo.'
|
|
|
|
|
*/
|
|
|
|
|
const uint32_t column_width = ytile_span;
|
|
|
|
|
const uint32_t bytes_per_column = column_width * ytile_height;
|
|
|
|
|
|
2018-01-26 16:07:15 -08:00
|
|
|
uint32_t y1 = MIN2(y3, ALIGN_UP(y0, 4));
|
|
|
|
|
uint32_t y2 = MAX2(y1, ALIGN_DOWN(y3, 4));
|
|
|
|
|
|
2014-12-12 11:28:05 -08:00
|
|
|
uint32_t xo0 = (x0 % ytile_span) + (x0 / ytile_span) * bytes_per_column;
|
|
|
|
|
uint32_t xo1 = (x1 % ytile_span) + (x1 / ytile_span) * bytes_per_column;
|
|
|
|
|
|
|
|
|
|
/* Bit 9 of the destination offset control swizzling.
|
|
|
|
|
* Only the X offset contributes to bit 9 of the total offset,
|
|
|
|
|
* so swizzle can be calculated in advance for these X positions.
|
|
|
|
|
* Move bit 9 three places down to bit 6.
|
|
|
|
|
*/
|
|
|
|
|
uint32_t swizzle0 = (xo0 >> 3) & swizzle_bit;
|
|
|
|
|
uint32_t swizzle1 = (xo1 >> 3) & swizzle_bit;
|
|
|
|
|
|
|
|
|
|
uint32_t x, yo;
|
|
|
|
|
|
2015-01-28 03:30:32 -08:00
|
|
|
src += (ptrdiff_t)y0 * src_pitch;
|
2014-12-12 11:28:05 -08:00
|
|
|
|
2018-01-26 16:07:15 -08:00
|
|
|
if (y0 != y1) {
|
|
|
|
|
for (yo = y0 * column_width; yo < y1 * column_width; yo += column_width) {
|
|
|
|
|
uint32_t xo = xo1;
|
|
|
|
|
uint32_t swizzle = swizzle1;
|
|
|
|
|
|
|
|
|
|
mem_copy(dst + ((xo0 + yo) ^ swizzle0), src + x0, x1 - x0);
|
|
|
|
|
|
|
|
|
|
/* Step by spans/columns. As it happens, the swizzle bit flips
|
|
|
|
|
* at each step so we don't need to calculate it explicitly.
|
|
|
|
|
*/
|
|
|
|
|
for (x = x1; x < x2; x += ytile_span) {
|
|
|
|
|
mem_copy_align16(dst + ((xo + yo) ^ swizzle), src + x, ytile_span);
|
|
|
|
|
xo += bytes_per_column;
|
|
|
|
|
swizzle ^= swizzle_bit;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mem_copy_align16(dst + ((xo + yo) ^ swizzle), src + x2, x3 - x2);
|
|
|
|
|
|
|
|
|
|
src += src_pitch;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (yo = y1 * column_width; yo < y2 * column_width; yo += 4 * column_width) {
|
2014-12-12 11:28:05 -08:00
|
|
|
uint32_t xo = xo1;
|
|
|
|
|
uint32_t swizzle = swizzle1;
|
|
|
|
|
|
2018-01-26 16:07:15 -08:00
|
|
|
if (x0 != x1) {
|
|
|
|
|
mem_copy(dst + ((xo0 + yo + 0 * column_width) ^ swizzle0), src + x0 + 0 * src_pitch, x1 - x0);
|
|
|
|
|
mem_copy(dst + ((xo0 + yo + 1 * column_width) ^ swizzle0), src + x0 + 1 * src_pitch, x1 - x0);
|
|
|
|
|
mem_copy(dst + ((xo0 + yo + 2 * column_width) ^ swizzle0), src + x0 + 2 * src_pitch, x1 - x0);
|
|
|
|
|
mem_copy(dst + ((xo0 + yo + 3 * column_width) ^ swizzle0), src + x0 + 3 * src_pitch, x1 - x0);
|
|
|
|
|
}
|
2014-12-12 11:28:05 -08:00
|
|
|
|
|
|
|
|
/* Step by spans/columns. As it happens, the swizzle bit flips
|
|
|
|
|
* at each step so we don't need to calculate it explicitly.
|
|
|
|
|
*/
|
|
|
|
|
for (x = x1; x < x2; x += ytile_span) {
|
2018-01-26 16:07:15 -08:00
|
|
|
mem_copy_align16(dst + ((xo + yo + 0 * column_width) ^ swizzle), src + x + 0 * src_pitch, ytile_span);
|
|
|
|
|
mem_copy_align16(dst + ((xo + yo + 1 * column_width) ^ swizzle), src + x + 1 * src_pitch, ytile_span);
|
|
|
|
|
mem_copy_align16(dst + ((xo + yo + 2 * column_width) ^ swizzle), src + x + 2 * src_pitch, ytile_span);
|
|
|
|
|
mem_copy_align16(dst + ((xo + yo + 3 * column_width) ^ swizzle), src + x + 3 * src_pitch, ytile_span);
|
2014-12-12 11:28:05 -08:00
|
|
|
xo += bytes_per_column;
|
|
|
|
|
swizzle ^= swizzle_bit;
|
|
|
|
|
}
|
|
|
|
|
|
2018-01-26 16:07:15 -08:00
|
|
|
if (x2 != x3) {
|
|
|
|
|
mem_copy_align16(dst + ((xo + yo + 0 * column_width) ^ swizzle), src + x2 + 0 * src_pitch, x3 - x2);
|
|
|
|
|
mem_copy_align16(dst + ((xo + yo + 1 * column_width) ^ swizzle), src + x2 + 1 * src_pitch, x3 - x2);
|
|
|
|
|
mem_copy_align16(dst + ((xo + yo + 2 * column_width) ^ swizzle), src + x2 + 2 * src_pitch, x3 - x2);
|
|
|
|
|
mem_copy_align16(dst + ((xo + yo + 3 * column_width) ^ swizzle), src + x2 + 3 * src_pitch, x3 - x2);
|
|
|
|
|
}
|
2014-12-12 11:28:05 -08:00
|
|
|
|
2018-01-26 16:07:15 -08:00
|
|
|
src += 4 * src_pitch;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (y2 != y3) {
|
|
|
|
|
for (yo = y2 * column_width; yo < y3 * column_width; yo += column_width) {
|
|
|
|
|
uint32_t xo = xo1;
|
|
|
|
|
uint32_t swizzle = swizzle1;
|
|
|
|
|
|
|
|
|
|
mem_copy(dst + ((xo0 + yo) ^ swizzle0), src + x0, x1 - x0);
|
|
|
|
|
|
|
|
|
|
/* Step by spans/columns. As it happens, the swizzle bit flips
|
|
|
|
|
* at each step so we don't need to calculate it explicitly.
|
|
|
|
|
*/
|
|
|
|
|
for (x = x1; x < x2; x += ytile_span) {
|
|
|
|
|
mem_copy_align16(dst + ((xo + yo) ^ swizzle), src + x, ytile_span);
|
|
|
|
|
xo += bytes_per_column;
|
|
|
|
|
swizzle ^= swizzle_bit;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mem_copy_align16(dst + ((xo + yo) ^ swizzle), src + x2, x3 - x2);
|
|
|
|
|
|
|
|
|
|
src += src_pitch;
|
|
|
|
|
}
|
2014-12-12 11:28:05 -08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2015-01-03 11:16:08 -08:00
|
|
|
/**
|
|
|
|
|
* Copy texture data from X tile layout to linear.
|
|
|
|
|
*
|
|
|
|
|
* \copydoc tile_copy_fn
|
|
|
|
|
*/
|
|
|
|
|
static inline void
|
|
|
|
|
xtiled_to_linear(uint32_t x0, uint32_t x1, uint32_t x2, uint32_t x3,
|
|
|
|
|
uint32_t y0, uint32_t y1,
|
|
|
|
|
char *dst, const char *src,
|
2015-01-28 03:30:32 -08:00
|
|
|
int32_t dst_pitch,
|
2015-01-03 11:16:08 -08:00
|
|
|
uint32_t swizzle_bit,
|
2018-12-17 14:17:15 +02:00
|
|
|
isl_mem_copy_fn mem_copy,
|
|
|
|
|
isl_mem_copy_fn mem_copy_align16)
|
2015-01-03 11:16:08 -08:00
|
|
|
{
|
|
|
|
|
/* The copy destination offset for each range copied is the sum of
|
|
|
|
|
* an X offset 'x0' or 'xo' and a Y offset 'yo.'
|
|
|
|
|
*/
|
|
|
|
|
uint32_t xo, yo;
|
|
|
|
|
|
2015-01-28 03:30:32 -08:00
|
|
|
dst += (ptrdiff_t)y0 * dst_pitch;
|
2015-01-03 11:16:08 -08:00
|
|
|
|
|
|
|
|
for (yo = y0 * xtile_width; yo < y1 * xtile_width; yo += xtile_width) {
|
|
|
|
|
/* Bits 9 and 10 of the copy destination offset control swizzling.
|
|
|
|
|
* Only 'yo' contributes to those bits in the total offset,
|
|
|
|
|
* so calculate 'swizzle' just once per row.
|
|
|
|
|
* Move bits 9 and 10 three and four places respectively down
|
|
|
|
|
* to bit 6 and xor them.
|
|
|
|
|
*/
|
|
|
|
|
uint32_t swizzle = ((yo >> 3) ^ (yo >> 4)) & swizzle_bit;
|
|
|
|
|
|
|
|
|
|
mem_copy(dst + x0, src + ((x0 + yo) ^ swizzle), x1 - x0);
|
|
|
|
|
|
|
|
|
|
for (xo = x1; xo < x2; xo += xtile_span) {
|
2016-04-07 10:52:28 -07:00
|
|
|
mem_copy_align16(dst + xo, src + ((xo + yo) ^ swizzle), xtile_span);
|
2015-01-03 11:16:08 -08:00
|
|
|
}
|
|
|
|
|
|
2016-04-07 10:52:28 -07:00
|
|
|
mem_copy_align16(dst + x2, src + ((xo + yo) ^ swizzle), x3 - x2);
|
2015-01-03 11:16:08 -08:00
|
|
|
|
|
|
|
|
dst += dst_pitch;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* Copy texture data from Y tile layout to linear.
|
|
|
|
|
*
|
|
|
|
|
* \copydoc tile_copy_fn
|
|
|
|
|
*/
|
|
|
|
|
static inline void
|
|
|
|
|
ytiled_to_linear(uint32_t x0, uint32_t x1, uint32_t x2, uint32_t x3,
|
2018-04-30 10:25:47 -07:00
|
|
|
uint32_t y0, uint32_t y3,
|
2015-01-03 11:16:08 -08:00
|
|
|
char *dst, const char *src,
|
2015-01-28 03:30:32 -08:00
|
|
|
int32_t dst_pitch,
|
2015-01-03 11:16:08 -08:00
|
|
|
uint32_t swizzle_bit,
|
2018-12-17 14:17:15 +02:00
|
|
|
isl_mem_copy_fn mem_copy,
|
|
|
|
|
isl_mem_copy_fn mem_copy_align16)
|
2015-01-03 11:16:08 -08:00
|
|
|
{
|
|
|
|
|
/* Y tiles consist of columns that are 'ytile_span' wide (and the same height
|
|
|
|
|
* as the tile). Thus the destination offset for (x,y) is the sum of:
|
|
|
|
|
* (x % column_width) // position within column
|
|
|
|
|
* (x / column_width) * bytes_per_column // column number * bytes per column
|
|
|
|
|
* y * column_width
|
|
|
|
|
*
|
|
|
|
|
* The copy destination offset for each range copied is the sum of
|
|
|
|
|
* an X offset 'xo0' or 'xo' and a Y offset 'yo.'
|
|
|
|
|
*/
|
|
|
|
|
const uint32_t column_width = ytile_span;
|
|
|
|
|
const uint32_t bytes_per_column = column_width * ytile_height;
|
|
|
|
|
|
2018-04-30 10:25:47 -07:00
|
|
|
uint32_t y1 = MIN2(y3, ALIGN_UP(y0, 4));
|
|
|
|
|
uint32_t y2 = MAX2(y1, ALIGN_DOWN(y3, 4));
|
|
|
|
|
|
2015-01-03 11:16:08 -08:00
|
|
|
uint32_t xo0 = (x0 % ytile_span) + (x0 / ytile_span) * bytes_per_column;
|
|
|
|
|
uint32_t xo1 = (x1 % ytile_span) + (x1 / ytile_span) * bytes_per_column;
|
|
|
|
|
|
|
|
|
|
/* Bit 9 of the destination offset control swizzling.
|
|
|
|
|
* Only the X offset contributes to bit 9 of the total offset,
|
|
|
|
|
* so swizzle can be calculated in advance for these X positions.
|
|
|
|
|
* Move bit 9 three places down to bit 6.
|
|
|
|
|
*/
|
|
|
|
|
uint32_t swizzle0 = (xo0 >> 3) & swizzle_bit;
|
|
|
|
|
uint32_t swizzle1 = (xo1 >> 3) & swizzle_bit;
|
|
|
|
|
|
|
|
|
|
uint32_t x, yo;
|
|
|
|
|
|
2015-01-28 03:30:32 -08:00
|
|
|
dst += (ptrdiff_t)y0 * dst_pitch;
|
2015-01-03 11:16:08 -08:00
|
|
|
|
2018-04-30 10:25:47 -07:00
|
|
|
if (y0 != y1) {
|
|
|
|
|
for (yo = y0 * column_width; yo < y1 * column_width; yo += column_width) {
|
|
|
|
|
uint32_t xo = xo1;
|
|
|
|
|
uint32_t swizzle = swizzle1;
|
|
|
|
|
|
|
|
|
|
mem_copy(dst + x0, src + ((xo0 + yo) ^ swizzle0), x1 - x0);
|
|
|
|
|
|
|
|
|
|
/* Step by spans/columns. As it happens, the swizzle bit flips
|
|
|
|
|
* at each step so we don't need to calculate it explicitly.
|
|
|
|
|
*/
|
|
|
|
|
for (x = x1; x < x2; x += ytile_span) {
|
|
|
|
|
mem_copy_align16(dst + x, src + ((xo + yo) ^ swizzle), ytile_span);
|
|
|
|
|
xo += bytes_per_column;
|
|
|
|
|
swizzle ^= swizzle_bit;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mem_copy_align16(dst + x2, src + ((xo + yo) ^ swizzle), x3 - x2);
|
|
|
|
|
|
|
|
|
|
dst += dst_pitch;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
for (yo = y1 * column_width; yo < y2 * column_width; yo += 4 * column_width) {
|
2015-01-03 11:16:08 -08:00
|
|
|
uint32_t xo = xo1;
|
|
|
|
|
uint32_t swizzle = swizzle1;
|
|
|
|
|
|
2018-04-30 10:25:47 -07:00
|
|
|
if (x0 != x1) {
|
|
|
|
|
mem_copy(dst + x0 + 0 * dst_pitch, src + ((xo0 + yo + 0 * column_width) ^ swizzle0), x1 - x0);
|
|
|
|
|
mem_copy(dst + x0 + 1 * dst_pitch, src + ((xo0 + yo + 1 * column_width) ^ swizzle0), x1 - x0);
|
|
|
|
|
mem_copy(dst + x0 + 2 * dst_pitch, src + ((xo0 + yo + 2 * column_width) ^ swizzle0), x1 - x0);
|
|
|
|
|
mem_copy(dst + x0 + 3 * dst_pitch, src + ((xo0 + yo + 3 * column_width) ^ swizzle0), x1 - x0);
|
|
|
|
|
}
|
2015-01-03 11:16:08 -08:00
|
|
|
|
|
|
|
|
/* Step by spans/columns. As it happens, the swizzle bit flips
|
|
|
|
|
* at each step so we don't need to calculate it explicitly.
|
|
|
|
|
*/
|
|
|
|
|
for (x = x1; x < x2; x += ytile_span) {
|
2018-04-30 10:25:47 -07:00
|
|
|
mem_copy_align16(dst + x + 0 * dst_pitch, src + ((xo + yo + 0 * column_width) ^ swizzle), ytile_span);
|
|
|
|
|
mem_copy_align16(dst + x + 1 * dst_pitch, src + ((xo + yo + 1 * column_width) ^ swizzle), ytile_span);
|
|
|
|
|
mem_copy_align16(dst + x + 2 * dst_pitch, src + ((xo + yo + 2 * column_width) ^ swizzle), ytile_span);
|
|
|
|
|
mem_copy_align16(dst + x + 3 * dst_pitch, src + ((xo + yo + 3 * column_width) ^ swizzle), ytile_span);
|
2015-01-03 11:16:08 -08:00
|
|
|
xo += bytes_per_column;
|
|
|
|
|
swizzle ^= swizzle_bit;
|
|
|
|
|
}
|
|
|
|
|
|
2018-04-30 10:25:47 -07:00
|
|
|
if (x2 != x3) {
|
|
|
|
|
mem_copy_align16(dst + x2 + 0 * dst_pitch, src + ((xo + yo + 0 * column_width) ^ swizzle), x3 - x2);
|
|
|
|
|
mem_copy_align16(dst + x2 + 1 * dst_pitch, src + ((xo + yo + 1 * column_width) ^ swizzle), x3 - x2);
|
|
|
|
|
mem_copy_align16(dst + x2 + 2 * dst_pitch, src + ((xo + yo + 2 * column_width) ^ swizzle), x3 - x2);
|
|
|
|
|
mem_copy_align16(dst + x2 + 3 * dst_pitch, src + ((xo + yo + 3 * column_width) ^ swizzle), x3 - x2);
|
|
|
|
|
}
|
2015-01-03 11:16:08 -08:00
|
|
|
|
2018-04-30 10:25:47 -07:00
|
|
|
dst += 4 * dst_pitch;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (y2 != y3) {
|
|
|
|
|
for (yo = y2 * column_width; yo < y3 * column_width; yo += column_width) {
|
|
|
|
|
uint32_t xo = xo1;
|
|
|
|
|
uint32_t swizzle = swizzle1;
|
|
|
|
|
|
|
|
|
|
mem_copy(dst + x0, src + ((xo0 + yo) ^ swizzle0), x1 - x0);
|
|
|
|
|
|
|
|
|
|
/* Step by spans/columns. As it happens, the swizzle bit flips
|
|
|
|
|
* at each step so we don't need to calculate it explicitly.
|
|
|
|
|
*/
|
|
|
|
|
for (x = x1; x < x2; x += ytile_span) {
|
|
|
|
|
mem_copy_align16(dst + x, src + ((xo + yo) ^ swizzle), ytile_span);
|
|
|
|
|
xo += bytes_per_column;
|
|
|
|
|
swizzle ^= swizzle_bit;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
mem_copy_align16(dst + x2, src + ((xo + yo) ^ swizzle), x3 - x2);
|
|
|
|
|
|
|
|
|
|
dst += dst_pitch;
|
|
|
|
|
}
|
2015-01-03 11:16:08 -08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2018-09-24 08:33:06 +03:00
|
|
|
#if defined(INLINE_SSE41)
|
|
|
|
|
static ALWAYS_INLINE void *
|
|
|
|
|
_memcpy_streaming_load(void *dest, const void *src, size_t count)
|
|
|
|
|
{
|
|
|
|
|
if (count == 16) {
|
|
|
|
|
__m128i val = _mm_stream_load_si128((__m128i *)src);
|
|
|
|
|
_mm_storeu_si128((__m128i *)dest, val);
|
|
|
|
|
return dest;
|
|
|
|
|
} else if (count == 64) {
|
|
|
|
|
__m128i val0 = _mm_stream_load_si128(((__m128i *)src) + 0);
|
|
|
|
|
__m128i val1 = _mm_stream_load_si128(((__m128i *)src) + 1);
|
|
|
|
|
__m128i val2 = _mm_stream_load_si128(((__m128i *)src) + 2);
|
|
|
|
|
__m128i val3 = _mm_stream_load_si128(((__m128i *)src) + 3);
|
|
|
|
|
_mm_storeu_si128(((__m128i *)dest) + 0, val0);
|
|
|
|
|
_mm_storeu_si128(((__m128i *)dest) + 1, val1);
|
|
|
|
|
_mm_storeu_si128(((__m128i *)dest) + 2, val2);
|
|
|
|
|
_mm_storeu_si128(((__m128i *)dest) + 3, val3);
|
|
|
|
|
return dest;
|
|
|
|
|
} else {
|
|
|
|
|
assert(count < 64); /* and (count < 16) for ytiled */
|
|
|
|
|
return memcpy(dest, src, count);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2018-12-17 14:17:15 +02:00
|
|
|
static isl_mem_copy_fn
|
|
|
|
|
choose_copy_function(isl_memcpy_type copy_type)
|
2018-09-19 10:16:58 +03:00
|
|
|
{
|
|
|
|
|
switch(copy_type) {
|
2018-12-17 14:17:15 +02:00
|
|
|
case ISL_MEMCPY:
|
2018-09-19 10:16:58 +03:00
|
|
|
return memcpy;
|
2018-12-17 14:17:15 +02:00
|
|
|
case ISL_MEMCPY_BGRA8:
|
2018-09-19 10:16:58 +03:00
|
|
|
return rgba8_copy;
|
2018-12-17 14:17:15 +02:00
|
|
|
case ISL_MEMCPY_STREAMING_LOAD:
|
2018-11-08 12:55:35 -08:00
|
|
|
#if defined(INLINE_SSE41)
|
2018-09-24 08:33:06 +03:00
|
|
|
return _memcpy_streaming_load;
|
2018-11-08 12:55:35 -08:00
|
|
|
#else
|
2018-12-17 14:17:15 +02:00
|
|
|
unreachable("ISL_MEMCOPY_STREAMING_LOAD requires sse4.1");
|
2018-09-24 08:33:06 +03:00
|
|
|
#endif
|
2018-12-17 14:17:15 +02:00
|
|
|
case ISL_MEMCPY_INVALID:
|
2018-10-28 17:58:05 +00:00
|
|
|
unreachable("invalid copy_type");
|
2018-09-19 10:16:58 +03:00
|
|
|
}
|
2018-10-28 17:58:05 +00:00
|
|
|
unreachable("unhandled copy_type");
|
2018-09-19 10:16:58 +03:00
|
|
|
return NULL;
|
|
|
|
|
}
|
2015-01-03 11:16:08 -08:00
|
|
|
|
2014-12-12 11:28:05 -08:00
|
|
|
/**
|
|
|
|
|
* Copy texture data from linear to X tile layout, faster.
|
|
|
|
|
*
|
|
|
|
|
* Same as \ref linear_to_xtiled but faster, because it passes constant
|
|
|
|
|
* parameters for common cases, allowing the compiler to inline code
|
|
|
|
|
* optimized for those cases.
|
|
|
|
|
*
|
|
|
|
|
* \copydoc tile_copy_fn
|
|
|
|
|
*/
|
|
|
|
|
static FLATTEN void
|
|
|
|
|
linear_to_xtiled_faster(uint32_t x0, uint32_t x1, uint32_t x2, uint32_t x3,
|
|
|
|
|
uint32_t y0, uint32_t y1,
|
|
|
|
|
char *dst, const char *src,
|
2015-01-28 03:30:32 -08:00
|
|
|
int32_t src_pitch,
|
2014-12-12 11:28:05 -08:00
|
|
|
uint32_t swizzle_bit,
|
2018-12-17 14:17:15 +02:00
|
|
|
isl_memcpy_type copy_type)
|
2014-12-12 11:28:05 -08:00
|
|
|
{
|
2018-12-17 14:17:15 +02:00
|
|
|
isl_mem_copy_fn mem_copy = choose_copy_function(copy_type);
|
2018-09-19 10:16:58 +03:00
|
|
|
|
2014-12-12 11:28:05 -08:00
|
|
|
if (x0 == 0 && x3 == xtile_width && y0 == 0 && y1 == xtile_height) {
|
|
|
|
|
if (mem_copy == memcpy)
|
|
|
|
|
return linear_to_xtiled(0, 0, xtile_width, xtile_width, 0, xtile_height,
|
2016-04-07 10:52:28 -07:00
|
|
|
dst, src, src_pitch, swizzle_bit, memcpy, memcpy);
|
2016-04-07 11:21:19 -07:00
|
|
|
else if (mem_copy == rgba8_copy)
|
2014-12-12 11:28:05 -08:00
|
|
|
return linear_to_xtiled(0, 0, xtile_width, xtile_width, 0, xtile_height,
|
2015-03-04 15:21:53 -08:00
|
|
|
dst, src, src_pitch, swizzle_bit,
|
2016-04-07 11:21:19 -07:00
|
|
|
rgba8_copy, rgba8_copy_aligned_dst);
|
2015-03-04 17:27:21 -08:00
|
|
|
else
|
|
|
|
|
unreachable("not reached");
|
2014-12-12 11:28:05 -08:00
|
|
|
} else {
|
|
|
|
|
if (mem_copy == memcpy)
|
|
|
|
|
return linear_to_xtiled(x0, x1, x2, x3, y0, y1,
|
2016-04-07 10:52:28 -07:00
|
|
|
dst, src, src_pitch, swizzle_bit,
|
|
|
|
|
memcpy, memcpy);
|
2016-04-07 11:21:19 -07:00
|
|
|
else if (mem_copy == rgba8_copy)
|
2014-12-12 11:28:05 -08:00
|
|
|
return linear_to_xtiled(x0, x1, x2, x3, y0, y1,
|
2015-03-04 15:21:53 -08:00
|
|
|
dst, src, src_pitch, swizzle_bit,
|
2016-04-07 11:21:19 -07:00
|
|
|
rgba8_copy, rgba8_copy_aligned_dst);
|
2015-03-04 17:27:21 -08:00
|
|
|
else
|
|
|
|
|
unreachable("not reached");
|
2014-12-12 11:28:05 -08:00
|
|
|
}
|
|
|
|
|
linear_to_xtiled(x0, x1, x2, x3, y0, y1,
|
2016-04-07 10:52:28 -07:00
|
|
|
dst, src, src_pitch, swizzle_bit, mem_copy, mem_copy);
|
2014-12-12 11:28:05 -08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* Copy texture data from linear to Y tile layout, faster.
|
|
|
|
|
*
|
|
|
|
|
* Same as \ref linear_to_ytiled but faster, because it passes constant
|
|
|
|
|
* parameters for common cases, allowing the compiler to inline code
|
|
|
|
|
* optimized for those cases.
|
|
|
|
|
*
|
|
|
|
|
* \copydoc tile_copy_fn
|
|
|
|
|
*/
|
|
|
|
|
static FLATTEN void
|
|
|
|
|
linear_to_ytiled_faster(uint32_t x0, uint32_t x1, uint32_t x2, uint32_t x3,
|
|
|
|
|
uint32_t y0, uint32_t y1,
|
|
|
|
|
char *dst, const char *src,
|
2015-01-28 03:30:32 -08:00
|
|
|
int32_t src_pitch,
|
2014-12-12 11:28:05 -08:00
|
|
|
uint32_t swizzle_bit,
|
2018-12-17 14:17:15 +02:00
|
|
|
isl_memcpy_type copy_type)
|
2014-12-12 11:28:05 -08:00
|
|
|
{
|
2018-12-17 14:17:15 +02:00
|
|
|
isl_mem_copy_fn mem_copy = choose_copy_function(copy_type);
|
2018-09-19 10:16:58 +03:00
|
|
|
|
2014-12-12 11:28:05 -08:00
|
|
|
if (x0 == 0 && x3 == ytile_width && y0 == 0 && y1 == ytile_height) {
|
|
|
|
|
if (mem_copy == memcpy)
|
|
|
|
|
return linear_to_ytiled(0, 0, ytile_width, ytile_width, 0, ytile_height,
|
2016-04-07 10:52:28 -07:00
|
|
|
dst, src, src_pitch, swizzle_bit, memcpy, memcpy);
|
2016-04-07 11:21:19 -07:00
|
|
|
else if (mem_copy == rgba8_copy)
|
2014-12-12 11:28:05 -08:00
|
|
|
return linear_to_ytiled(0, 0, ytile_width, ytile_width, 0, ytile_height,
|
2015-03-04 15:21:53 -08:00
|
|
|
dst, src, src_pitch, swizzle_bit,
|
2016-04-07 11:21:19 -07:00
|
|
|
rgba8_copy, rgba8_copy_aligned_dst);
|
2015-03-04 17:27:21 -08:00
|
|
|
else
|
|
|
|
|
unreachable("not reached");
|
2014-12-12 11:28:05 -08:00
|
|
|
} else {
|
|
|
|
|
if (mem_copy == memcpy)
|
|
|
|
|
return linear_to_ytiled(x0, x1, x2, x3, y0, y1,
|
2016-04-07 10:52:28 -07:00
|
|
|
dst, src, src_pitch, swizzle_bit, memcpy, memcpy);
|
2016-04-07 11:21:19 -07:00
|
|
|
else if (mem_copy == rgba8_copy)
|
2014-12-12 11:28:05 -08:00
|
|
|
return linear_to_ytiled(x0, x1, x2, x3, y0, y1,
|
2015-03-04 15:21:53 -08:00
|
|
|
dst, src, src_pitch, swizzle_bit,
|
2016-04-07 11:21:19 -07:00
|
|
|
rgba8_copy, rgba8_copy_aligned_dst);
|
2015-03-04 17:27:21 -08:00
|
|
|
else
|
|
|
|
|
unreachable("not reached");
|
2014-12-12 11:28:05 -08:00
|
|
|
}
|
|
|
|
|
linear_to_ytiled(x0, x1, x2, x3, y0, y1,
|
2016-04-07 10:52:28 -07:00
|
|
|
dst, src, src_pitch, swizzle_bit, mem_copy, mem_copy);
|
2014-12-12 11:28:05 -08:00
|
|
|
}
|
|
|
|
|
|
2015-01-03 11:16:08 -08:00
|
|
|
/**
|
|
|
|
|
* Copy texture data from X tile layout to linear, faster.
|
|
|
|
|
*
|
|
|
|
|
* Same as \ref xtile_to_linear but faster, because it passes constant
|
|
|
|
|
* parameters for common cases, allowing the compiler to inline code
|
|
|
|
|
* optimized for those cases.
|
|
|
|
|
*
|
|
|
|
|
* \copydoc tile_copy_fn
|
|
|
|
|
*/
|
|
|
|
|
static FLATTEN void
|
|
|
|
|
xtiled_to_linear_faster(uint32_t x0, uint32_t x1, uint32_t x2, uint32_t x3,
|
|
|
|
|
uint32_t y0, uint32_t y1,
|
|
|
|
|
char *dst, const char *src,
|
2015-01-28 03:30:32 -08:00
|
|
|
int32_t dst_pitch,
|
2015-01-03 11:16:08 -08:00
|
|
|
uint32_t swizzle_bit,
|
2018-12-17 14:17:15 +02:00
|
|
|
isl_memcpy_type copy_type)
|
2015-01-03 11:16:08 -08:00
|
|
|
{
|
2018-12-17 14:17:15 +02:00
|
|
|
isl_mem_copy_fn mem_copy = choose_copy_function(copy_type);
|
2018-09-19 10:16:58 +03:00
|
|
|
|
2015-01-03 11:16:08 -08:00
|
|
|
if (x0 == 0 && x3 == xtile_width && y0 == 0 && y1 == xtile_height) {
|
|
|
|
|
if (mem_copy == memcpy)
|
|
|
|
|
return xtiled_to_linear(0, 0, xtile_width, xtile_width, 0, xtile_height,
|
2016-04-07 10:52:28 -07:00
|
|
|
dst, src, dst_pitch, swizzle_bit, memcpy, memcpy);
|
2016-04-07 11:21:19 -07:00
|
|
|
else if (mem_copy == rgba8_copy)
|
2015-01-03 11:16:08 -08:00
|
|
|
return xtiled_to_linear(0, 0, xtile_width, xtile_width, 0, xtile_height,
|
2015-03-04 15:21:53 -08:00
|
|
|
dst, src, dst_pitch, swizzle_bit,
|
2016-04-07 11:21:19 -07:00
|
|
|
rgba8_copy, rgba8_copy_aligned_src);
|
2018-09-24 08:33:06 +03:00
|
|
|
#if defined(INLINE_SSE41)
|
|
|
|
|
else if (mem_copy == _memcpy_streaming_load)
|
|
|
|
|
return xtiled_to_linear(0, 0, xtile_width, xtile_width, 0, xtile_height,
|
|
|
|
|
dst, src, dst_pitch, swizzle_bit,
|
|
|
|
|
memcpy, _memcpy_streaming_load);
|
|
|
|
|
#endif
|
2015-03-04 17:27:21 -08:00
|
|
|
else
|
|
|
|
|
unreachable("not reached");
|
2015-01-03 11:16:08 -08:00
|
|
|
} else {
|
|
|
|
|
if (mem_copy == memcpy)
|
|
|
|
|
return xtiled_to_linear(x0, x1, x2, x3, y0, y1,
|
2016-04-07 10:52:28 -07:00
|
|
|
dst, src, dst_pitch, swizzle_bit, memcpy, memcpy);
|
2016-04-07 11:21:19 -07:00
|
|
|
else if (mem_copy == rgba8_copy)
|
2015-01-03 11:16:08 -08:00
|
|
|
return xtiled_to_linear(x0, x1, x2, x3, y0, y1,
|
2015-03-04 15:21:53 -08:00
|
|
|
dst, src, dst_pitch, swizzle_bit,
|
2016-04-07 11:21:19 -07:00
|
|
|
rgba8_copy, rgba8_copy_aligned_src);
|
2018-09-24 08:33:06 +03:00
|
|
|
#if defined(INLINE_SSE41)
|
|
|
|
|
else if (mem_copy == _memcpy_streaming_load)
|
|
|
|
|
return xtiled_to_linear(x0, x1, x2, x3, y0, y1,
|
|
|
|
|
dst, src, dst_pitch, swizzle_bit,
|
|
|
|
|
memcpy, _memcpy_streaming_load);
|
|
|
|
|
#endif
|
2015-03-04 17:27:21 -08:00
|
|
|
else
|
|
|
|
|
unreachable("not reached");
|
2015-01-03 11:16:08 -08:00
|
|
|
}
|
|
|
|
|
xtiled_to_linear(x0, x1, x2, x3, y0, y1,
|
2016-04-07 10:52:28 -07:00
|
|
|
dst, src, dst_pitch, swizzle_bit, mem_copy, mem_copy);
|
2015-01-03 11:16:08 -08:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* Copy texture data from Y tile layout to linear, faster.
|
|
|
|
|
*
|
|
|
|
|
* Same as \ref ytile_to_linear but faster, because it passes constant
|
|
|
|
|
* parameters for common cases, allowing the compiler to inline code
|
|
|
|
|
* optimized for those cases.
|
|
|
|
|
*
|
|
|
|
|
* \copydoc tile_copy_fn
|
|
|
|
|
*/
|
|
|
|
|
static FLATTEN void
|
|
|
|
|
ytiled_to_linear_faster(uint32_t x0, uint32_t x1, uint32_t x2, uint32_t x3,
|
|
|
|
|
uint32_t y0, uint32_t y1,
|
|
|
|
|
char *dst, const char *src,
|
2015-01-28 03:30:32 -08:00
|
|
|
int32_t dst_pitch,
|
2015-01-03 11:16:08 -08:00
|
|
|
uint32_t swizzle_bit,
|
2018-12-17 14:17:15 +02:00
|
|
|
isl_memcpy_type copy_type)
|
2015-01-03 11:16:08 -08:00
|
|
|
{
|
2018-12-17 14:17:15 +02:00
|
|
|
isl_mem_copy_fn mem_copy = choose_copy_function(copy_type);
|
2018-09-19 10:16:58 +03:00
|
|
|
|
2015-01-03 11:16:08 -08:00
|
|
|
if (x0 == 0 && x3 == ytile_width && y0 == 0 && y1 == ytile_height) {
|
|
|
|
|
if (mem_copy == memcpy)
|
|
|
|
|
return ytiled_to_linear(0, 0, ytile_width, ytile_width, 0, ytile_height,
|
2016-04-07 10:52:28 -07:00
|
|
|
dst, src, dst_pitch, swizzle_bit, memcpy, memcpy);
|
2016-04-07 11:21:19 -07:00
|
|
|
else if (mem_copy == rgba8_copy)
|
2015-01-03 11:16:08 -08:00
|
|
|
return ytiled_to_linear(0, 0, ytile_width, ytile_width, 0, ytile_height,
|
2015-03-04 15:21:53 -08:00
|
|
|
dst, src, dst_pitch, swizzle_bit,
|
2016-04-07 11:21:19 -07:00
|
|
|
rgba8_copy, rgba8_copy_aligned_src);
|
2018-09-24 08:33:06 +03:00
|
|
|
#if defined(INLINE_SSE41)
|
2018-12-17 14:17:15 +02:00
|
|
|
else if (copy_type == ISL_MEMCPY_STREAMING_LOAD)
|
2018-09-24 08:33:06 +03:00
|
|
|
return ytiled_to_linear(0, 0, ytile_width, ytile_width, 0, ytile_height,
|
|
|
|
|
dst, src, dst_pitch, swizzle_bit,
|
|
|
|
|
memcpy, _memcpy_streaming_load);
|
|
|
|
|
#endif
|
2015-03-04 17:27:21 -08:00
|
|
|
else
|
|
|
|
|
unreachable("not reached");
|
2015-01-03 11:16:08 -08:00
|
|
|
} else {
|
|
|
|
|
if (mem_copy == memcpy)
|
|
|
|
|
return ytiled_to_linear(x0, x1, x2, x3, y0, y1,
|
2016-04-07 10:52:28 -07:00
|
|
|
dst, src, dst_pitch, swizzle_bit, memcpy, memcpy);
|
2016-04-07 11:21:19 -07:00
|
|
|
else if (mem_copy == rgba8_copy)
|
2015-01-03 11:16:08 -08:00
|
|
|
return ytiled_to_linear(x0, x1, x2, x3, y0, y1,
|
2015-03-04 15:21:53 -08:00
|
|
|
dst, src, dst_pitch, swizzle_bit,
|
2016-04-07 11:21:19 -07:00
|
|
|
rgba8_copy, rgba8_copy_aligned_src);
|
2018-09-24 08:33:06 +03:00
|
|
|
#if defined(INLINE_SSE41)
|
2018-12-17 14:17:15 +02:00
|
|
|
else if (copy_type == ISL_MEMCPY_STREAMING_LOAD)
|
2018-09-24 08:33:06 +03:00
|
|
|
return ytiled_to_linear(x0, x1, x2, x3, y0, y1,
|
|
|
|
|
dst, src, dst_pitch, swizzle_bit,
|
|
|
|
|
memcpy, _memcpy_streaming_load);
|
|
|
|
|
#endif
|
2015-03-04 17:27:21 -08:00
|
|
|
else
|
|
|
|
|
unreachable("not reached");
|
2015-01-03 11:16:08 -08:00
|
|
|
}
|
|
|
|
|
ytiled_to_linear(x0, x1, x2, x3, y0, y1,
|
2016-04-07 10:52:28 -07:00
|
|
|
dst, src, dst_pitch, swizzle_bit, mem_copy, mem_copy);
|
2015-01-03 11:16:08 -08:00
|
|
|
}
|
2014-12-12 11:28:05 -08:00
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* Copy from linear to tiled texture.
|
|
|
|
|
*
|
|
|
|
|
* Divide the region given by X range [xt1, xt2) and Y range [yt1, yt2) into
|
|
|
|
|
* pieces that do not cross tile boundaries and copy each piece with a tile
|
|
|
|
|
* copy function (\ref tile_copy_fn).
|
|
|
|
|
* The X range is in bytes, i.e. pixels * bytes-per-pixel.
|
|
|
|
|
* The Y range is in pixels (i.e. unitless).
|
2018-01-09 23:16:58 -08:00
|
|
|
* 'dst' is the address of (0, 0) in the destination tiled texture.
|
|
|
|
|
* 'src' is the address of (xt1, yt1) in the source linear texture.
|
2014-12-12 11:28:05 -08:00
|
|
|
*/
|
2018-09-24 08:33:06 +03:00
|
|
|
static void
|
2021-03-04 16:25:12 -08:00
|
|
|
linear_to_tiled(uint32_t xt1, uint32_t xt2,
|
2018-09-24 08:33:06 +03:00
|
|
|
uint32_t yt1, uint32_t yt2,
|
|
|
|
|
char *dst, const char *src,
|
|
|
|
|
uint32_t dst_pitch, int32_t src_pitch,
|
|
|
|
|
bool has_swizzling,
|
|
|
|
|
enum isl_tiling tiling,
|
2018-12-17 14:17:15 +02:00
|
|
|
isl_memcpy_type copy_type)
|
2014-12-12 11:28:05 -08:00
|
|
|
{
|
|
|
|
|
tile_copy_fn tile_copy;
|
|
|
|
|
uint32_t xt0, xt3;
|
|
|
|
|
uint32_t yt0, yt3;
|
|
|
|
|
uint32_t xt, yt;
|
|
|
|
|
uint32_t tw, th, span;
|
|
|
|
|
uint32_t swizzle_bit = has_swizzling ? 1<<6 : 0;
|
|
|
|
|
|
2017-06-22 15:17:41 +03:00
|
|
|
if (tiling == ISL_TILING_X) {
|
2014-12-12 11:28:05 -08:00
|
|
|
tw = xtile_width;
|
|
|
|
|
th = xtile_height;
|
|
|
|
|
span = xtile_span;
|
|
|
|
|
tile_copy = linear_to_xtiled_faster;
|
2017-06-22 15:17:41 +03:00
|
|
|
} else if (tiling == ISL_TILING_Y0) {
|
2014-12-12 11:28:05 -08:00
|
|
|
tw = ytile_width;
|
|
|
|
|
th = ytile_height;
|
|
|
|
|
span = ytile_span;
|
|
|
|
|
tile_copy = linear_to_ytiled_faster;
|
|
|
|
|
} else {
|
|
|
|
|
unreachable("unsupported tiling");
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Round out to tile boundaries. */
|
|
|
|
|
xt0 = ALIGN_DOWN(xt1, tw);
|
|
|
|
|
xt3 = ALIGN_UP (xt2, tw);
|
|
|
|
|
yt0 = ALIGN_DOWN(yt1, th);
|
|
|
|
|
yt3 = ALIGN_UP (yt2, th);
|
|
|
|
|
|
|
|
|
|
/* Loop over all tiles to which we have something to copy.
|
|
|
|
|
* 'xt' and 'yt' are the origin of the destination tile, whether copying
|
|
|
|
|
* copying a full or partial tile.
|
|
|
|
|
* tile_copy() copies one tile or partial tile.
|
|
|
|
|
* Looping x inside y is the faster memory access pattern.
|
|
|
|
|
*/
|
|
|
|
|
for (yt = yt0; yt < yt3; yt += th) {
|
|
|
|
|
for (xt = xt0; xt < xt3; xt += tw) {
|
|
|
|
|
/* The area to update is [x0,x3) x [y0,y1).
|
|
|
|
|
* May not want the whole tile, hence the min and max.
|
|
|
|
|
*/
|
|
|
|
|
uint32_t x0 = MAX2(xt1, xt);
|
|
|
|
|
uint32_t y0 = MAX2(yt1, yt);
|
|
|
|
|
uint32_t x3 = MIN2(xt2, xt + tw);
|
|
|
|
|
uint32_t y1 = MIN2(yt2, yt + th);
|
|
|
|
|
|
|
|
|
|
/* [x0,x3) is split into [x0,x1), [x1,x2), [x2,x3) such that
|
|
|
|
|
* the middle interval is the longest span-aligned part.
|
|
|
|
|
* The sub-ranges could be empty.
|
|
|
|
|
*/
|
|
|
|
|
uint32_t x1, x2;
|
|
|
|
|
x1 = ALIGN_UP(x0, span);
|
|
|
|
|
if (x1 > x3)
|
|
|
|
|
x1 = x2 = x3;
|
|
|
|
|
else
|
|
|
|
|
x2 = ALIGN_DOWN(x3, span);
|
|
|
|
|
|
|
|
|
|
assert(x0 <= x1 && x1 <= x2 && x2 <= x3);
|
|
|
|
|
assert(x1 - x0 < span && x3 - x2 < span);
|
|
|
|
|
assert(x3 - x0 <= tw);
|
|
|
|
|
assert((x2 - x1) % span == 0);
|
|
|
|
|
|
|
|
|
|
/* Translate by (xt,yt) for single-tile copier. */
|
|
|
|
|
tile_copy(x0-xt, x1-xt, x2-xt, x3-xt,
|
|
|
|
|
y0-yt, y1-yt,
|
2018-01-09 23:16:58 -08:00
|
|
|
dst + (ptrdiff_t)xt * th + (ptrdiff_t)yt * dst_pitch,
|
|
|
|
|
src + (ptrdiff_t)xt - xt1 + ((ptrdiff_t)yt - yt1) * src_pitch,
|
2014-12-12 11:28:05 -08:00
|
|
|
src_pitch,
|
|
|
|
|
swizzle_bit,
|
2018-09-19 10:16:58 +03:00
|
|
|
copy_type);
|
2014-12-12 11:28:05 -08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2015-01-03 11:16:08 -08:00
|
|
|
/**
|
|
|
|
|
* Copy from tiled to linear texture.
|
|
|
|
|
*
|
|
|
|
|
* Divide the region given by X range [xt1, xt2) and Y range [yt1, yt2) into
|
|
|
|
|
* pieces that do not cross tile boundaries and copy each piece with a tile
|
|
|
|
|
* copy function (\ref tile_copy_fn).
|
|
|
|
|
* The X range is in bytes, i.e. pixels * bytes-per-pixel.
|
|
|
|
|
* The Y range is in pixels (i.e. unitless).
|
2018-01-09 23:16:58 -08:00
|
|
|
* 'dst' is the address of (xt1, yt1) in the destination linear texture.
|
|
|
|
|
* 'src' is the address of (0, 0) in the source tiled texture.
|
2015-01-03 11:16:08 -08:00
|
|
|
*/
|
2018-09-24 08:33:06 +03:00
|
|
|
static void
|
2021-03-04 16:25:12 -08:00
|
|
|
tiled_to_linear(uint32_t xt1, uint32_t xt2,
|
2018-09-24 08:33:06 +03:00
|
|
|
uint32_t yt1, uint32_t yt2,
|
|
|
|
|
char *dst, const char *src,
|
|
|
|
|
int32_t dst_pitch, uint32_t src_pitch,
|
|
|
|
|
bool has_swizzling,
|
|
|
|
|
enum isl_tiling tiling,
|
2018-12-17 14:17:15 +02:00
|
|
|
isl_memcpy_type copy_type)
|
2015-01-03 11:16:08 -08:00
|
|
|
{
|
|
|
|
|
tile_copy_fn tile_copy;
|
|
|
|
|
uint32_t xt0, xt3;
|
|
|
|
|
uint32_t yt0, yt3;
|
|
|
|
|
uint32_t xt, yt;
|
|
|
|
|
uint32_t tw, th, span;
|
|
|
|
|
uint32_t swizzle_bit = has_swizzling ? 1<<6 : 0;
|
|
|
|
|
|
2017-06-22 15:17:41 +03:00
|
|
|
if (tiling == ISL_TILING_X) {
|
2015-01-03 11:16:08 -08:00
|
|
|
tw = xtile_width;
|
|
|
|
|
th = xtile_height;
|
|
|
|
|
span = xtile_span;
|
|
|
|
|
tile_copy = xtiled_to_linear_faster;
|
2017-06-22 15:17:41 +03:00
|
|
|
} else if (tiling == ISL_TILING_Y0) {
|
2015-01-03 11:16:08 -08:00
|
|
|
tw = ytile_width;
|
|
|
|
|
th = ytile_height;
|
|
|
|
|
span = ytile_span;
|
|
|
|
|
tile_copy = ytiled_to_linear_faster;
|
|
|
|
|
} else {
|
|
|
|
|
unreachable("unsupported tiling");
|
|
|
|
|
}
|
|
|
|
|
|
2018-09-24 08:33:06 +03:00
|
|
|
#if defined(INLINE_SSE41)
|
2018-12-17 14:17:15 +02:00
|
|
|
if (copy_type == ISL_MEMCPY_STREAMING_LOAD) {
|
2018-09-24 08:33:06 +03:00
|
|
|
/* The hidden cacheline sized register used by movntdqa can apparently
|
|
|
|
|
* give you stale data, so do an mfence to invalidate it.
|
|
|
|
|
*/
|
|
|
|
|
_mm_mfence();
|
|
|
|
|
}
|
|
|
|
|
#endif
|
|
|
|
|
|
2015-01-03 11:16:08 -08:00
|
|
|
/* Round out to tile boundaries. */
|
|
|
|
|
xt0 = ALIGN_DOWN(xt1, tw);
|
|
|
|
|
xt3 = ALIGN_UP (xt2, tw);
|
|
|
|
|
yt0 = ALIGN_DOWN(yt1, th);
|
|
|
|
|
yt3 = ALIGN_UP (yt2, th);
|
|
|
|
|
|
|
|
|
|
/* Loop over all tiles to which we have something to copy.
|
|
|
|
|
* 'xt' and 'yt' are the origin of the destination tile, whether copying
|
|
|
|
|
* copying a full or partial tile.
|
|
|
|
|
* tile_copy() copies one tile or partial tile.
|
|
|
|
|
* Looping x inside y is the faster memory access pattern.
|
|
|
|
|
*/
|
|
|
|
|
for (yt = yt0; yt < yt3; yt += th) {
|
|
|
|
|
for (xt = xt0; xt < xt3; xt += tw) {
|
|
|
|
|
/* The area to update is [x0,x3) x [y0,y1).
|
|
|
|
|
* May not want the whole tile, hence the min and max.
|
|
|
|
|
*/
|
|
|
|
|
uint32_t x0 = MAX2(xt1, xt);
|
|
|
|
|
uint32_t y0 = MAX2(yt1, yt);
|
|
|
|
|
uint32_t x3 = MIN2(xt2, xt + tw);
|
|
|
|
|
uint32_t y1 = MIN2(yt2, yt + th);
|
|
|
|
|
|
|
|
|
|
/* [x0,x3) is split into [x0,x1), [x1,x2), [x2,x3) such that
|
|
|
|
|
* the middle interval is the longest span-aligned part.
|
|
|
|
|
* The sub-ranges could be empty.
|
|
|
|
|
*/
|
|
|
|
|
uint32_t x1, x2;
|
|
|
|
|
x1 = ALIGN_UP(x0, span);
|
|
|
|
|
if (x1 > x3)
|
|
|
|
|
x1 = x2 = x3;
|
|
|
|
|
else
|
|
|
|
|
x2 = ALIGN_DOWN(x3, span);
|
|
|
|
|
|
|
|
|
|
assert(x0 <= x1 && x1 <= x2 && x2 <= x3);
|
|
|
|
|
assert(x1 - x0 < span && x3 - x2 < span);
|
|
|
|
|
assert(x3 - x0 <= tw);
|
|
|
|
|
assert((x2 - x1) % span == 0);
|
|
|
|
|
|
|
|
|
|
/* Translate by (xt,yt) for single-tile copier. */
|
|
|
|
|
tile_copy(x0-xt, x1-xt, x2-xt, x3-xt,
|
|
|
|
|
y0-yt, y1-yt,
|
2018-01-09 23:16:58 -08:00
|
|
|
dst + (ptrdiff_t)xt - xt1 + ((ptrdiff_t)yt - yt1) * dst_pitch,
|
|
|
|
|
src + (ptrdiff_t)xt * th + (ptrdiff_t)yt * src_pitch,
|
2015-01-03 11:16:08 -08:00
|
|
|
dst_pitch,
|
|
|
|
|
swizzle_bit,
|
2018-09-19 10:16:58 +03:00
|
|
|
copy_type);
|
2015-01-03 11:16:08 -08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|