2020-02-14 11:32:18 +00:00
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/*
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* Copyright © 2020 Valve Corporation
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*
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2024-04-08 09:02:30 +02:00
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* SPDX-License-Identifier: MIT
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2020-02-14 11:32:18 +00:00
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*/
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aco/isel: track control flow divergence in loops more accurately
We introduce two new variables, cf_context::in_divergent_cf and
cf_context::parent_loop.has_divergent_break, in order to determine
whether there is any other invocations on a different CF path.
Totals from 1305 (1.64% of 79395) affected shaders: (Navi31)
Instrs: 659211 -> 657815 (-0.21%); split: -0.22%, +0.01%
CodeSize: 3483228 -> 3477960 (-0.15%); split: -0.16%, +0.01%
VGPRs: 68820 -> 48048 (-30.18%)
Latency: 14197750 -> 14170767 (-0.19%); split: -0.26%, +0.07%
InvThroughput: 1619103 -> 1619826 (+0.04%); split: -0.02%, +0.07%
VClause: 12384 -> 12350 (-0.27%)
SClause: 26693 -> 26844 (+0.57%); split: -0.01%, +0.57%
Copies: 44994 -> 43535 (-3.24%); split: -3.26%, +0.02%
PreSGPRs: 49007 -> 48907 (-0.20%)
PreVGPRs: 32171 -> 32121 (-0.16%)
VALU: 349984 -> 349857 (-0.04%); split: -0.04%, +0.00%
SALU: 84252 -> 83988 (-0.31%); split: -0.32%, +0.00%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33206>
2025-01-24 12:32:47 +01:00
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#include "nir_builder.h"
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2021-03-18 19:14:24 +00:00
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#include <llvm/Config/llvm-config.h>
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2023-05-26 12:55:35 +01:00
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2020-02-14 11:32:18 +00:00
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#include "helpers.h"
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#include "test_isel-spirv.h"
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using namespace aco;
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BEGIN_TEST(isel.interp.simple)
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QoShaderModuleCreateInfo vs = qoShaderModuleCreateInfoGLSL(VERTEX,
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layout(location = 0) in vec4 in_color;
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layout(location = 0) out vec4 out_color;
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void main() { out_color = in_color;
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}
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);
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QoShaderModuleCreateInfo fs = qoShaderModuleCreateInfoGLSL(FRAGMENT,
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layout(location = 0) in vec4 in_color;
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layout(location = 0) out vec4 out_color;
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void main() {
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radv: eliminate unused FS output channels
For formats that don't have all color channels, there is no reason to
output all of them.
Games often write to R only or RGB formats with non trivial remaining channels.
Foz-DB Navi21:
Totals from 10270 (10.55% of 97347) affected shaders:
MaxWaves: 249166 -> 250950 (+0.72%); split: +0.73%, -0.01%
Instrs: 8442016 -> 8354715 (-1.03%); split: -1.05%, +0.01%
CodeSize: 45939644 -> 45487156 (-0.98%); split: -1.01%, +0.02%
VGPRs: 472584 -> 463784 (-1.86%); split: -1.98%, +0.12%
SpillSGPRs: 1502 -> 1448 (-3.60%)
LDS: 6024192 -> 6011904 (-0.20%)
Inputs: 42463 -> 41773 (-1.62%)
Outputs: 24601 -> 23955 (-2.63%)
Latency: 78011745 -> 77653907 (-0.46%); split: -0.56%, +0.10%
InvThroughput: 19767826 -> 19274046 (-2.50%); split: -2.53%, +0.03%
VClause: 177891 -> 176681 (-0.68%); split: -0.80%, +0.12%
SClause: 236784 -> 235324 (-0.62%); split: -0.72%, +0.10%
Copies: 621048 -> 616096 (-0.80%); split: -1.03%, +0.23%
Branches: 202608 -> 201811 (-0.39%); split: -0.44%, +0.05%
PreSGPRs: 441032 -> 437698 (-0.76%); split: -0.77%, +0.01%
PreVGPRs: 378067 -> 369564 (-2.25%); split: -2.26%, +0.01%
VALU: 5906415 -> 5833179 (-1.24%); split: -1.25%, +0.01%
SALU: 973428 -> 968088 (-0.55%); split: -0.61%, +0.06%
VMEM: 298277 -> 296504 (-0.59%); split: -0.61%, +0.01%
SMEM: 402244 -> 399612 (-0.65%); split: -0.71%, +0.06%
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38853>
2025-12-07 18:22:15 +01:00
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//>> v1: %a_tmp = v_interp_p1_f32 %bx, %pm:m0 attr0.w
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2021-04-20 17:35:41 +01:00
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//! v1: %a = v_interp_p2_f32 %by, %pm:m0, (kill)%a_tmp attr0.w
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2020-01-31 17:44:19 +01:00
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//! v1: %r_tmp = v_interp_p1_f32 %bx, %pm:m0 attr0.x
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//! v1: %r = v_interp_p2_f32 %by, %pm:m0, (kill)%r_tmp attr0.x
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radv: eliminate unused FS output channels
For formats that don't have all color channels, there is no reason to
output all of them.
Games often write to R only or RGB formats with non trivial remaining channels.
Foz-DB Navi21:
Totals from 10270 (10.55% of 97347) affected shaders:
MaxWaves: 249166 -> 250950 (+0.72%); split: +0.73%, -0.01%
Instrs: 8442016 -> 8354715 (-1.03%); split: -1.05%, +0.01%
CodeSize: 45939644 -> 45487156 (-0.98%); split: -1.01%, +0.02%
VGPRs: 472584 -> 463784 (-1.86%); split: -1.98%, +0.12%
SpillSGPRs: 1502 -> 1448 (-3.60%)
LDS: 6024192 -> 6011904 (-0.20%)
Inputs: 42463 -> 41773 (-1.62%)
Outputs: 24601 -> 23955 (-2.63%)
Latency: 78011745 -> 77653907 (-0.46%); split: -0.56%, +0.10%
InvThroughput: 19767826 -> 19274046 (-2.50%); split: -2.53%, +0.03%
VClause: 177891 -> 176681 (-0.68%); split: -0.80%, +0.12%
SClause: 236784 -> 235324 (-0.62%); split: -0.72%, +0.10%
Copies: 621048 -> 616096 (-0.80%); split: -1.03%, +0.23%
Branches: 202608 -> 201811 (-0.39%); split: -0.44%, +0.05%
PreSGPRs: 441032 -> 437698 (-0.76%); split: -0.77%, +0.01%
PreVGPRs: 378067 -> 369564 (-2.25%); split: -2.26%, +0.01%
VALU: 5906415 -> 5833179 (-1.24%); split: -1.25%, +0.01%
SALU: 973428 -> 968088 (-0.55%); split: -0.61%, +0.06%
VMEM: 298277 -> 296504 (-0.59%); split: -0.61%, +0.01%
SMEM: 402244 -> 399612 (-0.65%); split: -0.71%, +0.06%
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38853>
2025-12-07 18:22:15 +01:00
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//! v1: %g_tmp = v_interp_p1_f32 %bx, %pm:m0 attr0.y
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//! v1: %g = v_interp_p2_f32 %by, %pm:m0, (kill)%g_tmp attr0.y
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//! v1: %b_tmp = v_interp_p1_f32 (kill)%bx, %pm:m0 attr0.z
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//! v1: %b = v_interp_p2_f32 (kill)%by, (kill)%pm:m0, (kill)%b_tmp attr0.z
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2021-04-20 17:35:41 +01:00
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//! exp (kill)%r, (kill)%g, (kill)%b, (kill)%a mrt0
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2020-02-14 11:32:18 +00:00
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out_color = in_color;
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}
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);
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2020-11-06 12:41:35 +01:00
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PipelineBuilder pbld(get_vk_device(GFX9));
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pbld.add_vsfs(vs, fs);
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pbld.print_ir(VK_SHADER_STAGE_FRAGMENT_BIT, "ACO IR");
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2020-02-14 11:32:18 +00:00
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END_TEST
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BEGIN_TEST(isel.compute.simple)
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for (unsigned i = GFX7; i <= GFX8; i++) {
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2022-05-12 02:50:17 -04:00
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if (!set_variant((amd_gfx_level)i))
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2020-02-14 11:32:18 +00:00
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continue;
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QoShaderModuleCreateInfo cs = qoShaderModuleCreateInfoGLSL(COMPUTE,
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layout(local_size_x=1) in;
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layout(binding=0) buffer Buf {
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uint res;
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};
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void main() {
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2020-07-30 19:44:28 +01:00
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//>> v1: %data = p_parallelcopy 42
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2025-07-06 20:54:49 +02:00
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//! buffer_store_dword (kill)%_, v1: undef, 0, (kill)%data storage:buffer
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2020-02-14 11:32:18 +00:00
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res = 42;
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}
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);
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2022-05-12 02:50:17 -04:00
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PipelineBuilder pbld(get_vk_device((amd_gfx_level)i));
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2020-11-06 12:41:35 +01:00
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pbld.add_cs(cs);
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pbld.print_ir(VK_SHADER_STAGE_COMPUTE_BIT, "ACO IR", true);
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2020-02-14 11:32:18 +00:00
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}
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END_TEST
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2020-11-12 14:21:00 +00:00
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BEGIN_TEST(isel.gs.no_outputs)
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for (unsigned i = GFX8; i <= GFX10; i++) {
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2022-05-12 02:50:17 -04:00
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if (!set_variant((amd_gfx_level)i))
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2020-11-12 14:21:00 +00:00
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continue;
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QoShaderModuleCreateInfo vs = qoShaderModuleCreateInfoGLSL(VERTEX,
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void main() {}
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);
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QoShaderModuleCreateInfo gs = qoShaderModuleCreateInfoGLSL(GEOMETRY,
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layout(points) in;
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layout(points, max_vertices = 1) out;
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void main() {
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EmitVertex();
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EndPrimitive();
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}
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);
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2022-05-12 02:50:17 -04:00
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PipelineBuilder pbld(get_vk_device((amd_gfx_level)i));
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2020-11-12 14:21:00 +00:00
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pbld.add_stage(VK_SHADER_STAGE_VERTEX_BIT, vs);
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pbld.add_stage(VK_SHADER_STAGE_GEOMETRY_BIT, gs);
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pbld.create_pipeline();
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//! success
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fprintf(output, "success\n");
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}
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END_TEST
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2020-11-12 14:32:57 +00:00
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BEGIN_TEST(isel.gs.no_verts)
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for (unsigned i = GFX8; i <= GFX10; i++) {
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2022-05-12 02:50:17 -04:00
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if (!set_variant((amd_gfx_level)i))
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2020-11-12 14:32:57 +00:00
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continue;
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QoShaderModuleCreateInfo vs = qoShaderModuleCreateInfoGLSL(VERTEX,
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void main() {}
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);
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QoShaderModuleCreateInfo gs = qoShaderModuleCreateInfoGLSL(GEOMETRY,
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layout(points) in;
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layout(points, max_vertices = 0) out;
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void main() {}
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);
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2022-05-12 02:50:17 -04:00
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PipelineBuilder pbld(get_vk_device((amd_gfx_level)i));
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2020-11-12 14:32:57 +00:00
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pbld.add_stage(VK_SHADER_STAGE_VERTEX_BIT, vs);
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pbld.add_stage(VK_SHADER_STAGE_GEOMETRY_BIT, gs);
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pbld.create_pipeline();
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//! success
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fprintf(output, "success\n");
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}
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END_TEST
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2020-11-23 12:51:15 +00:00
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BEGIN_TEST(isel.sparse.clause)
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2021-05-19 14:36:43 +01:00
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for (unsigned i = GFX10_3; i <= GFX10_3; i++) {
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2022-05-12 02:50:17 -04:00
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if (!set_variant((amd_gfx_level)i))
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2020-11-23 12:51:15 +00:00
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continue;
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QoShaderModuleCreateInfo cs = qoShaderModuleCreateInfoGLSL(COMPUTE,
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QO_EXTENSION GL_ARB_sparse_texture2 : require
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layout(local_size_x=1) in;
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layout(binding=0) uniform sampler2D tex;
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radv,aco: use nir_address_format_vec2_index_32bit_offset
The vec2 index helps the compiler make use of SMEM's SOFFSET field when
loading descriptors.
fossil-db (GFX10.3):
Totals from 126326 (86.37% of 146267) affected shaders:
VGPRs: 4898704 -> 4899088 (+0.01%); split: -0.02%, +0.03%
SpillSGPRs: 13490 -> 14404 (+6.78%); split: -1.10%, +7.87%
CodeSize: 306442996 -> 302277700 (-1.36%); split: -1.36%, +0.01%
MaxWaves: 3277108 -> 3276624 (-0.01%); split: +0.01%, -0.02%
Instrs: 58301101 -> 57469370 (-1.43%); split: -1.43%, +0.01%
VClause: 1208270 -> 1199264 (-0.75%); split: -1.02%, +0.28%
SClause: 2517691 -> 2432744 (-3.37%); split: -3.75%, +0.38%
Copies: 3518643 -> 3161097 (-10.16%); split: -10.45%, +0.29%
Branches: 1228383 -> 1228254 (-0.01%); split: -0.12%, +0.11%
PreSGPRs: 3973880 -> 4031099 (+1.44%); split: -0.19%, +1.63%
PreVGPRs: 3831599 -> 3831707 (+0.00%)
Cycles: 1785250712 -> 1778222316 (-0.39%); split: -0.42%, +0.03%
VMEM: 52873776 -> 50663317 (-4.18%); split: +0.18%, -4.36%
SMEM: 8534270 -> 8361666 (-2.02%); split: +1.79%, -3.82%
Signed-off-by: Rhys Perry <pendingchaos02@gmail.com>
Reviewed-by: Samuel Pitoiset <samuel.pitoiset@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/9523>
2021-03-10 15:47:40 +00:00
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layout(binding=1) buffer Buf {
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2020-11-23 12:51:15 +00:00
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vec4 res[4];
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uint code[4];
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};
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void main() {
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//>> v5: (noCSE)%zero0 = p_create_vector 0, 0, 0, 0, 0
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radv: always run nir_opt_16bit_tex_image
The pass can optimize pack_half and constants sources even when
no 16bit instructions exist.
Foz-DB Navi21:
Totals from 3042 (3.83% of 79395) affected shaders:
MaxWaves: 69039 -> 69031 (-0.01%); split: +0.01%, -0.02%
Instrs: 2292054 -> 2291874 (-0.01%); split: -0.03%, +0.02%
CodeSize: 12567868 -> 12544888 (-0.18%); split: -0.23%, +0.05%
VGPRs: 145384 -> 145352 (-0.02%); split: -0.06%, +0.04%
SpillSGPRs: 451 -> 452 (+0.22%)
Latency: 23546543 -> 23536416 (-0.04%); split: -0.07%, +0.03%
InvThroughput: 5180446 -> 5164437 (-0.31%); split: -0.35%, +0.04%
VClause: 50537 -> 50535 (-0.00%); split: -0.05%, +0.04%
SClause: 84726 -> 84750 (+0.03%); split: -0.04%, +0.06%
Copies: 140384 -> 140421 (+0.03%); split: -0.34%, +0.37%
Branches: 40412 -> 40413 (+0.00%)
PreVGPRs: 120213 -> 120262 (+0.04%); split: -0.03%, +0.07%
VALU: 1607545 -> 1607593 (+0.00%); split: -0.03%, +0.03%
SALU: 215846 -> 215837 (-0.00%); split: -0.03%, +0.02%
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28730>
2024-04-13 16:27:55 +02:00
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//>> v5: %_ = image_sample_lz_o %_, %_, (kill)%zero0, (kill)%_, %_ dmask:xyzw 2d tfe a16
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2020-11-23 12:51:15 +00:00
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//>> v5: (noCSE)%zero1 = p_create_vector 0, 0, 0, 0, 0
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radv: always run nir_opt_16bit_tex_image
The pass can optimize pack_half and constants sources even when
no 16bit instructions exist.
Foz-DB Navi21:
Totals from 3042 (3.83% of 79395) affected shaders:
MaxWaves: 69039 -> 69031 (-0.01%); split: +0.01%, -0.02%
Instrs: 2292054 -> 2291874 (-0.01%); split: -0.03%, +0.02%
CodeSize: 12567868 -> 12544888 (-0.18%); split: -0.23%, +0.05%
VGPRs: 145384 -> 145352 (-0.02%); split: -0.06%, +0.04%
SpillSGPRs: 451 -> 452 (+0.22%)
Latency: 23546543 -> 23536416 (-0.04%); split: -0.07%, +0.03%
InvThroughput: 5180446 -> 5164437 (-0.31%); split: -0.35%, +0.04%
VClause: 50537 -> 50535 (-0.00%); split: -0.05%, +0.04%
SClause: 84726 -> 84750 (+0.03%); split: -0.04%, +0.06%
Copies: 140384 -> 140421 (+0.03%); split: -0.34%, +0.37%
Branches: 40412 -> 40413 (+0.00%)
PreVGPRs: 120213 -> 120262 (+0.04%); split: -0.03%, +0.07%
VALU: 1607545 -> 1607593 (+0.00%); split: -0.03%, +0.03%
SALU: 215846 -> 215837 (-0.00%); split: -0.03%, +0.02%
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28730>
2024-04-13 16:27:55 +02:00
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//>> v5: %_ = image_sample_lz_o %_, %_, (kill)%zero1, (kill)%_, %_ dmask:xyzw 2d tfe a16
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2020-11-23 12:51:15 +00:00
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//>> v5: (noCSE)%zero2 = p_create_vector 0, 0, 0, 0, 0
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radv: always run nir_opt_16bit_tex_image
The pass can optimize pack_half and constants sources even when
no 16bit instructions exist.
Foz-DB Navi21:
Totals from 3042 (3.83% of 79395) affected shaders:
MaxWaves: 69039 -> 69031 (-0.01%); split: +0.01%, -0.02%
Instrs: 2292054 -> 2291874 (-0.01%); split: -0.03%, +0.02%
CodeSize: 12567868 -> 12544888 (-0.18%); split: -0.23%, +0.05%
VGPRs: 145384 -> 145352 (-0.02%); split: -0.06%, +0.04%
SpillSGPRs: 451 -> 452 (+0.22%)
Latency: 23546543 -> 23536416 (-0.04%); split: -0.07%, +0.03%
InvThroughput: 5180446 -> 5164437 (-0.31%); split: -0.35%, +0.04%
VClause: 50537 -> 50535 (-0.00%); split: -0.05%, +0.04%
SClause: 84726 -> 84750 (+0.03%); split: -0.04%, +0.06%
Copies: 140384 -> 140421 (+0.03%); split: -0.34%, +0.37%
Branches: 40412 -> 40413 (+0.00%)
PreVGPRs: 120213 -> 120262 (+0.04%); split: -0.03%, +0.07%
VALU: 1607545 -> 1607593 (+0.00%); split: -0.03%, +0.03%
SALU: 215846 -> 215837 (-0.00%); split: -0.03%, +0.02%
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28730>
2024-04-13 16:27:55 +02:00
|
|
|
//>> v5: %_ = image_sample_lz_o %_, %_, (kill)%zero2, (kill)%_, %_ dmask:xyzw 2d tfe a16
|
2020-11-23 12:51:15 +00:00
|
|
|
//>> v5: (noCSE)%zero3 = p_create_vector 0, 0, 0, 0, 0
|
radv: always run nir_opt_16bit_tex_image
The pass can optimize pack_half and constants sources even when
no 16bit instructions exist.
Foz-DB Navi21:
Totals from 3042 (3.83% of 79395) affected shaders:
MaxWaves: 69039 -> 69031 (-0.01%); split: +0.01%, -0.02%
Instrs: 2292054 -> 2291874 (-0.01%); split: -0.03%, +0.02%
CodeSize: 12567868 -> 12544888 (-0.18%); split: -0.23%, +0.05%
VGPRs: 145384 -> 145352 (-0.02%); split: -0.06%, +0.04%
SpillSGPRs: 451 -> 452 (+0.22%)
Latency: 23546543 -> 23536416 (-0.04%); split: -0.07%, +0.03%
InvThroughput: 5180446 -> 5164437 (-0.31%); split: -0.35%, +0.04%
VClause: 50537 -> 50535 (-0.00%); split: -0.05%, +0.04%
SClause: 84726 -> 84750 (+0.03%); split: -0.04%, +0.06%
Copies: 140384 -> 140421 (+0.03%); split: -0.34%, +0.37%
Branches: 40412 -> 40413 (+0.00%)
PreVGPRs: 120213 -> 120262 (+0.04%); split: -0.03%, +0.07%
VALU: 1607545 -> 1607593 (+0.00%); split: -0.03%, +0.03%
SALU: 215846 -> 215837 (-0.00%); split: -0.03%, +0.02%
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28730>
2024-04-13 16:27:55 +02:00
|
|
|
//>> v5: %_ = image_sample_lz_o (kill)%_, (kill)%_, (kill)%zero3, (kill)%_, (kill)%_ dmask:xyzw 2d tfe a16
|
2020-11-23 12:51:15 +00:00
|
|
|
//>> s_clause 0x3
|
radv: always run nir_opt_16bit_tex_image
The pass can optimize pack_half and constants sources even when
no 16bit instructions exist.
Foz-DB Navi21:
Totals from 3042 (3.83% of 79395) affected shaders:
MaxWaves: 69039 -> 69031 (-0.01%); split: +0.01%, -0.02%
Instrs: 2292054 -> 2291874 (-0.01%); split: -0.03%, +0.02%
CodeSize: 12567868 -> 12544888 (-0.18%); split: -0.23%, +0.05%
VGPRs: 145384 -> 145352 (-0.02%); split: -0.06%, +0.04%
SpillSGPRs: 451 -> 452 (+0.22%)
Latency: 23546543 -> 23536416 (-0.04%); split: -0.07%, +0.03%
InvThroughput: 5180446 -> 5164437 (-0.31%); split: -0.35%, +0.04%
VClause: 50537 -> 50535 (-0.00%); split: -0.05%, +0.04%
SClause: 84726 -> 84750 (+0.03%); split: -0.04%, +0.06%
Copies: 140384 -> 140421 (+0.03%); split: -0.34%, +0.37%
Branches: 40412 -> 40413 (+0.00%)
PreVGPRs: 120213 -> 120262 (+0.04%); split: -0.03%, +0.07%
VALU: 1607545 -> 1607593 (+0.00%); split: -0.03%, +0.03%
SALU: 215846 -> 215837 (-0.00%); split: -0.03%, +0.02%
Reviewed-by: Alyssa Rosenzweig <alyssa@rosenzweig.io>
Reviewed-by: Rhys Perry <pendingchaos02@gmail.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28730>
2024-04-13 16:27:55 +02:00
|
|
|
//! image_sample_lz_o v[#_:#_], v[#_:#_], @s256(img), @s128(samp) dmask:0xf dim:SQ_RSRC_IMG_2D a16 tfe
|
|
|
|
|
//! image_sample_lz_o v[#_:#_], [v#_, v#_], @s256(img), @s128(samp) dmask:0xf dim:SQ_RSRC_IMG_2D a16 tfe
|
|
|
|
|
//! image_sample_lz_o v[#_:#_], [v#_, v#_], @s256(img), @s128(samp) dmask:0xf dim:SQ_RSRC_IMG_2D a16 tfe
|
|
|
|
|
//! image_sample_lz_o v[#_:#_], [v#_, v#_], @s256(img), @s128(samp) dmask:0xf dim:SQ_RSRC_IMG_2D a16 tfe
|
2020-11-23 12:51:15 +00:00
|
|
|
code[0] = sparseTextureOffsetARB(tex, vec2(0.5), ivec2(1, 0), res[0]);
|
|
|
|
|
code[1] = sparseTextureOffsetARB(tex, vec2(0.5), ivec2(2, 0), res[1]);
|
|
|
|
|
code[2] = sparseTextureOffsetARB(tex, vec2(0.5), ivec2(3, 0), res[2]);
|
|
|
|
|
code[3] = sparseTextureOffsetARB(tex, vec2(0.5), ivec2(4, 0), res[3]);
|
|
|
|
|
}
|
|
|
|
|
);
|
|
|
|
|
|
2022-05-12 02:50:17 -04:00
|
|
|
PipelineBuilder pbld(get_vk_device((amd_gfx_level)i));
|
2020-11-23 12:51:15 +00:00
|
|
|
pbld.add_cs(cs);
|
|
|
|
|
pbld.print_ir(VK_SHADER_STAGE_COMPUTE_BIT, "ACO IR", true);
|
|
|
|
|
pbld.print_ir(VK_SHADER_STAGE_COMPUTE_BIT, "Assembly", true);
|
|
|
|
|
}
|
|
|
|
|
END_TEST
|
2023-06-02 13:36:55 +01:00
|
|
|
|
|
|
|
|
BEGIN_TEST(isel.discard_early_exit.mrtz)
|
|
|
|
|
QoShaderModuleCreateInfo vs = qoShaderModuleCreateInfoGLSL(VERTEX,
|
|
|
|
|
void main() {}
|
|
|
|
|
);
|
|
|
|
|
QoShaderModuleCreateInfo fs = qoShaderModuleCreateInfoGLSL(FRAGMENT,
|
|
|
|
|
void main() {
|
|
|
|
|
if (gl_FragCoord.w > 0.5)
|
|
|
|
|
discard;
|
|
|
|
|
gl_FragDepth = 1.0 / gl_FragCoord.z;
|
|
|
|
|
}
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
/* On GFX11, the discard early exit must use mrtz if the shader exports only depth. */
|
aco/ra: re-use registers from killed operands
Totals from 77283 (97.34% of 79395) affected shaders: (GFX11)
MaxWaves: 2348498 -> 2348250 (-0.01%); split: +0.01%, -0.02%
Instrs: 45304558 -> 45097367 (-0.46%); split: -0.57%, +0.11%
CodeSize: 235719656 -> 234957768 (-0.32%); split: -0.43%, +0.11%
VGPRs: 3065984 -> 3073244 (+0.24%); split: -0.41%, +0.65%
Latency: 308010576 -> 307008565 (-0.33%); split: -0.85%, +0.52%
InvThroughput: 49560307 -> 49464214 (-0.19%); split: -0.54%, +0.34%
VClause: 881895 -> 879739 (-0.24%); split: -0.78%, +0.53%
SClause: 1388139 -> 1374634 (-0.97%); split: -1.12%, +0.14%
Copies: 2918583 -> 2910434 (-0.28%); split: -1.92%, +1.64%
Branches: 893947 -> 893712 (-0.03%); split: -0.06%, +0.03%
VALU: 25260728 -> 25256766 (-0.02%); split: -0.20%, +0.19%
SALU: 4377750 -> 4373595 (-0.09%); split: -0.17%, +0.07%
VOPD: 8603 -> 9163 (+6.51%); split: +8.54%, -2.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29235>
2024-04-19 11:55:28 +02:00
|
|
|
//>> exp mrtz v#_, off, off, off done ; $_ $_
|
2024-04-08 15:10:39 +01:00
|
|
|
//! s_endpgm ; $_
|
2023-06-02 13:36:55 +01:00
|
|
|
//! BB1:
|
2024-04-08 15:10:39 +01:00
|
|
|
//! exp mrtz off, off, off, off done ; $_ $_
|
|
|
|
|
//! s_endpgm ; $_
|
2023-06-02 13:36:55 +01:00
|
|
|
|
|
|
|
|
PipelineBuilder pbld(get_vk_device(GFX11));
|
|
|
|
|
pbld.add_vsfs(vs, fs);
|
|
|
|
|
pbld.print_ir(VK_SHADER_STAGE_FRAGMENT_BIT, "Assembly");
|
|
|
|
|
END_TEST
|
|
|
|
|
|
|
|
|
|
BEGIN_TEST(isel.discard_early_exit.mrt0)
|
|
|
|
|
QoShaderModuleCreateInfo vs = qoShaderModuleCreateInfoGLSL(VERTEX,
|
|
|
|
|
void main() {}
|
|
|
|
|
);
|
|
|
|
|
QoShaderModuleCreateInfo fs = qoShaderModuleCreateInfoGLSL(FRAGMENT,
|
|
|
|
|
layout(location = 0) out vec4 out_color;
|
|
|
|
|
void main() {
|
|
|
|
|
if (gl_FragCoord.w > 0.5)
|
|
|
|
|
discard;
|
|
|
|
|
out_color = vec4(1.0 / gl_FragCoord.z);
|
|
|
|
|
}
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
/* On GFX11, the discard early exit must use mrt0 if the shader exports color. */
|
aco/ra: re-use registers from killed operands
Totals from 77283 (97.34% of 79395) affected shaders: (GFX11)
MaxWaves: 2348498 -> 2348250 (-0.01%); split: +0.01%, -0.02%
Instrs: 45304558 -> 45097367 (-0.46%); split: -0.57%, +0.11%
CodeSize: 235719656 -> 234957768 (-0.32%); split: -0.43%, +0.11%
VGPRs: 3065984 -> 3073244 (+0.24%); split: -0.41%, +0.65%
Latency: 308010576 -> 307008565 (-0.33%); split: -0.85%, +0.52%
InvThroughput: 49560307 -> 49464214 (-0.19%); split: -0.54%, +0.34%
VClause: 881895 -> 879739 (-0.24%); split: -0.78%, +0.53%
SClause: 1388139 -> 1374634 (-0.97%); split: -1.12%, +0.14%
Copies: 2918583 -> 2910434 (-0.28%); split: -1.92%, +1.64%
Branches: 893947 -> 893712 (-0.03%); split: -0.06%, +0.03%
VALU: 25260728 -> 25256766 (-0.02%); split: -0.20%, +0.19%
SALU: 4377750 -> 4373595 (-0.09%); split: -0.17%, +0.07%
VOPD: 8603 -> 9163 (+6.51%); split: +8.54%, -2.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29235>
2024-04-19 11:55:28 +02:00
|
|
|
//>> exp mrt0 v#x, v#x, v#x, v#x done ; $_ $_
|
2024-04-08 15:10:39 +01:00
|
|
|
//! s_endpgm ; $_
|
2023-06-02 13:36:55 +01:00
|
|
|
//! BB1:
|
2024-04-08 15:10:39 +01:00
|
|
|
//! exp mrt0 off, off, off, off done ; $_ $_
|
|
|
|
|
//! s_endpgm ; $_
|
2023-06-02 13:36:55 +01:00
|
|
|
|
|
|
|
|
PipelineBuilder pbld(get_vk_device(GFX11));
|
|
|
|
|
pbld.add_vsfs(vs, fs);
|
|
|
|
|
pbld.print_ir(VK_SHADER_STAGE_FRAGMENT_BIT, "Assembly");
|
|
|
|
|
END_TEST
|
2023-06-06 12:02:02 +01:00
|
|
|
|
|
|
|
|
BEGIN_TEST(isel.s_bfe_mask_bits)
|
|
|
|
|
QoShaderModuleCreateInfo cs = qoShaderModuleCreateInfoGLSL(COMPUTE,
|
|
|
|
|
layout(local_size_x=1) in;
|
|
|
|
|
layout(binding=0) buffer Buf {
|
|
|
|
|
int res;
|
|
|
|
|
};
|
|
|
|
|
void main() {
|
|
|
|
|
//>> s1: %bits, s1: (kill)%_:scc = s_and_b32 (kill)%_, 31
|
|
|
|
|
//! s1: %src1 = s_pack_ll_b32_b16 0, (kill)%bits
|
|
|
|
|
//! s1: %_, s1: (kill)%_:scc = s_bfe_i32 0xdeadbeef, (kill)%src1
|
|
|
|
|
res = bitfieldExtract(0xdeadbeef, 0, res & 0x1f);
|
|
|
|
|
}
|
|
|
|
|
);
|
|
|
|
|
|
|
|
|
|
PipelineBuilder pbld(get_vk_device(GFX10_3));
|
|
|
|
|
pbld.add_cs(cs);
|
|
|
|
|
pbld.print_ir(VK_SHADER_STAGE_COMPUTE_BIT, "ACO IR", true);
|
|
|
|
|
END_TEST
|
2024-03-20 12:45:31 +00:00
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* loop {
|
|
|
|
|
* if (uniform) {
|
|
|
|
|
* break;
|
|
|
|
|
* } else {
|
|
|
|
|
* break;
|
|
|
|
|
* }
|
|
|
|
|
* // unreachable continue
|
|
|
|
|
* }
|
|
|
|
|
*/
|
|
|
|
|
BEGIN_TEST(isel.cf.unreachable_continue.uniform_break)
|
|
|
|
|
if (!setup_nir_cs(GFX11))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
//>> s1: %init0 = p_unit_test 0
|
|
|
|
|
//>> v1: %init1 = p_unit_test 1
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_def *init0 = nir_unit_test_uniform_input(nb, 1, 32, .base=0);
|
|
|
|
|
nir_def *init1 = nir_unit_test_divergent_input(nb, 1, 32, .base=1);
|
2024-03-20 12:45:31 +00:00
|
|
|
nir_phi_instr *phi[2];
|
|
|
|
|
|
|
|
|
|
nir_loop *loop = nir_push_loop(nb);
|
|
|
|
|
{
|
|
|
|
|
//>> BB1
|
|
|
|
|
//! /* logical preds: BB0, / linear preds: BB0, / kind: uniform, loop-header, */
|
|
|
|
|
//! v1: %_ = p_phi %init1
|
|
|
|
|
//! s1: %_ = p_linear_phi %init0
|
|
|
|
|
phi[0] = nir_phi_instr_create(nb->shader);
|
|
|
|
|
phi[1] = nir_phi_instr_create(nb->shader);
|
|
|
|
|
nir_def_init(&phi[0]->instr, &phi[0]->def, 1, 32);
|
|
|
|
|
nir_def_init(&phi[1]->instr, &phi[1]->def, 1, 32);
|
2025-08-12 21:49:32 +02:00
|
|
|
nir_phi_instr_add_src(phi[0], nir_def_block(init0), init0);
|
|
|
|
|
nir_phi_instr_add_src(phi[1], nir_def_block(init1), init1);
|
2024-03-20 12:45:31 +00:00
|
|
|
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_uniform_input(nb, 1, 1, .base=4));
|
2024-03-20 12:45:31 +00:00
|
|
|
{
|
|
|
|
|
//>> BB2
|
|
|
|
|
//! /* logical preds: BB1, / linear preds: BB1, / kind: uniform, break, */
|
|
|
|
|
nir_jump(nb, nir_jump_break);
|
|
|
|
|
}
|
|
|
|
|
nir_push_else(nb, NULL);
|
|
|
|
|
{
|
|
|
|
|
/* The contents of this branch is moved to the merge block. */
|
|
|
|
|
//>> BB3
|
2026-01-21 11:00:58 +01:00
|
|
|
//! /* logical preds: BB1, / linear preds: BB1, / kind: uniform, break, */
|
2024-03-20 12:45:31 +00:00
|
|
|
//! p_logical_start
|
|
|
|
|
//! s1: %_ = p_unit_test 5
|
|
|
|
|
//! p_logical_end
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_uniform_input(nb, 1, 32, .base=5);
|
2024-03-20 12:45:31 +00:00
|
|
|
nir_jump(nb, nir_jump_break);
|
|
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_def *cont0 = nir_unit_test_uniform_input(nb, 1, 32, .base=2);
|
|
|
|
|
nir_def *cont1 = nir_unit_test_divergent_input(nb, 1, 32, .base=3);
|
2024-03-20 12:45:31 +00:00
|
|
|
|
|
|
|
|
nir_phi_instr_add_src(phi[0], nir_loop_last_block(loop), cont0);
|
|
|
|
|
nir_phi_instr_add_src(phi[1], nir_loop_last_block(loop), cont1);
|
|
|
|
|
}
|
|
|
|
|
nir_pop_loop(nb, NULL);
|
|
|
|
|
|
|
|
|
|
nb->cursor = nir_after_phis(nir_loop_first_block(loop));
|
|
|
|
|
nir_builder_instr_insert(nb, &phi[0]->instr);
|
|
|
|
|
nir_builder_instr_insert(nb, &phi[1]->instr);
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, &phi[0]->def);
|
|
|
|
|
nir_unit_test_output(nb, &phi[1]->def);
|
2024-03-20 12:45:31 +00:00
|
|
|
|
|
|
|
|
finish_isel_test();
|
|
|
|
|
END_TEST
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* loop {
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* break;
|
|
|
|
|
* } else {
|
|
|
|
|
* break;
|
|
|
|
|
* }
|
|
|
|
|
* // unreachable continue
|
|
|
|
|
* }
|
|
|
|
|
*/
|
|
|
|
|
BEGIN_TEST(isel.cf.unreachable_continue.divergent_break)
|
|
|
|
|
if (!setup_nir_cs(GFX11))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
//>> s1: %init0 = p_unit_test 0
|
|
|
|
|
//>> v1: %init1 = p_unit_test 1
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_def *init0 = nir_unit_test_uniform_input(nb, 1, 32, .base=0);
|
|
|
|
|
nir_def *init1 = nir_unit_test_divergent_input(nb, 1, 32, .base=1);
|
2024-03-20 12:45:31 +00:00
|
|
|
nir_phi_instr *phi[2];
|
|
|
|
|
|
|
|
|
|
nir_loop *loop = nir_push_loop(nb);
|
|
|
|
|
{
|
|
|
|
|
//>> BB1
|
|
|
|
|
//! /* logical preds: BB0, / linear preds: BB0, / kind: loop-header, branch, */
|
|
|
|
|
//! v1: %_ = p_phi %init1
|
|
|
|
|
//! s1: %_ = p_linear_phi %init0
|
|
|
|
|
phi[0] = nir_phi_instr_create(nb->shader);
|
|
|
|
|
phi[1] = nir_phi_instr_create(nb->shader);
|
|
|
|
|
nir_def_init(&phi[0]->instr, &phi[0]->def, 1, 32);
|
|
|
|
|
nir_def_init(&phi[1]->instr, &phi[1]->def, 1, 32);
|
2025-08-12 21:49:32 +02:00
|
|
|
nir_phi_instr_add_src(phi[0], nir_def_block(init0), init0);
|
|
|
|
|
nir_phi_instr_add_src(phi[1], nir_def_block(init1), init1);
|
2024-03-20 12:45:31 +00:00
|
|
|
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base=4));
|
2024-03-20 12:45:31 +00:00
|
|
|
{
|
|
|
|
|
//>> BB2
|
|
|
|
|
//! /* logical preds: BB1, / linear preds: BB1, / kind: break, */
|
|
|
|
|
nir_jump(nb, nir_jump_break);
|
|
|
|
|
}
|
|
|
|
|
nir_push_else(nb, NULL);
|
|
|
|
|
{
|
|
|
|
|
/* The contents of this branch is moved to the merge block. */
|
2026-01-21 14:09:52 +01:00
|
|
|
//>> BB6
|
|
|
|
|
//! /* logical preds: BB1, / linear preds: BB4, BB5, / kind: uniform, break, merge, */
|
2024-03-20 12:45:31 +00:00
|
|
|
//! p_logical_start
|
|
|
|
|
//! s1: %_ = p_unit_test 5
|
|
|
|
|
//! p_logical_end
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_uniform_input(nb, 1, 32, .base=5);
|
2024-03-20 12:45:31 +00:00
|
|
|
nir_jump(nb, nir_jump_break);
|
|
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_def *cont0 = nir_unit_test_uniform_input(nb, 1, 32, .base=2);
|
|
|
|
|
nir_def *cont1 = nir_unit_test_divergent_input(nb, 1, 32, .base=3);
|
2024-03-20 12:45:31 +00:00
|
|
|
|
|
|
|
|
nir_phi_instr_add_src(phi[0], nir_loop_last_block(loop), cont0);
|
|
|
|
|
nir_phi_instr_add_src(phi[1], nir_loop_last_block(loop), cont1);
|
|
|
|
|
}
|
|
|
|
|
nir_pop_loop(nb, NULL);
|
|
|
|
|
|
|
|
|
|
nb->cursor = nir_after_phis(nir_loop_first_block(loop));
|
|
|
|
|
nir_builder_instr_insert(nb, &phi[0]->instr);
|
|
|
|
|
nir_builder_instr_insert(nb, &phi[1]->instr);
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, &phi[0]->def);
|
|
|
|
|
nir_unit_test_output(nb, &phi[1]->def);
|
2024-03-20 12:45:31 +00:00
|
|
|
|
|
|
|
|
finish_isel_test();
|
|
|
|
|
END_TEST
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* loop {
|
|
|
|
|
* if (uniform) {
|
|
|
|
|
* continue;
|
|
|
|
|
* } else {
|
|
|
|
|
* continue;
|
|
|
|
|
* }
|
|
|
|
|
* // unreachable block
|
|
|
|
|
* break;
|
|
|
|
|
* }
|
2026-02-11 13:40:12 +01:00
|
|
|
*
|
|
|
|
|
* after nir_lower_continue_constructs() and sanitize_if():
|
|
|
|
|
*
|
|
|
|
|
* loop {
|
|
|
|
|
* if (uniform) {
|
|
|
|
|
* cont = true;
|
|
|
|
|
* } else {
|
|
|
|
|
* cont = true;
|
|
|
|
|
* }
|
|
|
|
|
* if (false) {
|
|
|
|
|
* break;
|
|
|
|
|
* }
|
|
|
|
|
* }
|
2024-03-20 12:45:31 +00:00
|
|
|
*/
|
|
|
|
|
BEGIN_TEST(isel.cf.unreachable_break.uniform_continue)
|
|
|
|
|
if (!setup_nir_cs(GFX11))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
nir_def *val0;
|
|
|
|
|
nir_def *val1;
|
|
|
|
|
|
|
|
|
|
/* These are undefs. */
|
|
|
|
|
//>> s3: %val1 = p_create_vector 0, 0, 0
|
|
|
|
|
//>> s1: %val0 = p_parallelcopy 0
|
|
|
|
|
|
2026-02-11 13:40:12 +01:00
|
|
|
nir_loop *loop = nir_push_loop(nb);
|
|
|
|
|
nir_loop_add_continue_construct(loop);
|
2024-03-20 12:45:31 +00:00
|
|
|
{
|
|
|
|
|
//>> BB1
|
2026-02-11 13:40:12 +01:00
|
|
|
//! /* logical preds: BB0, BB6, / linear preds: BB0, BB6, / kind: uniform, loop-header, */
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_uniform_input(nb, 1, 1, .base=2));
|
2024-03-20 12:45:31 +00:00
|
|
|
{
|
|
|
|
|
//>> BB2
|
2026-02-11 13:40:12 +01:00
|
|
|
//! /* logical preds: BB1, / linear preds: BB1, / kind: uniform, */
|
2024-03-20 12:45:31 +00:00
|
|
|
nir_jump(nb, nir_jump_continue);
|
|
|
|
|
}
|
|
|
|
|
nir_push_else(nb, NULL);
|
|
|
|
|
{
|
|
|
|
|
//>> BB3
|
|
|
|
|
//! /* logical preds: BB1, / linear preds: BB1, / kind: uniform, */
|
|
|
|
|
//! p_logical_start
|
|
|
|
|
//! s1: %_ = p_unit_test 5
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_uniform_input(nb, 1, 32, .base=5);
|
2024-03-20 12:45:31 +00:00
|
|
|
nir_jump(nb, nir_jump_continue);
|
|
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
2026-02-11 13:40:12 +01:00
|
|
|
/* The unreachable break is removed when lowering the continues. However,
|
|
|
|
|
* a dummy break is inserted, so that the loop has an exit.
|
|
|
|
|
*/
|
|
|
|
|
//>> BB4
|
|
|
|
|
//! /* logical preds: BB2, BB3, / linear preds: BB2, BB3, / kind: uniform, */
|
|
|
|
|
//! p_logical_start
|
|
|
|
|
//! s2: %zero = p_parallelcopy 0
|
|
|
|
|
//! s2: %_, s1: %cond:scc = s_and_b64 %zero, %0:exec
|
|
|
|
|
//! p_logical_end
|
|
|
|
|
//! p_cbranch_z %cond:scc
|
|
|
|
|
//! BB5
|
|
|
|
|
//! /* logical preds: BB4, / linear preds: BB4, / kind: uniform, break, */
|
|
|
|
|
//>> BB6
|
|
|
|
|
//! /* logical preds: BB4, / linear preds: BB4, / kind: uniform, continue, */
|
2024-03-20 12:45:31 +00:00
|
|
|
val0 = nir_imm_zero(nb, 1, 32);
|
|
|
|
|
val1 = nir_load_local_invocation_id(nb);
|
|
|
|
|
|
|
|
|
|
nir_jump(nb, nir_jump_break);
|
|
|
|
|
}
|
2026-02-11 13:40:12 +01:00
|
|
|
nir_pop_loop(nb, loop);
|
|
|
|
|
//>> BB7
|
|
|
|
|
//! /* logical preds: BB5, / linear preds: BB5, / kind: uniform, top-level, loop-exit, */
|
2024-03-20 12:45:31 +00:00
|
|
|
|
|
|
|
|
//>> p_unit_test 0, %val0
|
|
|
|
|
//! p_unit_test 1, %val1
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, val0, .base=0);
|
|
|
|
|
nir_unit_test_output(nb, val1, .base=1);
|
2024-03-20 12:45:31 +00:00
|
|
|
|
|
|
|
|
finish_isel_test();
|
|
|
|
|
END_TEST
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* loop {
|
|
|
|
|
* if (uniform) {
|
|
|
|
|
* break;
|
|
|
|
|
* } else {
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* break;
|
|
|
|
|
* } else {
|
|
|
|
|
* break;
|
|
|
|
|
* }
|
|
|
|
|
* }
|
|
|
|
|
* // unreachable continue
|
|
|
|
|
* }
|
|
|
|
|
*/
|
|
|
|
|
BEGIN_TEST(isel.cf.unreachable_continue.mixed_break)
|
|
|
|
|
if (!setup_nir_cs(GFX11))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
//>> s1: %init0 = p_unit_test 0
|
|
|
|
|
//>> v1: %init1 = p_unit_test 1
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_def *init0 = nir_unit_test_uniform_input(nb, 1, 32, .base=0);
|
|
|
|
|
nir_def *init1 = nir_unit_test_divergent_input(nb, 1, 32, .base=1);
|
2024-03-20 12:45:31 +00:00
|
|
|
nir_phi_instr *phi[2];
|
|
|
|
|
|
|
|
|
|
nir_loop *loop = nir_push_loop(nb);
|
|
|
|
|
{
|
|
|
|
|
//>> BB1
|
|
|
|
|
//! /* logical preds: BB0, / linear preds: BB0, / kind: uniform, loop-header, */
|
|
|
|
|
//! v1: %_ = p_phi %init1
|
|
|
|
|
//! s1: %_ = p_linear_phi %init0
|
|
|
|
|
phi[0] = nir_phi_instr_create(nb->shader);
|
|
|
|
|
phi[1] = nir_phi_instr_create(nb->shader);
|
|
|
|
|
nir_def_init(&phi[0]->instr, &phi[0]->def, 1, 32);
|
|
|
|
|
nir_def_init(&phi[1]->instr, &phi[1]->def, 1, 32);
|
2025-08-12 21:49:32 +02:00
|
|
|
nir_phi_instr_add_src(phi[0], nir_def_block(init0), init0);
|
|
|
|
|
nir_phi_instr_add_src(phi[1], nir_def_block(init1), init1);
|
2024-03-20 12:45:31 +00:00
|
|
|
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_uniform_input(nb, 1, 1, .base=4));
|
2024-03-20 12:45:31 +00:00
|
|
|
{
|
|
|
|
|
//>> BB2
|
|
|
|
|
//! /* logical preds: BB1, / linear preds: BB1, / kind: uniform, break, */
|
|
|
|
|
nir_jump(nb, nir_jump_break);
|
|
|
|
|
}
|
|
|
|
|
nir_push_else(nb, NULL);
|
|
|
|
|
{
|
|
|
|
|
/* The contents of this branch is moved to the merge block. */
|
|
|
|
|
//>> BB3
|
2026-01-21 11:00:58 +01:00
|
|
|
//! /* logical preds: BB1, / linear preds: BB1, / kind: branch, */
|
2024-03-20 12:45:31 +00:00
|
|
|
//! p_logical_start
|
|
|
|
|
//! s2: %cond = p_unit_test 5
|
|
|
|
|
//! p_logical_end
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//! p_cbranch_z %cond
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base=5));
|
2024-03-20 12:45:31 +00:00
|
|
|
{
|
2026-01-21 11:00:58 +01:00
|
|
|
//>> BB4
|
|
|
|
|
//! /* logical preds: BB3, / linear preds: BB3, / kind: break, */
|
2024-03-20 12:45:31 +00:00
|
|
|
nir_jump(nb, nir_jump_break);
|
|
|
|
|
}
|
|
|
|
|
nir_push_else(nb, NULL);
|
|
|
|
|
{
|
|
|
|
|
/* The contents of this branch is moved to the merge block. */
|
2026-01-21 14:09:52 +01:00
|
|
|
//>> BB8
|
|
|
|
|
//! /* logical preds: BB3, / linear preds: BB6, BB7, / kind: uniform, break, merge, */
|
2024-03-20 12:45:31 +00:00
|
|
|
//! p_logical_start
|
|
|
|
|
//! s1: %_ = p_unit_test 6
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_uniform_input(nb, 1, 32, .base=6);
|
2024-03-20 12:45:31 +00:00
|
|
|
nir_jump(nb, nir_jump_break);
|
|
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_def *cont0 = nir_unit_test_uniform_input(nb, 1, 32, .base=2);
|
|
|
|
|
nir_def *cont1 = nir_unit_test_divergent_input(nb, 1, 32, .base=3);
|
2024-03-20 12:45:31 +00:00
|
|
|
|
|
|
|
|
nir_phi_instr_add_src(phi[0], nir_loop_last_block(loop), cont0);
|
|
|
|
|
nir_phi_instr_add_src(phi[1], nir_loop_last_block(loop), cont1);
|
|
|
|
|
}
|
|
|
|
|
nir_pop_loop(nb, NULL);
|
2026-01-21 14:09:52 +01:00
|
|
|
//>> BB9
|
|
|
|
|
//! /* logical preds: BB2, BB4, BB8, / linear preds: BB2, BB5, BB8, / kind: uniform, top-level, loop-exit, */
|
2024-03-20 12:45:31 +00:00
|
|
|
|
|
|
|
|
nb->cursor = nir_after_phis(nir_loop_first_block(loop));
|
|
|
|
|
nir_builder_instr_insert(nb, &phi[0]->instr);
|
|
|
|
|
nir_builder_instr_insert(nb, &phi[1]->instr);
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, &phi[0]->def);
|
|
|
|
|
nir_unit_test_output(nb, &phi[1]->def);
|
2024-03-20 12:45:31 +00:00
|
|
|
|
|
|
|
|
finish_isel_test();
|
|
|
|
|
END_TEST
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* loop {
|
|
|
|
|
* if (uniform) {
|
|
|
|
|
* break;
|
|
|
|
|
* } else {
|
|
|
|
|
* if (uniform) {
|
|
|
|
|
* break;
|
|
|
|
|
* } else {
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* break;
|
|
|
|
|
* } else {
|
|
|
|
|
* break;
|
|
|
|
|
* }
|
|
|
|
|
* }
|
|
|
|
|
* }
|
|
|
|
|
* // unreachable continue
|
|
|
|
|
* }
|
|
|
|
|
*/
|
|
|
|
|
BEGIN_TEST(isel.cf.unreachable_continue.nested_mixed_break)
|
|
|
|
|
if (!setup_nir_cs(GFX11))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
//>> s1: %init0 = p_unit_test 0
|
|
|
|
|
//>> v1: %init1 = p_unit_test 1
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_def *init0 = nir_unit_test_uniform_input(nb, 1, 32, .base=0);
|
|
|
|
|
nir_def *init1 = nir_unit_test_divergent_input(nb, 1, 32, .base=1);
|
2024-03-20 12:45:31 +00:00
|
|
|
nir_phi_instr *phi[2];
|
|
|
|
|
|
|
|
|
|
nir_loop *loop = nir_push_loop(nb);
|
|
|
|
|
{
|
|
|
|
|
//>> BB1
|
|
|
|
|
//! /* logical preds: BB0, / linear preds: BB0, / kind: uniform, loop-header, */
|
|
|
|
|
//! v1: %_ = p_phi %init1
|
|
|
|
|
//! s1: %_ = p_linear_phi %init0
|
|
|
|
|
phi[0] = nir_phi_instr_create(nb->shader);
|
|
|
|
|
phi[1] = nir_phi_instr_create(nb->shader);
|
|
|
|
|
nir_def_init(&phi[0]->instr, &phi[0]->def, 1, 32);
|
|
|
|
|
nir_def_init(&phi[1]->instr, &phi[1]->def, 1, 32);
|
2025-08-12 21:49:32 +02:00
|
|
|
nir_phi_instr_add_src(phi[0], nir_def_block(init0), init0);
|
|
|
|
|
nir_phi_instr_add_src(phi[1], nir_def_block(init1), init1);
|
2024-03-20 12:45:31 +00:00
|
|
|
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_uniform_input(nb, 1, 1, .base=4));
|
2024-03-20 12:45:31 +00:00
|
|
|
{
|
|
|
|
|
//>> BB2
|
|
|
|
|
//! /* logical preds: BB1, / linear preds: BB1, / kind: uniform, break, */
|
|
|
|
|
nir_jump(nb, nir_jump_break);
|
|
|
|
|
}
|
|
|
|
|
nir_push_else(nb, NULL);
|
|
|
|
|
{
|
|
|
|
|
/* The contents of this branch is moved to the merge block. */
|
|
|
|
|
//>> BB3
|
|
|
|
|
//! /* logical preds: BB1, / linear preds: BB1, / kind: uniform, */
|
|
|
|
|
//! p_logical_start
|
|
|
|
|
//! s2: %cond1 = p_unit_test 4
|
|
|
|
|
//! s2: %_, s1: %_:scc = s_and_b64 %cond1, %0:exec
|
|
|
|
|
//! p_logical_end
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//! p_cbranch_z %_:scc
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_uniform_input(nb, 1, 1, .base=4));
|
2024-03-20 12:45:31 +00:00
|
|
|
{
|
2026-01-21 11:00:58 +01:00
|
|
|
//>> BB4
|
|
|
|
|
//! /* logical preds: BB3, / linear preds: BB3, / kind: uniform, break, */
|
2024-03-20 12:45:31 +00:00
|
|
|
nir_jump(nb, nir_jump_break);
|
|
|
|
|
}
|
|
|
|
|
nir_push_else(nb, NULL);
|
|
|
|
|
{
|
|
|
|
|
/* The contents of this branch is moved to the merge block. */
|
2026-01-21 11:00:58 +01:00
|
|
|
//>> BB5
|
|
|
|
|
//! /* logical preds: BB3, / linear preds: BB3, / kind: branch, */
|
2024-03-20 12:45:31 +00:00
|
|
|
//! p_logical_start
|
|
|
|
|
//! s2: %cond2 = p_unit_test 5
|
|
|
|
|
//! p_logical_end
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//! p_cbranch_z %cond2
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base=5));
|
2024-03-20 12:45:31 +00:00
|
|
|
{
|
2026-01-21 11:00:58 +01:00
|
|
|
//>> BB6
|
|
|
|
|
//! /* logical preds: BB5, / linear preds: BB5, / kind: break, */
|
2024-03-20 12:45:31 +00:00
|
|
|
nir_jump(nb, nir_jump_break);
|
|
|
|
|
}
|
|
|
|
|
nir_push_else(nb, NULL);
|
|
|
|
|
{
|
|
|
|
|
/* The contents of this branch is moved to the merge block. */
|
2026-01-21 14:09:52 +01:00
|
|
|
//>> BB10
|
|
|
|
|
//! /* logical preds: BB5, / linear preds: BB8, BB9, / kind: uniform, break, merge, */
|
2024-03-20 12:45:31 +00:00
|
|
|
nir_jump(nb, nir_jump_break);
|
|
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_def *cont0 = nir_unit_test_uniform_input(nb, 1, 32, .base=2);
|
|
|
|
|
nir_def *cont1 = nir_unit_test_divergent_input(nb, 1, 32, .base=3);
|
2024-03-20 12:45:31 +00:00
|
|
|
|
|
|
|
|
nir_phi_instr_add_src(phi[0], nir_loop_last_block(loop), cont0);
|
|
|
|
|
nir_phi_instr_add_src(phi[1], nir_loop_last_block(loop), cont1);
|
|
|
|
|
}
|
|
|
|
|
nir_pop_loop(nb, NULL);
|
|
|
|
|
|
|
|
|
|
nb->cursor = nir_after_phis(nir_loop_first_block(loop));
|
|
|
|
|
nir_builder_instr_insert(nb, &phi[0]->instr);
|
|
|
|
|
nir_builder_instr_insert(nb, &phi[1]->instr);
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, &phi[0]->def);
|
|
|
|
|
nir_unit_test_output(nb, &phi[1]->def);
|
2024-03-20 12:45:31 +00:00
|
|
|
|
|
|
|
|
finish_isel_test();
|
|
|
|
|
END_TEST
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* loop {
|
|
|
|
|
* continue;
|
|
|
|
|
* }
|
|
|
|
|
*/
|
|
|
|
|
BEGIN_TEST(isel.cf.unreachable_loop_exit)
|
|
|
|
|
if (!setup_nir_cs(GFX11))
|
|
|
|
|
return;
|
|
|
|
|
|
2026-02-11 13:40:12 +01:00
|
|
|
nir_loop *loop = nir_push_loop(nb);
|
|
|
|
|
nir_loop_add_continue_construct(loop);
|
2024-03-20 12:45:31 +00:00
|
|
|
{
|
|
|
|
|
/* A dummy break is inserted before the continue so that the loop has an exit. */
|
|
|
|
|
//>> BB1
|
2026-01-21 11:00:58 +01:00
|
|
|
//! /* logical preds: BB0, BB3, / linear preds: BB0, BB3, / kind: uniform, loop-header, */
|
2024-03-20 12:45:31 +00:00
|
|
|
//>> s1: %_ = p_unit_test 0
|
|
|
|
|
//>> s2: %zero = p_parallelcopy 0
|
|
|
|
|
//>> s2: %_, s1: %cond:scc = s_and_b64 %zero, %0:exec
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//>> p_cbranch_z %cond:scc
|
2024-03-20 12:45:31 +00:00
|
|
|
//! BB2
|
|
|
|
|
//! /* logical preds: BB1, / linear preds: BB1, / kind: uniform, break, */
|
2026-01-21 11:00:58 +01:00
|
|
|
//>> BB3
|
|
|
|
|
//! /* logical preds: BB1, / linear preds: BB1, / kind: uniform, continue, */
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_uniform_input(nb, 1, 32, .base=0);
|
2024-03-20 12:45:31 +00:00
|
|
|
nir_jump(nb, nir_jump_continue);
|
|
|
|
|
}
|
2026-02-11 13:40:12 +01:00
|
|
|
nir_pop_loop(nb, loop);
|
2024-03-20 12:45:31 +00:00
|
|
|
|
|
|
|
|
finish_isel_test();
|
|
|
|
|
END_TEST
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* loop {
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* break;
|
|
|
|
|
* } else {
|
|
|
|
|
* val = uniform;
|
|
|
|
|
* }
|
|
|
|
|
* use(val);
|
|
|
|
|
* }
|
|
|
|
|
*/
|
|
|
|
|
BEGIN_TEST(isel.cf.divergent_if_branch_use)
|
|
|
|
|
if (!setup_nir_cs(GFX11))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
nir_push_loop(nb);
|
|
|
|
|
{
|
|
|
|
|
nir_def *val;
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base=2));
|
2024-03-20 12:45:31 +00:00
|
|
|
{
|
|
|
|
|
//>> BB2
|
|
|
|
|
//! /* logical preds: BB1, / linear preds: BB1, / kind: break, */
|
|
|
|
|
nir_jump(nb, nir_jump_break);
|
|
|
|
|
}
|
|
|
|
|
nir_push_else(nb, NULL);
|
|
|
|
|
{
|
|
|
|
|
/* The contents of this branch is moved to the merge block. */
|
2026-01-21 14:09:52 +01:00
|
|
|
//>> BB6
|
|
|
|
|
//! /* logical preds: BB1, / linear preds: BB4, BB5, / kind: uniform, continue, merge, */
|
2024-03-20 12:45:31 +00:00
|
|
|
//! p_logical_start
|
|
|
|
|
//! s1: %val = p_unit_test 0
|
2025-12-23 12:38:52 -08:00
|
|
|
val = nir_unit_test_uniform_input(nb, 1, 32, .base=0);
|
2024-03-20 12:45:31 +00:00
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
|
|
|
|
|
//! p_unit_test 1, %val
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, val, .base=1);
|
2024-03-20 12:45:31 +00:00
|
|
|
}
|
|
|
|
|
nir_pop_loop(nb, NULL);
|
|
|
|
|
|
|
|
|
|
finish_isel_test();
|
|
|
|
|
END_TEST
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* loop {
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* continue;
|
|
|
|
|
* }
|
|
|
|
|
* if (uniform) {
|
|
|
|
|
* break;
|
|
|
|
|
* } else {
|
|
|
|
|
* val = uniform;
|
|
|
|
|
* }
|
|
|
|
|
* use(val);
|
|
|
|
|
* }
|
2026-02-11 13:40:12 +01:00
|
|
|
*
|
|
|
|
|
* after nir_lower_continue_constructs() and sanitize_if():
|
|
|
|
|
*
|
|
|
|
|
* loop {
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* } else {
|
|
|
|
|
* if (uniform) {
|
|
|
|
|
* break;
|
|
|
|
|
* }
|
|
|
|
|
* val = uniform;
|
|
|
|
|
* use(val);
|
|
|
|
|
* }
|
|
|
|
|
* }
|
2024-03-20 12:45:31 +00:00
|
|
|
*/
|
|
|
|
|
BEGIN_TEST(isel.cf.uniform_if_branch_use)
|
|
|
|
|
if (!setup_nir_cs(GFX11))
|
|
|
|
|
return;
|
|
|
|
|
|
2026-02-11 13:40:12 +01:00
|
|
|
nir_loop *loop = nir_push_loop(nb);
|
|
|
|
|
nir_loop_add_continue_construct(loop);
|
2024-03-20 12:45:31 +00:00
|
|
|
{
|
2026-02-11 13:40:12 +01:00
|
|
|
//>> BB1
|
|
|
|
|
//! /* logical preds: BB0, BB15, / linear preds: BB0, BB15, / kind: loop-header, branch, */
|
|
|
|
|
//>> s2: %_ = p_unit_test 3
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base=3));
|
2024-03-20 12:45:31 +00:00
|
|
|
{
|
|
|
|
|
nir_jump(nb, nir_jump_continue);
|
|
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
|
2026-02-11 13:40:12 +01:00
|
|
|
//>> BB4
|
|
|
|
|
//! /* logical preds: / linear preds: BB2, BB3, / kind: invert, */
|
|
|
|
|
//>> BB5
|
|
|
|
|
//! /* logical preds: BB1, / linear preds: BB4, / kind: uniform, */
|
2024-03-20 12:45:31 +00:00
|
|
|
//>> s2: %cond = p_unit_test 2
|
|
|
|
|
//! s2: %_, s1: %_:scc = s_and_b64 %cond, %0:exec
|
|
|
|
|
//! p_logical_end
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//! p_cbranch_z %_:scc
|
2024-03-20 12:45:31 +00:00
|
|
|
nir_def *val;
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_uniform_input(nb, 1, 1, .base=2));
|
2024-03-20 12:45:31 +00:00
|
|
|
{
|
2026-02-11 13:40:12 +01:00
|
|
|
//>> BB6
|
|
|
|
|
//! /* logical preds: BB5, / linear preds: BB5, / kind: break, */
|
2024-03-20 12:45:31 +00:00
|
|
|
nir_jump(nb, nir_jump_break);
|
|
|
|
|
}
|
|
|
|
|
nir_push_else(nb, NULL);
|
|
|
|
|
{
|
|
|
|
|
/* The contents of this branch is moved to the merge block. */
|
2026-02-11 13:40:12 +01:00
|
|
|
//>> BB10
|
|
|
|
|
//! /* logical preds: BB9, / linear preds: BB8, BB9, / kind: uniform, */
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//>> p_cbranch_z %0:exec rarely_taken
|
2026-02-11 13:40:12 +01:00
|
|
|
//! BB11
|
|
|
|
|
//! /* logical preds: BB10, / linear preds: BB10, / kind: uniform, */
|
2024-03-20 12:45:31 +00:00
|
|
|
//! p_logical_start
|
|
|
|
|
//! s1: %val = p_unit_test 0
|
2026-02-11 13:40:12 +01:00
|
|
|
//! p_unit_test 1, %val
|
2025-12-23 12:38:52 -08:00
|
|
|
val = nir_unit_test_uniform_input(nb, 1, 32, .base=0);
|
2024-03-20 12:45:31 +00:00
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, val, .base=1);
|
2024-07-19 20:03:43 +01:00
|
|
|
|
2026-02-11 13:40:12 +01:00
|
|
|
//>> BB15
|
|
|
|
|
//! /* logical preds: BB2, BB13, / linear preds: BB13, BB14, / kind: uniform, continue, merge, */
|
2024-03-20 12:45:31 +00:00
|
|
|
}
|
2026-02-11 13:40:12 +01:00
|
|
|
nir_pop_loop(nb, loop);
|
2024-03-20 12:45:31 +00:00
|
|
|
|
|
|
|
|
finish_isel_test();
|
|
|
|
|
END_TEST
|
2024-04-22 11:51:47 +01:00
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* b = ...
|
|
|
|
|
* loop {
|
|
|
|
|
* a = linear_phi b, c, d
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* c = ...
|
|
|
|
|
* continue
|
|
|
|
|
* }
|
|
|
|
|
* d = c or undef
|
|
|
|
|
* break
|
|
|
|
|
* }
|
2026-02-11 13:40:12 +01:00
|
|
|
*
|
|
|
|
|
* after nir_lower_continue_constructs() and sanitize_if():
|
|
|
|
|
*
|
|
|
|
|
* b = ...
|
|
|
|
|
* loop {
|
|
|
|
|
* a = linear_phi b, c
|
|
|
|
|
* if (!divergent) {
|
|
|
|
|
* break
|
|
|
|
|
* }
|
|
|
|
|
* c = ...
|
|
|
|
|
* }
|
2024-04-22 11:51:47 +01:00
|
|
|
*/
|
|
|
|
|
BEGIN_TEST(isel.cf.hidden_continue)
|
|
|
|
|
if (!setup_nir_cs(GFX11))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
//>> s1: %init = p_unit_test 0
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_def* init = nir_unit_test_uniform_input(nb, 1, 32, .base = 0);
|
2024-04-22 11:51:47 +01:00
|
|
|
nir_phi_instr* phi;
|
|
|
|
|
|
2026-02-11 13:40:12 +01:00
|
|
|
nir_loop *loop = nir_push_loop(nb);
|
|
|
|
|
nir_loop_add_continue_construct(loop);
|
2024-04-22 11:51:47 +01:00
|
|
|
{
|
|
|
|
|
//>> BB1
|
2026-02-11 13:40:12 +01:00
|
|
|
//! /* logical preds: BB0, BB6, / linear preds: BB0, BB6, / kind: loop-header, branch, */
|
|
|
|
|
//! s1: %2 = p_linear_phi %init, %cont
|
2024-04-22 11:51:47 +01:00
|
|
|
phi = nir_phi_instr_create(nb->shader);
|
|
|
|
|
nir_def_init(&phi->instr, &phi->def, 1, 32);
|
2025-08-12 21:49:32 +02:00
|
|
|
nir_phi_instr_add_src(phi, nir_def_block(init), init);
|
2024-04-22 11:51:47 +01:00
|
|
|
|
2026-02-11 13:40:12 +01:00
|
|
|
//>> s2: %cond = p_unit_test 4
|
|
|
|
|
//! s2: %inverse_cond, s1: %_:scc = s_not_b64 %cond
|
|
|
|
|
//>> p_cbranch_z %inverse_cond
|
|
|
|
|
//>> BB2
|
|
|
|
|
//! /* logical preds: BB1, / linear preds: BB1, / kind: break, */
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 4));
|
2024-04-22 11:51:47 +01:00
|
|
|
{
|
2026-02-11 13:40:12 +01:00
|
|
|
//>> BB6
|
|
|
|
|
//! /* logical preds: BB1, / linear preds: BB4, BB5, / kind: uniform, continue, merge, */
|
2024-04-22 11:51:47 +01:00
|
|
|
//! p_logical_start
|
|
|
|
|
//! s1: %cont = p_unit_test 1
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_def* cont = nir_unit_test_uniform_input(nb, 1, 32, .base = 1);
|
2026-02-11 13:40:12 +01:00
|
|
|
nir_phi_instr_add_src(phi, nir_loop_first_continue_block(loop), cont);
|
2024-04-22 11:51:47 +01:00
|
|
|
nir_jump(nb, nir_jump_continue);
|
|
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
|
|
|
|
|
nir_jump(nb, nir_jump_break);
|
|
|
|
|
}
|
2026-02-11 13:40:12 +01:00
|
|
|
//>> BB7
|
|
|
|
|
//! /* logical preds: BB2, / linear preds: BB3, / kind: uniform, top-level, loop-exit, */
|
|
|
|
|
nir_pop_loop(nb, loop);
|
2024-04-22 11:51:47 +01:00
|
|
|
|
|
|
|
|
nb->cursor = nir_after_phis(nir_loop_first_block(loop));
|
|
|
|
|
nir_builder_instr_insert(nb, &phi->instr);
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, &phi->def);
|
2024-04-22 11:51:47 +01:00
|
|
|
|
|
|
|
|
finish_isel_test();
|
|
|
|
|
END_TEST
|
|
|
|
|
|
2024-04-05 17:38:33 +01:00
|
|
|
/**
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* a =
|
|
|
|
|
* } else {
|
|
|
|
|
* }
|
|
|
|
|
* b = phi(a, undef);
|
|
|
|
|
* }
|
|
|
|
|
*/
|
|
|
|
|
BEGIN_TEST(isel.cf.divergent_if_undef.basic_then)
|
|
|
|
|
if (!setup_nir_cs(GFX11))
|
|
|
|
|
return;
|
|
|
|
|
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 2));
|
2024-04-05 17:38:33 +01:00
|
|
|
//>> BB1
|
|
|
|
|
//! /* logical preds: BB0, / linear preds: BB0, / kind: uniform, */
|
|
|
|
|
//! p_logical_start
|
|
|
|
|
//! s1: %val = p_unit_test 0
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_def* val = nir_unit_test_uniform_input(nb, 1, 32, .base = 0);
|
2024-04-05 17:38:33 +01:00
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
|
|
|
|
|
//>> BB3
|
|
|
|
|
//! /* logical preds: / linear preds: BB1, BB2, / kind: invert, */
|
|
|
|
|
//! s1: %phi = p_linear_phi %val, s1: undef
|
|
|
|
|
//>> BB6
|
|
|
|
|
//! /* logical preds: BB1, BB4, / linear preds: BB4, BB5, / kind: uniform, top-level, merge, */
|
|
|
|
|
//! s1: %phi2 = p_linear_phi %phi, %phi
|
|
|
|
|
//! p_logical_start
|
|
|
|
|
//! p_unit_test 1, %phi2
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_if_phi(nb, val, nir_undef(nb, 1, 32)), .base = 1);
|
2024-04-05 17:38:33 +01:00
|
|
|
|
|
|
|
|
finish_isel_test();
|
|
|
|
|
END_TEST
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* } else {
|
|
|
|
|
* a =
|
|
|
|
|
* }
|
|
|
|
|
* b = phi(undef, a);
|
|
|
|
|
* }
|
|
|
|
|
*/
|
|
|
|
|
BEGIN_TEST(isel.cf.divergent_if_undef.basic_else)
|
|
|
|
|
if (!setup_nir_cs(GFX11))
|
|
|
|
|
return;
|
|
|
|
|
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 2));
|
2024-04-05 17:38:33 +01:00
|
|
|
nir_push_else(nb, NULL);
|
|
|
|
|
//>> BB3
|
|
|
|
|
//! /* logical preds: / linear preds: BB1, BB2, / kind: invert, */
|
|
|
|
|
//>> BB4
|
|
|
|
|
//! /* logical preds: BB0, / linear preds: BB3, / kind: uniform, */
|
|
|
|
|
//! p_logical_start
|
|
|
|
|
//! s1: %val = p_unit_test 0
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_def* val = nir_unit_test_uniform_input(nb, 1, 32, .base = 0);
|
2024-04-05 17:38:33 +01:00
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
|
|
|
|
|
//>> BB6
|
|
|
|
|
//! /* logical preds: BB1, BB4, / linear preds: BB4, BB5, / kind: uniform, top-level, merge, */
|
|
|
|
|
//! s1: %phi = p_linear_phi %val, s1: undef
|
|
|
|
|
//! p_logical_start
|
|
|
|
|
//! p_unit_test 1, %phi
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_if_phi(nb, nir_undef(nb, 1, 32), val), .base = 1);
|
2024-04-05 17:38:33 +01:00
|
|
|
|
|
|
|
|
finish_isel_test();
|
|
|
|
|
END_TEST
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* loop {
|
|
|
|
|
* a =
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* break;
|
|
|
|
|
* } else {
|
|
|
|
|
* }
|
|
|
|
|
* b = phi(a);
|
|
|
|
|
* }
|
|
|
|
|
*/
|
2026-01-21 14:09:52 +01:00
|
|
|
BEGIN_TEST(isel.cf.divergent_if_phi.break)
|
2024-04-05 17:38:33 +01:00
|
|
|
if (!setup_nir_cs(GFX11))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
nir_push_loop(nb);
|
|
|
|
|
{
|
|
|
|
|
//>> BB1
|
2026-01-21 14:09:52 +01:00
|
|
|
//! /* logical preds: BB0, BB6, / linear preds: BB0, BB6, / kind: loop-header, branch, */
|
2024-04-05 17:38:33 +01:00
|
|
|
//! p_logical_start
|
|
|
|
|
//! s1: %val = p_unit_test 0
|
|
|
|
|
//! s2: %_ = p_unit_test 2
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_def* val = nir_unit_test_uniform_input(nb, 1, 32, .base = 0);
|
|
|
|
|
nir_if* nif = nir_push_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 2));
|
2024-04-05 17:38:33 +01:00
|
|
|
{
|
|
|
|
|
//>> BB2
|
|
|
|
|
//! /* logical preds: BB1, / linear preds: BB1, / kind: break, */
|
|
|
|
|
nir_jump(nb, nir_jump_break);
|
|
|
|
|
}
|
|
|
|
|
nir_push_else(nb, NULL);
|
|
|
|
|
{}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
2026-01-21 14:09:52 +01:00
|
|
|
/* As the ELSE gets omitted, the logical predecessor dominates both linear predecessors. */
|
2024-04-05 17:38:33 +01:00
|
|
|
|
2026-01-21 14:09:52 +01:00
|
|
|
//>> BB6
|
|
|
|
|
//! /* logical preds: BB1, / linear preds: BB4, BB5, / kind: uniform, continue, merge, */
|
|
|
|
|
//! s1: %phi = p_linear_phi %val, %val
|
2024-04-05 17:38:33 +01:00
|
|
|
nir_phi_instr* phi = nir_phi_instr_create(nb->shader);
|
|
|
|
|
nir_phi_instr_add_src(phi, nir_if_last_else_block(nif), val);
|
|
|
|
|
nir_def_init(&phi->instr, &phi->def, 1, 32);
|
|
|
|
|
nir_builder_instr_insert(nb, &phi->instr);
|
|
|
|
|
|
|
|
|
|
//! p_logical_start
|
|
|
|
|
//! p_unit_test 1, %phi
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, &phi->def, .base = 1);
|
2024-04-05 17:38:33 +01:00
|
|
|
}
|
|
|
|
|
nir_pop_loop(nb, NULL);
|
|
|
|
|
|
|
|
|
|
finish_isel_test();
|
|
|
|
|
END_TEST
|
|
|
|
|
|
|
|
|
|
/**
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* } else {
|
|
|
|
|
* }
|
|
|
|
|
* a = phi(undef, undef);
|
|
|
|
|
* }
|
|
|
|
|
*/
|
|
|
|
|
BEGIN_TEST(isel.cf.divergent_if_undef.both)
|
|
|
|
|
if (!setup_nir_cs(GFX11))
|
|
|
|
|
return;
|
|
|
|
|
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 1));
|
2024-04-05 17:38:33 +01:00
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
//>> BB6
|
|
|
|
|
//! /* logical preds: BB1, BB4, / linear preds: BB4, BB5, / kind: uniform, top-level, merge, */
|
|
|
|
|
//! s1: %4 = p_linear_phi s1: undef, s1: undef
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_if_phi(nb, nir_undef(nb, 1, 32), nir_undef(nb, 1, 32)), .base = 0);
|
2024-04-05 17:38:33 +01:00
|
|
|
|
|
|
|
|
finish_isel_test();
|
|
|
|
|
END_TEST
|
2024-10-10 14:27:40 +01:00
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* if (uniform) {
|
|
|
|
|
* terminate_if
|
|
|
|
|
* }
|
|
|
|
|
*/
|
|
|
|
|
BEGIN_TEST(isel.cf.empty_exec.uniform_if)
|
|
|
|
|
if (!setup_nir_cs(GFX11))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
//>> BB0
|
|
|
|
|
//>> s2: %_ = p_unit_test 0
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//>> p_cbranch_z %_:scc
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_uniform_input(nb, 1, 1, .base = 0));
|
2024-10-10 14:27:40 +01:00
|
|
|
{
|
|
|
|
|
//>> BB1
|
|
|
|
|
//>> s2: %_ = p_unit_test 1
|
|
|
|
|
//>> p_discard_if %_
|
|
|
|
|
//>> p_unit_test 2, %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_terminate_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 1));
|
|
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 2);
|
2024-10-10 14:27:40 +01:00
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
//>> BB3
|
|
|
|
|
//! /* logical preds: BB1, BB2, / linear preds: BB1, BB2, / kind: uniform, top-level, */
|
|
|
|
|
|
|
|
|
|
//>> p_unit_test 3, %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 3);
|
2024-10-10 14:27:40 +01:00
|
|
|
|
|
|
|
|
finish_isel_test();
|
|
|
|
|
END_TEST
|
|
|
|
|
|
2025-01-24 10:05:34 +01:00
|
|
|
/*
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* if (uniform) {
|
|
|
|
|
* terminate_if
|
|
|
|
|
* // exec potentially empty
|
|
|
|
|
* } else {
|
|
|
|
|
* }
|
|
|
|
|
* // exec potentially empty
|
|
|
|
|
* }
|
|
|
|
|
*/
|
|
|
|
|
BEGIN_TEST(isel.cf.empty_exec.nested_uniform_if)
|
|
|
|
|
if (!setup_nir_cs(GFX11))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
//>> BB0
|
|
|
|
|
//>> s2: %_ = p_unit_test 0
|
|
|
|
|
//>> p_cbranch_z %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 0));
|
2025-01-24 10:05:34 +01:00
|
|
|
{
|
|
|
|
|
//>> BB1
|
|
|
|
|
//>> s2: %_ = p_unit_test 1
|
|
|
|
|
//>> p_cbranch_z %_:scc
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_uniform_input(nb, 1, 1, .base = 1));
|
2025-01-24 10:05:34 +01:00
|
|
|
{
|
|
|
|
|
//>> BB2
|
|
|
|
|
//>> s2: %_ = p_unit_test 2
|
|
|
|
|
//>> p_discard_if %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_terminate_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 2));
|
2025-01-24 10:05:34 +01:00
|
|
|
|
|
|
|
|
//>> p_cbranch_z %0:exec rarely_taken
|
|
|
|
|
//>> p_unit_test 3, %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 3);
|
2025-01-24 10:05:34 +01:00
|
|
|
}
|
|
|
|
|
nir_push_else(nb, NULL);
|
|
|
|
|
{
|
|
|
|
|
//>> BB6
|
|
|
|
|
//>> p_unit_test 4, %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 4);
|
2025-01-24 10:05:34 +01:00
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
|
|
|
|
|
//>> BB7
|
|
|
|
|
//>> p_cbranch_z %0:exec rarely_taken
|
|
|
|
|
//>> p_unit_test 5, %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 5);
|
2025-01-24 10:05:34 +01:00
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
//>> BB15
|
|
|
|
|
//! /* logical preds: BB10, BB13, / linear preds: BB13, BB14, / kind: uniform, top-level, merge, */
|
|
|
|
|
//>> p_unit_test 6, %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 6);
|
2025-01-24 10:05:34 +01:00
|
|
|
|
|
|
|
|
finish_isel_test();
|
|
|
|
|
END_TEST
|
|
|
|
|
|
2024-10-10 14:27:40 +01:00
|
|
|
/*
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* terminate_if
|
|
|
|
|
* //potentially empty
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* terminate_if
|
|
|
|
|
* //potentially empty
|
|
|
|
|
* } else {
|
|
|
|
|
* terminate_if
|
|
|
|
|
* //potentially empty
|
|
|
|
|
* }
|
|
|
|
|
* //potentially empty
|
|
|
|
|
* }
|
|
|
|
|
*/
|
|
|
|
|
BEGIN_TEST(isel.cf.empty_exec.divergent_if)
|
|
|
|
|
if (!setup_nir_cs(GFX11))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
//>> BB0
|
|
|
|
|
//>> s2: %_ = p_unit_test 0
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//>> p_cbranch_z %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 0));
|
2024-10-10 14:27:40 +01:00
|
|
|
{
|
|
|
|
|
//>> BB1
|
|
|
|
|
//>> s2: %_ = p_unit_test 1
|
|
|
|
|
//>> p_discard_if %_
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//>> p_cbranch_z %0:exec rarely_taken
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_terminate_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 1));
|
2024-10-10 14:27:40 +01:00
|
|
|
|
|
|
|
|
//>> p_unit_test 2, %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 2);
|
2024-10-10 14:27:40 +01:00
|
|
|
|
|
|
|
|
//>> s2: %_ = p_unit_test 3
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//>> p_cbranch_z %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 3));
|
2024-10-10 14:27:40 +01:00
|
|
|
{
|
|
|
|
|
//>> p_unit_test 4, %_
|
|
|
|
|
//>> s2: %_ = p_unit_test 5
|
|
|
|
|
//>> p_discard_if %_
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//>> p_cbranch_z %0:exec rarely_taken
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 4);
|
|
|
|
|
nir_terminate_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 5));
|
2024-10-10 14:27:40 +01:00
|
|
|
|
|
|
|
|
//>> p_unit_test 6, %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 6);
|
2024-10-10 14:27:40 +01:00
|
|
|
}
|
|
|
|
|
nir_push_else(nb, NULL);
|
|
|
|
|
{
|
|
|
|
|
//>> p_unit_test 7, %_
|
|
|
|
|
//>> s2: %_ = p_unit_test 8
|
|
|
|
|
//>> p_discard_if %_
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//>> p_cbranch_z %0:exec rarely_taken
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 7);
|
|
|
|
|
nir_terminate_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 8));
|
2024-10-10 14:27:40 +01:00
|
|
|
|
|
|
|
|
//>> p_unit_test 9, %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 9);
|
2024-10-10 14:27:40 +01:00
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
//>> BB14
|
|
|
|
|
//! /* logical preds: BB6, BB12, / linear preds: BB12, BB13, / kind: uniform, merge, */
|
|
|
|
|
//>> BB15
|
|
|
|
|
//>> /* logical preds: / linear preds: BB1, / kind: uniform, */
|
|
|
|
|
//>> BB16
|
|
|
|
|
//! /* logical preds: BB14, / linear preds: BB14, BB15, / kind: uniform, */
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//>> p_cbranch_z %0:exec rarely_taken
|
2024-10-10 14:27:40 +01:00
|
|
|
|
|
|
|
|
//>> p_unit_test 10, %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 10);
|
2024-10-10 14:27:40 +01:00
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
|
|
|
|
|
//>> BB24
|
|
|
|
|
//! /* logical preds: BB19, BB22, / linear preds: BB22, BB23, / kind: uniform, top-level, merge, */
|
|
|
|
|
//! p_logical_start
|
|
|
|
|
//! p_unit_test 11, %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 11);
|
2024-10-10 14:27:40 +01:00
|
|
|
|
|
|
|
|
finish_isel_test();
|
|
|
|
|
END_TEST
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* loop {
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* break
|
|
|
|
|
* }
|
|
|
|
|
* //potentially empty
|
|
|
|
|
* }
|
|
|
|
|
* }
|
|
|
|
|
*/
|
|
|
|
|
BEGIN_TEST(isel.cf.empty_exec.loop_break)
|
|
|
|
|
if (!setup_nir_cs(GFX11))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
nir_push_loop(nb);
|
|
|
|
|
{
|
|
|
|
|
//>> BB1
|
|
|
|
|
//>> p_unit_test 0, %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 0);
|
2024-10-10 14:27:40 +01:00
|
|
|
|
|
|
|
|
//>> s2: %_ = p_unit_test 1
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 1));
|
2024-10-10 14:27:40 +01:00
|
|
|
{
|
|
|
|
|
//>> BB2
|
|
|
|
|
//>> s2: %_ = p_unit_test 2
|
|
|
|
|
//>> BB3
|
|
|
|
|
//! /* logical preds: BB2, / linear preds: BB2, / kind: break, */
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_break_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 2));
|
2026-01-21 14:09:52 +01:00
|
|
|
//>> BB7
|
|
|
|
|
//! /* logical preds: BB2, / linear preds: BB5, BB6, / kind: uniform, merge, */
|
2024-10-10 14:27:40 +01:00
|
|
|
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//>> p_cbranch_z %0:exec rarely_taken
|
2026-01-21 14:09:52 +01:00
|
|
|
//>> BB8
|
2024-10-10 14:27:40 +01:00
|
|
|
//>> p_unit_test 3, %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 3);
|
2024-10-10 14:27:40 +01:00
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
2026-01-21 14:09:52 +01:00
|
|
|
//>> BB15
|
|
|
|
|
//! /* logical preds: BB10, BB13, / linear preds: BB13, BB14, / kind: uniform, continue, merge, */
|
2024-10-10 14:27:40 +01:00
|
|
|
//! p_logical_start
|
|
|
|
|
|
|
|
|
|
//! p_unit_test 4, %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 4);
|
2024-10-10 14:27:40 +01:00
|
|
|
}
|
|
|
|
|
nir_pop_loop(nb, NULL);
|
2026-01-21 14:09:52 +01:00
|
|
|
//>> BB16
|
2024-10-10 14:27:40 +01:00
|
|
|
//! /* logical preds: BB3, / linear preds: BB4, / kind: uniform, top-level, loop-exit, */
|
|
|
|
|
//! p_logical_start
|
|
|
|
|
|
|
|
|
|
//! p_unit_test 5, %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 5);
|
2024-10-10 14:27:40 +01:00
|
|
|
|
|
|
|
|
finish_isel_test();
|
|
|
|
|
END_TEST
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* loop {
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* continue
|
|
|
|
|
* }
|
2026-02-11 13:40:12 +01:00
|
|
|
* unit_test 3
|
2024-10-10 14:27:40 +01:00
|
|
|
* //potentially empty
|
|
|
|
|
* }
|
2026-02-11 13:40:12 +01:00
|
|
|
* unit_test 4
|
|
|
|
|
* }
|
|
|
|
|
*
|
|
|
|
|
* after nir_lower_continue_constructs() and sanitize_if():
|
|
|
|
|
*
|
|
|
|
|
* loop {
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* cont = true
|
|
|
|
|
* } else {
|
|
|
|
|
* unit_test 3
|
|
|
|
|
* //potentially empty
|
|
|
|
|
* }
|
|
|
|
|
* }
|
|
|
|
|
* if (cont) {
|
|
|
|
|
* } else {
|
|
|
|
|
* unit_test 4
|
|
|
|
|
* }
|
2024-10-10 14:27:40 +01:00
|
|
|
* }
|
|
|
|
|
*/
|
|
|
|
|
BEGIN_TEST(isel.cf.empty_exec.loop_continue)
|
|
|
|
|
if (!setup_nir_cs(GFX11))
|
|
|
|
|
return;
|
|
|
|
|
|
2026-02-11 13:40:12 +01:00
|
|
|
nir_loop *loop = nir_push_loop(nb);
|
|
|
|
|
nir_loop_add_continue_construct(loop);
|
2024-10-10 14:27:40 +01:00
|
|
|
{
|
|
|
|
|
nir_break_if(nb, nir_imm_false(nb));
|
|
|
|
|
|
2026-01-21 11:00:58 +01:00
|
|
|
//>> BB3
|
2024-10-10 14:27:40 +01:00
|
|
|
//>> p_unit_test 0, %_
|
|
|
|
|
//>> s2: %_ = p_unit_test 1
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 0);
|
|
|
|
|
nir_push_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 1));
|
2024-10-10 14:27:40 +01:00
|
|
|
{
|
2026-01-21 11:00:58 +01:00
|
|
|
//>> BB4
|
2024-10-10 14:27:40 +01:00
|
|
|
//>> s2: %_ = p_unit_test 2
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 2));
|
2024-10-10 14:27:40 +01:00
|
|
|
{
|
2026-01-21 11:00:58 +01:00
|
|
|
//>> BB5
|
2026-02-11 13:40:12 +01:00
|
|
|
//! /* logical preds: BB4, / linear preds: BB4, / kind: uniform, */
|
|
|
|
|
//>> s2: %_ = p_parallelcopy -1
|
|
|
|
|
//>> s2: %cont1 = p_parallelcopy %0:exec
|
2024-10-10 14:27:40 +01:00
|
|
|
nir_jump(nb, nir_jump_continue);
|
|
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
2026-02-11 13:40:12 +01:00
|
|
|
//>> BB8
|
|
|
|
|
//! /* logical preds: BB4, / linear preds: BB7, / kind: uniform, */
|
|
|
|
|
//>> p_unit_test 3, %_
|
2024-10-10 14:27:40 +01:00
|
|
|
|
2026-01-21 14:09:52 +01:00
|
|
|
//>> BB10
|
2026-02-11 13:40:12 +01:00
|
|
|
//! /* logical preds: BB5, BB8, / linear preds: BB8, BB9, / kind: uniform, merge, */
|
|
|
|
|
//! s2: %cont2 = p_linear_phi %cont1, %cont1
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 3);
|
2024-10-10 14:27:40 +01:00
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
2026-02-11 13:40:12 +01:00
|
|
|
//>> BB12
|
|
|
|
|
//! /* logical preds: / linear preds: BB10, BB11, / kind: invert, */
|
|
|
|
|
//! s2: %tmp = p_linear_phi %cont2, s2: undef
|
|
|
|
|
//! s2: %cont3, s1: %16:scc = s_and_b64 %tmp, %0:exec
|
|
|
|
|
//>> BB15
|
|
|
|
|
//! /* logical preds: BB10, BB13, / linear preds: BB13, BB14, / kind: branch, merge, */
|
|
|
|
|
//! s2: %cont = p_linear_phi %cont3, %cont3
|
|
|
|
|
//>> p_cbranch_z %cont
|
|
|
|
|
//>> BB19
|
|
|
|
|
//! /* logical preds: BB15, / linear preds: BB18, / kind: uniform, */
|
|
|
|
|
//>> p_unit_test 4, %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 4);
|
2026-02-11 13:40:12 +01:00
|
|
|
//>> BB21
|
|
|
|
|
//! /* logical preds: BB16, BB19, / linear preds: BB19, BB20, / kind: uniform, continue, merge, */
|
2024-10-10 14:27:40 +01:00
|
|
|
}
|
2026-02-11 13:40:12 +01:00
|
|
|
nir_pop_loop(nb, loop);
|
|
|
|
|
//>> BB22
|
2024-10-10 14:27:40 +01:00
|
|
|
//! /* logical preds: BB2, / linear preds: BB2, / kind: uniform, top-level, loop-exit, */
|
|
|
|
|
//! p_logical_start
|
|
|
|
|
|
|
|
|
|
//! p_unit_test 5, %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 5);
|
2024-10-10 14:27:40 +01:00
|
|
|
|
|
|
|
|
finish_isel_test();
|
|
|
|
|
END_TEST
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* loop {
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* continue
|
|
|
|
|
* }
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* break
|
|
|
|
|
* }
|
|
|
|
|
* //potentially empty
|
|
|
|
|
* }
|
2026-02-11 13:40:12 +01:00
|
|
|
*
|
|
|
|
|
* after nir_lower_continue_constructs() and sanitize_if():
|
|
|
|
|
*
|
|
|
|
|
* loop {
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* } else {
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* break
|
|
|
|
|
* }
|
|
|
|
|
* //potentially empty
|
|
|
|
|
* }
|
|
|
|
|
* }
|
2024-10-10 14:27:40 +01:00
|
|
|
*/
|
|
|
|
|
BEGIN_TEST(isel.cf.empty_exec.loop_continue_then_break)
|
|
|
|
|
if (!setup_nir_cs(GFX11))
|
|
|
|
|
return;
|
|
|
|
|
|
2026-02-11 13:40:12 +01:00
|
|
|
nir_loop *loop = nir_push_loop(nb);
|
|
|
|
|
nir_loop_add_continue_construct(loop);
|
2024-10-10 14:27:40 +01:00
|
|
|
{
|
|
|
|
|
//>> BB1
|
2026-02-11 13:40:12 +01:00
|
|
|
//! /* logical preds: BB0, BB15, / linear preds: BB0, BB15, / kind: loop-header, branch, */
|
2024-10-10 14:27:40 +01:00
|
|
|
//>> p_unit_test 0, %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 0);
|
2024-10-10 14:27:40 +01:00
|
|
|
|
|
|
|
|
//>> s2: %_ = p_unit_test 1
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 1));
|
2024-10-10 14:27:40 +01:00
|
|
|
{
|
|
|
|
|
//>> BB2
|
2026-02-11 13:40:12 +01:00
|
|
|
//! /* logical preds: BB1, / linear preds: BB1, / kind: uniform, */
|
2024-10-10 14:27:40 +01:00
|
|
|
nir_jump(nb, nir_jump_continue);
|
|
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
|
2026-02-11 13:40:12 +01:00
|
|
|
//>> BB4
|
|
|
|
|
//! /* logical preds: / linear preds: BB2, BB3, / kind: invert, */
|
|
|
|
|
//>> BB5
|
|
|
|
|
//! /* logical preds: BB1, / linear preds: BB4, / kind: branch, */
|
2024-10-10 14:27:40 +01:00
|
|
|
//>> p_unit_test 2, %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 2);
|
2024-10-10 14:27:40 +01:00
|
|
|
|
|
|
|
|
//>> s2: %_ = p_unit_test 3
|
2026-02-11 13:40:12 +01:00
|
|
|
//>> BB6
|
|
|
|
|
//! /* logical preds: BB5, / linear preds: BB5, / kind: break, */
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_break_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 3));
|
2026-02-11 13:40:12 +01:00
|
|
|
//>> BB10
|
|
|
|
|
//! /* logical preds: BB5, / linear preds: BB8, BB9, / kind: uniform, merge, */
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//>> p_cbranch_z %0:exec rarely_taken
|
2024-10-10 14:27:40 +01:00
|
|
|
|
2026-02-11 13:40:12 +01:00
|
|
|
//>> BB11
|
|
|
|
|
//! /* logical preds: BB10, / linear preds: BB10, / kind: uniform, */
|
2024-10-10 14:27:40 +01:00
|
|
|
//>> p_unit_test 4, %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 4);
|
2024-10-10 14:27:40 +01:00
|
|
|
|
2026-02-11 13:40:12 +01:00
|
|
|
//>> BB15
|
|
|
|
|
//! /* logical preds: BB2, BB13, / linear preds: BB13, BB14, / kind: uniform, continue, merge, */
|
2024-10-10 14:27:40 +01:00
|
|
|
}
|
2026-02-11 13:40:12 +01:00
|
|
|
nir_pop_loop(nb, loop);
|
|
|
|
|
//>> BB16
|
|
|
|
|
//! /* logical preds: BB6, / linear preds: BB7, / kind: uniform, top-level, loop-exit, */
|
2024-10-10 14:27:40 +01:00
|
|
|
//! p_logical_start
|
|
|
|
|
|
|
|
|
|
//! p_unit_test 5, %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 5);
|
2024-10-10 14:27:40 +01:00
|
|
|
|
|
|
|
|
finish_isel_test();
|
|
|
|
|
END_TEST
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* terminate_if
|
|
|
|
|
* //potentially empty
|
|
|
|
|
* if (uniform) {
|
|
|
|
|
* }
|
|
|
|
|
* //potentially empty
|
|
|
|
|
* }
|
|
|
|
|
*/
|
|
|
|
|
BEGIN_TEST(isel.cf.empty_exec.terminate_then_uniform_if)
|
|
|
|
|
if (!setup_nir_cs(GFX11))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
//>> BB0
|
|
|
|
|
//>> s2: %_ = p_unit_test 0
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//>> p_cbranch_z %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 0));
|
2024-10-10 14:27:40 +01:00
|
|
|
{
|
|
|
|
|
//>> BB1
|
|
|
|
|
//>> s2: %_ = p_unit_test 1
|
|
|
|
|
//>> s2: %_ = p_unit_test 2
|
|
|
|
|
//>> p_discard_if %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_def* cond = nir_unit_test_uniform_input(nb, 1, 1, .base = 1);
|
|
|
|
|
nir_terminate_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 2));
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//>> p_cbranch_z %0:exec rarely_taken
|
2024-10-10 14:27:40 +01:00
|
|
|
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//>> p_cbranch_z %_:scc
|
2024-10-10 14:27:40 +01:00
|
|
|
nir_push_if(nb, cond);
|
|
|
|
|
{
|
|
|
|
|
//>> p_unit_test 3, %2
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 3);
|
2024-10-10 14:27:40 +01:00
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
|
|
|
|
|
//>> p_unit_test 4, %1
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 4);
|
2024-10-10 14:27:40 +01:00
|
|
|
|
|
|
|
|
//>> BB6
|
|
|
|
|
//! /* logical preds: / linear preds: BB1, / kind: uniform, */
|
|
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
|
|
|
|
|
finish_isel_test();
|
|
|
|
|
END_TEST
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* terminate_if
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* }
|
|
|
|
|
* //potentially empty
|
|
|
|
|
* }
|
|
|
|
|
*/
|
|
|
|
|
BEGIN_TEST(isel.cf.empty_exec.terminate_then_divergent_if)
|
|
|
|
|
if (!setup_nir_cs(GFX11))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
//>> BB0
|
|
|
|
|
//>> s2: %_ = p_unit_test 0
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//>> p_cbranch_z %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 0));
|
2024-10-10 14:27:40 +01:00
|
|
|
{
|
|
|
|
|
//>> BB1
|
|
|
|
|
//>> s2: %_ = p_unit_test 1
|
|
|
|
|
//>> s2: %_ = p_unit_test 2
|
|
|
|
|
//>> p_discard_if %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_def* cond = nir_unit_test_divergent_input(nb, 1, 1, .base = 1);
|
|
|
|
|
nir_terminate_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 2));
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//>> p_cbranch_z %0:exec rarely_taken
|
2024-10-10 14:27:40 +01:00
|
|
|
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//>> p_cbranch_z %_
|
2024-10-10 14:27:40 +01:00
|
|
|
nir_push_if(nb, cond);
|
|
|
|
|
{
|
|
|
|
|
//>> BB3
|
|
|
|
|
//! /* logical preds: BB2, / linear preds: BB2, / kind: uniform, */
|
|
|
|
|
//! p_logical_start
|
|
|
|
|
//! p_unit_test 3, %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 3);
|
2024-10-10 14:27:40 +01:00
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
|
|
|
|
|
//>> p_unit_test 4, %1
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 4);
|
2024-10-10 14:27:40 +01:00
|
|
|
|
|
|
|
|
//>> BB9
|
|
|
|
|
//! /* logical preds: / linear preds: BB1, / kind: uniform, */
|
|
|
|
|
}
|
|
|
|
|
nir_pop_if(nb, NULL);
|
|
|
|
|
|
|
|
|
|
finish_isel_test();
|
|
|
|
|
END_TEST
|
|
|
|
|
|
|
|
|
|
/*
|
|
|
|
|
* if (divergent) {
|
|
|
|
|
* terminate_if
|
|
|
|
|
* //potentially empty
|
|
|
|
|
* loop {
|
|
|
|
|
* }
|
|
|
|
|
* //potentially empty
|
|
|
|
|
* }
|
|
|
|
|
*/
|
|
|
|
|
BEGIN_TEST(isel.cf.empty_exec.terminate_then_loop)
|
|
|
|
|
if (!setup_nir_cs(GFX11))
|
|
|
|
|
return;
|
|
|
|
|
|
|
|
|
|
//>> BB0
|
|
|
|
|
//>> s2: %_ = p_unit_test 0
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//>> p_cbranch_z %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_push_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 0));
|
2024-10-10 14:27:40 +01:00
|
|
|
{
|
|
|
|
|
//>> BB1
|
|
|
|
|
//>> s2: %_ = p_unit_test 1
|
|
|
|
|
//>> p_discard_if %_
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_terminate_if(nb, nir_unit_test_divergent_input(nb, 1, 1, .base = 1));
|
aco: remove definition from Pseudo branch instructions
They are not needed anymore.
Totals from 7019 (8.84% of 79395) affected shaders: (Navi31)
Instrs: 14805400 -> 14824196 (+0.13%); split: -0.00%, +0.13%
CodeSize: 78079972 -> 78132932 (+0.07%); split: -0.01%, +0.08%
SpillSGPRs: 4485 -> 4515 (+0.67%); split: -0.76%, +1.43%
Latency: 165862000 -> 165836134 (-0.02%); split: -0.02%, +0.00%
InvThroughput: 30061764 -> 30057781 (-0.01%); split: -0.01%, +0.00%
SClause: 392323 -> 392286 (-0.01%); split: -0.01%, +0.00%
Copies: 1012262 -> 1012234 (-0.00%); split: -0.04%, +0.04%
Branches: 365910 -> 365909 (-0.00%); split: -0.00%, +0.00%
PreSGPRs: 360167 -> 355363 (-1.33%)
VALU: 8837197 -> 8837276 (+0.00%); split: -0.00%, +0.00%
SALU: 1402593 -> 1402621 (+0.00%); split: -0.03%, +0.03%
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/32037>
2024-11-07 09:42:04 +01:00
|
|
|
//>> p_cbranch_z %0:exec rarely_taken
|
2024-10-10 14:27:40 +01:00
|
|
|
|
|
|
|
|
//>> BB2
|
|
|
|
|
//! /* logical preds: BB1, / linear preds: BB1, / kind: uniform, loop-preheader, */
|
|
|
|
|
nir_push_loop(nb);
|
|
|
|
|
{
|
|
|
|
|
nir_break_if(nb, nir_imm_false(nb));
|
|
|
|
|
|
2026-01-21 11:00:58 +01:00
|
|
|
//>> BB5
|
|
|
|
|
//! /* logical preds: BB3, / linear preds: BB3, / kind: uniform, continue, */
|
2024-10-10 14:27:40 +01:00
|
|
|
//>> p_unit_test 2, %1
|
2025-12-23 12:38:52 -08:00
|
|
|
nir_unit_test_output(nb, nir_undef(nb, 1, 32), .base = 2);
|
2024-10-10 14:27:40 +01:00
|
|
|
}
|
|
|
|
|
nir_pop_loop(nb, NULL);
|
2026-01-21 11:00:58 +01:00
|
|
|
//>> BB6
|
2024-10-10 14:27:40 +01:00
|
|
|
//! /* logical preds: BB4, / linear preds: BB4, / kind: uniform, loop-exit, */
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
finish_isel_test();
|
|
|
|
|
END_TEST
|