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mesa/src/intel/genxml/gen6.xml

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genxml: Add XML version tags There's not much point to having them or not having them but this reduces some pointless diff from the version we can auto-generate Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-03-15 22:33:00 -07:00
<?xml version="1.0" ?>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<genxml name="SNB" gen="6">
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<enum name="3D_Prim_Topo_Type" prefix="3DPRIM">
<value name="POINTLIST" value="1"/>
<value name="LINELIST" value="2"/>
<value name="LINESTRIP" value="3"/>
<value name="TRILIST" value="4"/>
<value name="TRISTRIP" value="5"/>
<value name="TRIFAN" value="6"/>
<value name="QUADLIST" value="7"/>
<value name="QUADSTRIP" value="8"/>
<value name="LINELIST_ADJ" value="9"/>
<value name="LINESTRIP_ADJ" value="10"/>
<value name="TRILIST_ADJ" value="11"/>
<value name="TRISTRIP_ADJ" value="12"/>
<value name="TRISTRIP_REVERSE" value="13"/>
<value name="POLYGON" value="14"/>
<value name="RECTLIST" value="15"/>
<value name="LINELOOP" value="16"/>
<value name="POINTLIST _BF" value="17"/>
<value name="LINESTRIP_CONT" value="18"/>
<value name="LINESTRIP_BF" value="19"/>
<value name="LINESTRIP_CONT_BF" value="20"/>
<value name="TRIFAN_NOSTIPPLE" value="22"/>
</enum>
genxml: Make gen6-7 blending look more like gen8 This renames BLEND_STATE to BLEND_STATE_ENTRY and adds an new struct BLEND_STATE which is just an array of 8 BLEND_STATE_ENTRYs. This will make it much easier to write gen-agnostic blend handling code. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Cc: "12.0" <mesa-stable@lists.freedesktop.org>
2016-07-14 17:52:07 -07:00
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<enum name="3D_Vertex_Component_Control" prefix="VFCOMP">
<value name="NOSTORE" value="0"/>
<value name="STORE_SRC" value="1"/>
<value name="STORE_0" value="2"/>
<value name="STORE_1_FP" value="3"/>
<value name="STORE_1_INT" value="4"/>
<value name="STORE_VID" value="5"/>
<value name="STORE_IID" value="6"/>
<value name="STORE_PID" value="7"/>
</enum>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
intel/genxml: Use blend function and factor enums where applicable Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 17:42:46 -08:00
<enum name="3D_Color_Buffer_Blend_Function" prefix="BLENDFUNCTION">
<value name="ADD" value="0"/>
<value name="SUBTRACT" value="1"/>
<value name="REVERSE_SUBTRACT" value="2"/>
<value name="MIN" value="3"/>
<value name="MAX" value="4"/>
</enum>
<enum name="3D_Color_Buffer_Blend_Factor" prefix="BLENDFACTOR">
<value name="ONE" value="1"/>
<value name="SRC_COLOR" value="2"/>
<value name="SRC_ALPHA" value="3"/>
<value name="DST_ALPHA" value="4"/>
<value name="DST_COLOR" value="5"/>
<value name="SRC_ALPHA_SATURATE" value="6"/>
<value name="CONST_COLOR" value="7"/>
<value name="CONST_ALPHA" value="8"/>
<value name="SRC1_COLOR" value="9"/>
<value name="SRC1_ALPHA" value="10"/>
<value name="ZERO" value="17"/>
<value name="INV_SRC_COLOR" value="18"/>
<value name="INV_SRC_ALPHA" value="19"/>
<value name="INV_DST_ALPHA" value="20"/>
<value name="INV_DST_COLOR" value="21"/>
<value name="INV_CONST_COLOR" value="23"/>
<value name="INV_CONST_ALPHA" value="24"/>
<value name="INV_SRC1_COLOR" value="25"/>
<value name="INV_SRC1_ALPHA" value="26"/>
</enum>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<enum name="3D_Compare_Function" prefix="COMPAREFUNCTION">
<value name="ALWAYS" value="0"/>
<value name="NEVER" value="1"/>
<value name="LESS" value="2"/>
<value name="EQUAL" value="3"/>
<value name="LEQUAL" value="4"/>
<value name="GREATER" value="5"/>
<value name="NOTEQUAL" value="6"/>
<value name="GEQUAL" value="7"/>
</enum>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
intel/genxml: Use enum 3D_Stencil_Operation where applicable Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 17:10:57 -08:00
<enum name="3D_Stencil_Operation" prefix="STENCILOP">
<value name="KEEP" value="0"/>
<value name="ZERO" value="1"/>
<value name="REPLACE" value="2"/>
<value name="INCRSAT" value="3"/>
<value name="DECRSAT" value="4"/>
<value name="INCR" value="5"/>
<value name="DECR" value="6"/>
<value name="INVERT" value="7"/>
</enum>
intel/genxml: Use enum 3D_Logic_Op_Function where applicable Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 17:46:05 -08:00
<enum name="3D_Logic_Op_Function" prefix="LOGICOP">
<value name="CLEAR" value="0"/>
<value name="NOR" value="1"/>
<value name="AND_INVERTED" value="2"/>
<value name="COPY_INVERTED" value="3"/>
<value name="AND_REVERSE" value="4"/>
<value name="INVERT" value="5"/>
<value name="XOR" value="6"/>
<value name="NAND" value="7"/>
<value name="AND" value="8"/>
<value name="EQUIV" value="9"/>
<value name="NOOP" value="10"/>
<value name="OR_INVERTED" value="11"/>
<value name="COPY" value="12"/>
<value name="OR_REVERSE" value="13"/>
<value name="OR" value="14"/>
<value name="SET" value="15"/>
</enum>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<enum name="Texture Coordinate Mode" prefix="TCM">
<value name="WRAP" value="0"/>
<value name="MIRROR" value="1"/>
<value name="CLAMP" value="2"/>
<value name="CUBE" value="3"/>
<value name="CLAMP_BORDER" value="4"/>
<value name="MIRROR_ONCE" value="5"/>
</enum>
<struct name="MEMORY_OBJECT_CONTROL_STATE" length="1">
<field name="Graphics Data Type (GFDT)" start="2" end="2" type="uint"/>
<field name="Cacheability Control" start="0" end="1" type="uint"/>
</struct>
<struct name="VERTEX_BUFFER_STATE" length="4">
<field name="Vertex Buffer Index" start="26" end="31" type="uint"/>
<field name="Buffer Access Type" start="20" end="20" type="uint">
<value name="VERTEXDATA" value="0"/>
<value name="INSTANCEDATA" value="1"/>
</field>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="MOCS" start="16" end="19" type="uint"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Null Vertex Buffer" start="13" end="13" type="bool"/>
<field name="Vertex Fetch Invalidate" start="12" end="12" type="bool" default="0"/>
<field name="Buffer Pitch" start="0" end="11" type="uint"/>
<field name="Buffer Starting Address" start="32" end="63" type="address"/>
<field name="End Address" start="64" end="95" type="address"/>
<field name="Instance Data Step Rate" start="96" end="127" type="uint"/>
</struct>
<struct name="VERTEX_ELEMENT_STATE" length="2">
<field name="Vertex Buffer Index" start="26" end="31" type="uint"/>
<field name="Valid" start="25" end="25" type="bool"/>
intel: Drop SURFACE_FORMAT enum from genxml. We want people to be using ISL_FORMAT_*, rather than the genxml format enumerations. This patch drops 10 separate copies, and drops a bunch of ugly casting. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> [jordan.l.justen@intel.com: Minor changes for rebase] Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2018-02-13 18:13:51 -08:00
<field name="Source Element Format" start="16" end="24" type="uint"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Edge Flag Enable" start="15" end="15" type="bool"/>
<field name="Source Element Offset" start="0" end="11" type="uint"/>
intel/genxml: Use enum 3D_Vertex_Component_Control where applicable Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 17:20:23 -08:00
<field name="Component 0 Control" start="60" end="62" type="3D_Vertex_Component_Control"/>
<field name="Component 1 Control" start="56" end="58" type="3D_Vertex_Component_Control"/>
<field name="Component 2 Control" start="52" end="54" type="3D_Vertex_Component_Control"/>
<field name="Component 3 Control" start="48" end="50" type="3D_Vertex_Component_Control"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
</struct>
<struct name="SF_OUTPUT_ATTRIBUTE_DETAIL" length="1">
<field name="Component Override W" start="15" end="15" type="bool"/>
<field name="Component Override Z" start="14" end="14" type="bool"/>
<field name="Component Override Y" start="13" end="13" type="bool"/>
<field name="Component Override X" start="12" end="12" type="bool"/>
<field name="Swizzle Control Mode" start="11" end="11" type="uint"/>
<field name="Constant Source" start="9" end="10" type="uint">
<value name="CONST_0000" value="0"/>
<value name="CONST_0001_FLOAT" value="1"/>
<value name="CONST_1111_FLOAT" value="2"/>
<value name="PRIM_ID" value="3"/>
</field>
<field name="Swizzle Select" start="6" end="7" type="uint">
<value name="INPUTATTR" value="0"/>
<value name="INPUTATTR_FACING" value="1"/>
<value name="INPUTATTR_W" value="2"/>
<value name="INPUTATTR_FACING_W" value="3"/>
</field>
<field name="Source Attribute" start="0" end="4" type="uint"/>
</struct>
<struct name="CLIP_VIEWPORT" length="4">
genxml: Clip guardbands are float, not int. This makes genxml create the right struct types, and generate the right batch commands. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-03-30 10:36:25 -07:00
<field name="XMin Clip Guardband" start="0" end="31" type="float"/>
<field name="XMax Clip Guardband" start="32" end="63" type="float"/>
<field name="YMin Clip Guardband" start="64" end="95" type="float"/>
<field name="YMax Clip Guardband" start="96" end="127" type="float"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
</struct>
<struct name="SCISSOR_RECT" length="2">
<field name="Scissor Rectangle Y Min" start="16" end="31" type="uint"/>
<field name="Scissor Rectangle X Min" start="0" end="15" type="uint"/>
<field name="Scissor Rectangle Y Max" start="48" end="63" type="uint"/>
<field name="Scissor Rectangle X Max" start="32" end="47" type="uint"/>
</struct>
<struct name="SF_VIEWPORT" length="8">
<field name="Viewport Matrix Element m00" start="0" end="31" type="float"/>
<field name="Viewport Matrix Element m11" start="32" end="63" type="float"/>
<field name="Viewport Matrix Element m22" start="64" end="95" type="float">
<value name="Excludes DWord (0,1)" value="0"/>
</field>
<field name="Viewport Matrix Element m30" start="96" end="127" type="float"/>
<field name="Viewport Matrix Element m31" start="128" end="159" type="float"/>
<field name="Viewport Matrix Element m32" start="160" end="191" type="float"/>
</struct>
<struct name="BLEND_STATE_ENTRY" length="2">
<field name="Color Buffer Blend Enable" start="31" end="31" type="bool"/>
<field name="Independent Alpha Blend Enable" start="30" end="30" type="bool"/>
intel/genxml: Use blend function and factor enums where applicable Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 17:42:46 -08:00
<field name="Alpha Blend Function" start="26" end="28" type="3D_Color_Buffer_Blend_Function"/>
<field name="Source Alpha Blend Factor" start="20" end="24" type="3D_Color_Buffer_Blend_Factor"/>
<field name="Destination Alpha Blend Factor" start="15" end="19" type="3D_Color_Buffer_Blend_Factor"/>
<field name="Color Blend Function" start="11" end="13" type="3D_Color_Buffer_Blend_Function"/>
<field name="Source Blend Factor" start="5" end="9" type="3D_Color_Buffer_Blend_Factor"/>
<field name="Destination Blend Factor" start="0" end="4" type="3D_Color_Buffer_Blend_Factor"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="AlphaToCoverage Enable" start="63" end="63" type="bool"/>
<field name="AlphaToOne Enable" start="62" end="62" type="bool"/>
<field name="AlphaToCoverage Dither Enable" start="61" end="61" type="bool"/>
<field name="Write Disable Alpha" start="59" end="59" type="bool"/>
<field name="Write Disable Red" start="58" end="58" type="bool"/>
<field name="Write Disable Green" start="57" end="57" type="bool"/>
<field name="Write Disable Blue" start="56" end="56" type="bool"/>
<field name="Logic Op Enable" start="54" end="54" type="bool"/>
intel/genxml: Use enum 3D_Logic_Op_Function where applicable Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 17:46:05 -08:00
<field name="Logic Op Function" start="50" end="53" type="3D_Logic_Op_Function"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Alpha Test Enable" start="48" end="48" type="bool"/>
intel/genxml: Remove duplicate COMPAREFUNCTION values These values were defined both as an enum and as inline values. Remove the inline values and reference the 3D_Compare_Function enum instead. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:32:20 -08:00
<field name="Alpha Test Function" start="45" end="47" type="3D_Compare_Function"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Color Dither Enable" start="44" end="44" type="bool"/>
<field name="X Dither Offset" start="42" end="43" type="uint"/>
<field name="Y Dither Offset" start="40" end="41" type="uint"/>
<field name="Color Clamp Range" start="34" end="35" type="uint">
<value name="COLORCLAMP_UNORM" value="0"/>
<value name="COLORCLAMP_SNORM" value="1"/>
<value name="COLORCLAMP_RTFORMAT" value="2"/>
</field>
<field name="Pre-Blend Color Clamp Enable" start="33" end="33" type="bool"/>
<field name="Post-Blend Color Clamp Enable" start="32" end="32" type="bool"/>
</struct>
genxml: Make BLEND_STATE command support variable length array. We need to emit BLEND_STATE, which size is 1 + 2 * nr_draw_buffers dwords (on gen8+), but the BLEND_STATE struct length is always 17. By marking it size 1, which is actually the size of the struct minus the BLEND_STATE_ENTRY's, we can emit a BLEND_STATE of variable number of entries. For gen6 and gen7 we set length to 0, since it only contains BLEND_STATE_ENTRY's, and no other data. With this change, we also change the code for blorp and anv to emit only the needed BLEND_STATE_ENTRY's, instead of always emitting 16 dwords on gen6-7 and 17 dwords on gen8+. v2: - Use designated initializers on blorp and remove 0 from initialization (Jason) - Default entries to disabled on Vulkan (Jason) - Rebase code. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-03-30 11:33:05 -07:00
<struct name="BLEND_STATE" length="0">
<group count="0" start="0" size="64">
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Entry" start="0" end="63" type="BLEND_STATE_ENTRY"/>
</group>
</struct>
<struct name="CC_VIEWPORT" length="2">
<field name="Minimum Depth" start="0" end="31" type="float"/>
<field name="Maximum Depth" start="32" end="63" type="float"/>
</struct>
<struct name="COLOR_CALC_STATE" length="6">
<field name="Stencil Reference Value" start="24" end="31" type="uint"/>
<field name="Backface Stencil Reference Value" start="16" end="23" type="uint"/>
<field name="Round Disable Function Disable" start="15" end="15" type="bool"/>
<field name="Alpha Test Format" start="0" end="0" type="uint">
<value name="ALPHATEST_UNORM8" value="0"/>
<value name="ALPHATEST_FLOAT32" value="1"/>
</field>
<field name="Alpha Reference Value As UNORM8" start="32" end="63" type="uint"/>
<field name="Alpha Reference Value As FLOAT32" start="32" end="63" type="float"/>
<field name="Blend Constant Color Red" start="64" end="95" type="float"/>
<field name="Blend Constant Color Green" start="96" end="127" type="float"/>
<field name="Blend Constant Color Blue" start="128" end="159" type="float"/>
<field name="Blend Constant Color Alpha" start="160" end="191" type="float"/>
</struct>
<struct name="DEPTH_STENCIL_STATE" length="3">
<field name="Stencil Test Enable" start="31" end="31" type="bool"/>
intel/genxml: Remove duplicate COMPAREFUNCTION values These values were defined both as an enum and as inline values. Remove the inline values and reference the 3D_Compare_Function enum instead. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:32:20 -08:00
<field name="Stencil Test Function" start="28" end="30" type="3D_Compare_Function"/>
intel/genxml: Use enum 3D_Stencil_Operation where applicable Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 17:10:57 -08:00
<field name="Stencil Fail Op" start="25" end="27" type="3D_Stencil_Operation"/>
<field name="Stencil Pass Depth Fail Op" start="22" end="24" type="3D_Stencil_Operation"/>
<field name="Stencil Pass Depth Pass Op" start="19" end="21" type="3D_Stencil_Operation"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Stencil Buffer Write Enable" start="18" end="18" type="bool"/>
<field name="Double Sided Stencil Enable" start="15" end="15" type="bool"/>
intel/genxml: Remove duplicate COMPAREFUNCTION values These values were defined both as an enum and as inline values. Remove the inline values and reference the 3D_Compare_Function enum instead. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:32:20 -08:00
<field name="Backface Stencil Test Function" start="12" end="14" type="3D_Compare_Function"/>
intel/genxml: Use enum 3D_Stencil_Operation where applicable Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 17:10:57 -08:00
<field name="Backface Stencil Fail Op" start="9" end="11" type="3D_Stencil_Operation"/>
<field name="Backface Stencil Pass Depth Fail Op" start="6" end="8" type="3D_Stencil_Operation"/>
<field name="Backface Stencil Pass Depth Pass Op" start="3" end="5" type="3D_Stencil_Operation"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Stencil Test Mask" start="56" end="63" type="uint"/>
<field name="Stencil Write Mask" start="48" end="55" type="uint"/>
<field name="Backface Stencil Test Mask" start="40" end="47" type="uint"/>
<field name="Backface Stencil Write Mask" start="32" end="39" type="uint"/>
<field name="Depth Test Enable" start="95" end="95" type="bool"/>
intel/genxml: Remove duplicate COMPAREFUNCTION values These values were defined both as an enum and as inline values. Remove the inline values and reference the 3D_Compare_Function enum instead. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:32:20 -08:00
<field name="Depth Test Function" start="91" end="93" type="3D_Compare_Function"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Depth Buffer Write Enable" start="90" end="90" type="bool"/>
</struct>
<struct name="INTERFACE_DESCRIPTOR_DATA" length="8">
<field name="Kernel Start Pointer" start="6" end="31" type="offset"/>
<field name="Single Program Flow" start="50" end="50" type="bool"/>
<field name="Thread Priority" start="49" end="49" type="uint">
<value name="Normal Priority" value="0"/>
<value name="High Priority" value="1"/>
</field>
<field name="Floating Point Mode" start="48" end="48" type="uint">
<value name="IEEE-754" value="0"/>
<value name="Alternate" value="1"/>
</field>
<field name="Illegal Opcode Exception Enable" start="45" end="45" type="bool"/>
<field name="Mask Stack Exception Enable" start="43" end="43" type="bool"/>
<field name="Software Exception Enable" start="39" end="39" type="bool"/>
<field name="Sampler State Pointer" start="69" end="95" type="offset"/>
<field name="Sampler Count" start="66" end="68" type="uint">
<value name="No samplers used" value="0"/>
<value name="Between 1 and 4 samplers used" value="1"/>
<value name="Between 5 and 8 samplers used" value="2"/>
<value name="Between 9 and 12 samplers used" value="3"/>
<value name="Between 13 and 16 samplers used" value="4"/>
</field>
<field name="Binding Table Pointer" start="101" end="127" type="offset"/>
<field name="Binding Table Entry Count" start="96" end="100" type="uint"/>
<field name="Constant URB Entry Read Length" start="144" end="159" type="uint"/>
<field name="Constant URB Entry Read Offset" start="128" end="143" type="uint"/>
<field name="Barrier Return GRF Offset" start="184" end="191" type="uint"/>
<field name="Barrier Return Byte" start="168" end="175" type="uint"/>
<field name="Barrier ID" start="160" end="163" type="uint"/>
</struct>
<struct name="PALETTE_ENTRY" length="1">
<field name="Alpha" start="24" end="31" type="uint"/>
<field name="Red" start="16" end="23" type="uint"/>
<field name="Green" start="8" end="15" type="uint"/>
<field name="Blue" start="0" end="7" type="uint"/>
</struct>
<struct name="BINDING_TABLE_STATE" length="1">
<field name="Surface State Pointer" start="5" end="31" type="offset"/>
</struct>
<struct name="RENDER_SURFACE_STATE" length="6">
<field name="Surface Type" start="29" end="31" type="uint">
<value name="SURFTYPE_1D" value="0"/>
<value name="SURFTYPE_2D" value="1"/>
<value name="SURFTYPE_3D" value="2"/>
<value name="SURFTYPE_CUBE" value="3"/>
<value name="SURFTYPE_BUFFER" value="4"/>
<value name="SURFTYPE_NULL" value="7"/>
</field>
<field name="Data Return Format" start="27" end="27" type="uint">
<value name="DATA_RETURN_FLOAT32" value="0"/>
</field>
intel: Drop SURFACE_FORMAT enum from genxml. We want people to be using ISL_FORMAT_*, rather than the genxml format enumerations. This patch drops 10 separate copies, and drops a bunch of ugly casting. Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> [jordan.l.justen@intel.com: Minor changes for rebase] Signed-off-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Samuel Iglesias Gonsálvez <siglesias@igalia.com>
2018-02-13 18:13:51 -08:00
<field name="Surface Format" start="18" end="26" type="uint"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Vertical Line Stride" start="12" end="12" type="uint"/>
<field name="Vertical Line Stride Offset" start="11" end="11" type="uint"/>
<field name="MIP Map Layout Mode" start="10" end="10" type="uint">
<value name="MIPLAYOUT_BELOW" value="0"/>
<value name="MIPLAYOUT_RIGHT" value="1"/>
</field>
<field name="Cube Map Corner Mode" start="9" end="9" type="uint">
<value name="CUBE_REPLICATE" value="0"/>
<value name="CUBE_AVERAGE" value="1"/>
</field>
<field name="Render Cache Read Write Mode" start="8" end="8" type="uint">
<value name="WRITE_ONLY" value="0"/>
<value name="READ_WRITE" value="1"/>
</field>
<field name="Media Boundary Pixel Mode" start="6" end="7" type="uint">
<value name="NORMAL_MODE" value="0"/>
<value name="PROGRESSIVE_FRAME" value="2"/>
<value name="INTERLACED_FRAME" value="3"/>
</field>
intel: Make Cube Face Enable fields consistent across generations. I decided to use the one-boolean-per-cube-face approach because it's clearer which bits correspond to which cube face. Reviewed-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2017-09-28 14:51:53 -07:00
<field name="Cube Face Enable - Positive Z" start="0" end="0" type="bool"/>
<field name="Cube Face Enable - Negative Z" start="1" end="1" type="bool"/>
<field name="Cube Face Enable - Positive Y" start="2" end="2" type="bool"/>
<field name="Cube Face Enable - Negative Y" start="3" end="3" type="bool"/>
<field name="Cube Face Enable - Positive X" start="4" end="4" type="bool"/>
<field name="Cube Face Enable - Negative X" start="5" end="5" type="bool"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Surface Base Address" start="32" end="63" type="address"/>
<field name="Height" start="83" end="95" type="uint"/>
<field name="Width" start="70" end="82" type="uint"/>
<field name="MIP Count / LOD" start="66" end="69" type="uint"/>
<field name="Render Target Rotation" start="64" end="65" type="uint">
<value name="RTROTATE_0DEG" value="0"/>
<value name="RTROTATE_90DEG" value="1"/>
<value name="RTROTATE_270DEG" value="3"/>
</field>
<field name="Depth" start="117" end="127" type="uint"/>
<field name="Surface Pitch" start="99" end="115" type="uint"/>
<field name="Tiled Surface" start="97" end="97" type="bool"/>
<field name="Tile Walk" start="96" end="96" type="uint">
<value name="TILEWALK_XMAJOR" value="0"/>
<value name="TILEWALK_YMAJOR" value="1"/>
</field>
<field name="Surface Min LOD" start="156" end="159" type="uint"/>
<field name="Minimum Array Element" start="145" end="155" type="uint"/>
<field name="Render Target View Extent" start="136" end="144" type="uint"/>
<field name="Number of Multisamples" start="132" end="134" type="uint">
<value name="MULTISAMPLECOUNT_1" value="0"/>
<value name="MULTISAMPLECOUNT_4" value="2"/>
</field>
<field name="Multisample Position Palette Index" start="128" end="130" type="uint"/>
<field name="X Offset" start="185" end="191" type="uint"/>
<field name="Surface Vertical Alignment" start="184" end="184" type="uint">
<value name="VALIGN_2" value="0"/>
<value name="VALIGN_4" value="1"/>
</field>
<field name="Y Offset" start="180" end="183" type="uint"/>
<field name="MOCS" start="176" end="179" type="uint"/>
</struct>
<struct name="SAMPLER_BORDER_COLOR_STATE" length="12">
<field name="Border Color Unorm Red" start="0" end="7" type="uint"/>
<field name="Border Color Unorm Green" start="8" end="15" type="uint"/>
<field name="Border Color Unorm Blue" start="16" end="23" type="uint"/>
<field name="Border Color Unorm Alpha" start="24" end="31" type="uint"/>
<field name="Border Color Float Red" start="32" end="63" type="float"/>
<field name="Border Color Float Green" start="64" end="95" type="float"/>
<field name="Border Color Float Blue" start="96" end="127" type="float"/>
<field name="Border Color Float Alpha" start="128" end="159" type="float"/>
<field name="Border Color Float16 Red" start="160" end="175" type="uint"/>
<field name="Border Color Float16 Green" start="176" end="191" type="uint"/>
<field name="Border Color Float16 Blue" start="192" end="207" type="uint"/>
<field name="Border Color Float16 Alpha" start="208" end="223" type="uint"/>
<field name="Border Color Unorm16 Red" start="224" end="239" type="uint"/>
<field name="Border Color Unorm16 Green" start="240" end="255" type="uint"/>
<field name="Border Color Unorm16 Blue" start="256" end="271" type="uint"/>
<field name="Border Color Unorm16 Alpha" start="272" end="287" type="uint"/>
<field name="Border Color Snorm16 Red" start="288" end="303" type="int"/>
<field name="Border Color Snorm16 Green" start="304" end="319" type="int"/>
<field name="Border Color Snorm16 Blue" start="320" end="335" type="int"/>
<field name="Border Color Snorm16 Alpha" start="336" end="351" type="int"/>
<field name="Border Color Snorm8 Red" start="352" end="359" type="int"/>
<field name="Border Color Snorm8 Green" start="360" end="367" type="int"/>
<field name="Border Color Snorm8 Blue" start="368" end="375" type="int"/>
<field name="Border Color Snorm8 Alpha" start="376" end="383" type="int"/>
</struct>
<struct name="SAMPLER_STATE" length="4">
<field name="Sampler Disable" start="31" end="31" type="bool"/>
<field name="Texture Border Color Mode" start="29" end="29" type="uint">
<value name="DX10/OGL" value="0"/>
<value name="DX9" value="1"/>
</field>
<field name="LOD PreClamp Enable" start="28" end="28" type="uint" prefix="CLAMP_ENABLE">
<value name="OGL" value="1"/>
</field>
<field name="Min and Mag State Not Equal" start="27" end="27" type="uint">
<value name="MIN_MAG_EQ" value="0"/>
<value name="MIN_MAG_NEQ" value="1"/>
</field>
<field name="Base Mip Level" start="22" end="26" type="u4.1"/>
<field name="Mip Mode Filter" start="20" end="21" type="uint" prefix="MIPFILTER">
<value name="NONE" value="0"/>
<value name="NEAREST" value="1"/>
<value name="LINEAR" value="3"/>
</field>
<field name="Mag Mode Filter" start="17" end="19" type="uint" prefix="MAPFILTER">
<value name="NEAREST" value="0"/>
<value name="LINEAR" value="1"/>
<value name="ANISOTROPIC" value="2"/>
<value name="MONO" value="6"/>
</field>
<field name="Min Mode Filter" start="14" end="16" type="uint" prefix="MAPFILTER"/>
<field name="Texture LOD Bias" start="3" end="13" type="s4.6"/>
<field name="Shadow Function" start="0" end="2" type="uint">
<value name="PREFILTEROP_ALWAYS" value="0"/>
<value name="PREFILTEROP_NEVER" value="1"/>
<value name="PREFILTEROP_LESS" value="2"/>
<value name="PREFILTEROP_EQUAL" value="3"/>
<value name="PREFILTEROP_LEQUAL" value="4"/>
<value name="PREFILTEROP_GREATER" value="5"/>
<value name="PREFILTEROP_NOTEQUAL" value="6"/>
<value name="PREFILTEROP_GEQUAL" value="7"/>
</field>
<field name="Min LOD" start="54" end="63" type="u4.6"/>
<field name="Max LOD" start="44" end="53" type="u4.6"/>
<field name="Cube Surface Control Mode" start="41" end="41" type="uint">
<value name="CUBECTRLMODE_PROGRAMMED" value="0"/>
<value name="CUBECTRLMODE_OVERRIDE" value="1"/>
</field>
intel: genxml: make a couple of enums show up in aubinator In particular Shader Channel Select & Texture Address Control Mode. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2017-06-30 17:25:43 +01:00
<field name="TCX Address Control Mode" start="38" end="40" type="Texture Coordinate Mode"/>
<field name="TCY Address Control Mode" start="35" end="37" type="Texture Coordinate Mode"/>
<field name="TCZ Address Control Mode" start="32" end="34" type="Texture Coordinate Mode"/>
intel/genxml: Move enums above structs We'll need to define them before we can reference them in structs and instructions. Enums have no dependencies, so move them first in the file. Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:14:12 -08:00
<field name="Border Color Pointer" start="69" end="95" type="offset"/>
<field name="Monochrome Filter Height: Reserved" start="125" end="127" type="uint"/>
<field name="Monochrome Filter Width" start="122" end="124" type="uint"/>
<field name="ChromaKey Enable" start="121" end="121" type="bool"/>
<field name="ChromaKey Index" start="119" end="120" type="uint"/>
<field name="ChromaKey Mode" start="118" end="118" type="uint">
<value name="KEYFILTER_KILL_ON_ANY_MATCH" value="0"/>
<value name="KEYFILTER_REPLACE_BLACK" value="1"/>
</field>
<field name="Maximum Anisotropy" start="115" end="117" type="uint">
<value name="RATIO 2:1" value="0"/>
<value name="RATIO 4:1" value="1"/>
<value name="RATIO 6:1" value="2"/>
<value name="RATIO 8:1" value="3"/>
<value name="RATIO 10:1" value="4"/>
<value name="RATIO 12:1" value="5"/>
<value name="RATIO 14:1" value="6"/>
<value name="RATIO 16:1" value="7"/>
</field>
<field name="R Address Min Filter Rounding Enable" start="109" end="109" type="bool"/>
<field name="R Address Mag Filter Rounding Enable" start="110" end="110" type="bool"/>
<field name="V Address Min Filter Rounding Enable" start="111" end="111" type="bool"/>
<field name="V Address Mag Filter Rounding Enable" start="112" end="112" type="bool"/>
<field name="U Address Min Filter Rounding Enable" start="113" end="113" type="bool"/>
<field name="U Address Mag Filter Rounding Enable" start="114" end="114" type="bool"/>
<field name="Non-normalized Coordinate Enable" start="96" end="96" type="bool"/>
</struct>
genxml/gen6: Make SAMPLER_STATE look a bit more like gen7 Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-08-10 16:40:44 -07:00
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DPRIMITIVE" bias="2" length="6" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="3"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="0"/>
<field name="Vertex Access Type" start="15" end="15" type="uint">
<value name="SEQUENTIAL" value="0"/>
<value name="RANDOM" value="1"/>
</field>
intel/genxml: Use enum 3D_Prim_Topo_Type where applicable Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-28 16:44:22 -08:00
<field name="Primitive Topology Type" start="10" end="14" type="3D_Prim_Topo_Type"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Internal Vertex Count" start="9" end="9" type="uint"/>
<field name="DWord Length" start="0" end="7" type="uint" default="4"/>
<field name="Vertex Count Per Instance" start="32" end="63" type="uint"/>
<field name="Start Vertex Location" start="64" end="95" type="uint"/>
<field name="Instance Count" start="96" end="127" type="uint">
<value name="UNDEFINED" value="0"/>
<value name="'non-instanced' operation" value="1"/>
</field>
<field name="Start Instance Location" start="128" end="159" type="uint"/>
<field name="Base Vertex Location" start="160" end="191" type="int"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_AA_LINE_PARAMETERS" bias="2" length="3" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="10"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="AA Coverage Bias" start="48" end="55" type="u0.8"/>
<field name="AA Coverage Slope" start="32" end="39" type="u0.8"/>
<field name="AA Coverage EndCap Bias" start="80" end="87" type="u0.8"/>
<field name="AA Coverage EndCap Slope" start="64" end="71" type="u0.8"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_BINDING_TABLE_POINTERS" bias="2" length="4" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="1"/>
<field name="PS Binding Table Change" start="12" end="12" type="bool"/>
<field name="GS Binding Table Change" start="9" end="9" type="bool"/>
<field name="VS Binding Table Change" start="8" end="8" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
<field name="Pointer to VS Binding Table" start="37" end="63" type="offset"/>
<field name="Pointer to GS Binding Table" start="69" end="95" type="offset"/>
<field name="Pointer to PS Binding Table" start="101" end="127" type="offset"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_CC_STATE_POINTERS" bias="2" length="4" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="14"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
<field name="Pointer to BLEND_STATE" start="38" end="63" type="offset"/>
<field name="BLEND_STATE Change" start="32" end="32" type="bool"/>
<field name="Pointer to DEPTH_STENCIL_STATE" start="70" end="95" type="offset"/>
<field name="DEPTH_STENCIL_STATE Change" start="64" end="64" type="bool"/>
genxml: Normalize xml for 3DSTATE_CC_STATE_POINTERS. - "COLOR_CALC_STATE Change" -> "Color Calc State Pointer Valid" - "Pointer to COLOR_CALC_STATE" -> "Color Calc State Pointer" - "BackFace" -> "Backface" Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-04-19 16:13:20 -07:00
<field name="Color Calc State Pointer" start="102" end="127" type="offset"/>
<field name="Color Calc State Pointer Valid" start="96" end="96" type="bool"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_CHROMA_KEY" bias="2" length="4" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="4"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
<field name="ChromaKey Table Index" start="62" end="63" type="uint"/>
<field name="ChromaKey Low Value" start="64" end="95" type="uint"/>
<field name="ChromaKey High Value" start="96" end="127" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_CLEAR_PARAMS" bias="2" length="2" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="16"/>
<field name="Depth Clear Value Valid" start="15" end="15" type="bool"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
genxml/gen6: Make "Depth Clear Value" a uint The actual data storred is in float, UNORM24, or UNORM16 depending on the actual depth format. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-08-09 08:18:20 -07:00
<field name="Depth Clear Value" start="32" end="63" type="uint"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_CLIP" bias="2" length="4" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="18"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
genxml: s/Clipper Statistics Enable/Statistics Enable/ It's in 3DSTATE_CLIP, so it doesn't really need the extra detail. This matches what we do for VS, FS, etc. Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-03-16 12:31:42 -07:00
<field name="Statistics Enable" start="42" end="42" type="bool"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="User Clip Distance Cull Test Enable Bitmask" start="32" end="39" type="uint"/>
genxml: Rename clip enable property. There are two variants: - Clip Enable - CLIP Enable (on gen6) Rename everything to Clip Enable. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-03-15 17:07:10 -07:00
<field name="Clip Enable" start="95" end="95" type="bool"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="API Mode" start="94" end="94" type="uint">
<value name="APIMODE_OGL" value="0"/>
genxml: Add APIMODE_D3D missing enum values and improve consistency. Cc: "12.0" <mesa-stable@lists.freedesktop.org> Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-07-18 13:56:23 -07:00
<value name="APIMODE_D3D" value="1"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
</field>
genxml: Whitespace fixes Some field names had extra spaces and some had places where we should have had a space but didn't. Reviewed-by: Chad Versace <chadversary@chromium.org>
2017-03-24 14:26:20 -07:00
<field name="Viewport XY Clip Test Enable" start="92" end="92" type="bool"/>
<field name="Viewport Z Clip Test Enable" start="91" end="91" type="bool"/>
<field name="Guardband Clip Test Enable" start="90" end="90" type="bool"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="User Clip Distance Clip Test Enable Bitmask" start="80" end="87" type="uint"/>
<field name="Clip Mode" start="77" end="79" type="uint">
<value name="CLIPMODE_NORMAL" value="0"/>
<value name="reserved" value="2"/>
<value name="CLIPMODE_REJECT_ALL" value="3"/>
<value name="CLIPMODE_ACCEPT_ALL" value="4"/>
</field>
<field name="Perspective Divide Disable" start="73" end="73" type="bool"/>
<field name="Non-Perspective Barycentric Enable" start="72" end="72" type="bool"/>
<field name="Triangle Strip/List Provoking Vertex Select" start="68" end="69" type="uint">
<value name="Vertex 0" value="0"/>
<value name="Vertex 1" value="1"/>
<value name="Vertex 2" value="2"/>
</field>
<field name="Line Strip/List Provoking Vertex Select" start="66" end="67" type="uint">
<value name="Vertex 0" value="0"/>
<value name="Vertex 1" value="1"/>
</field>
<field name="Triangle Fan Provoking Vertex Select" start="64" end="65" type="uint">
<value name="Vertex 0" value="0"/>
<value name="Vertex 1" value="1"/>
<value name="Vertex 2" value="2"/>
</field>
<field name="Minimum Point Width" start="113" end="123" type="u8.3"/>
<field name="Maximum Point Width" start="102" end="112" type="u8.3"/>
genxml: Whitespace fixes Some field names had extra spaces and some had places where we should have had a space but didn't. Reviewed-by: Chad Versace <chadversary@chromium.org>
2017-03-24 14:26:20 -07:00
<field name="Force Zero RTA Index Enable" start="101" end="101" type="bool"/>
<field name="Maximum VP Index" start="96" end="99" type="uint"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
</instruction>
intel/batch_decoder: decoding of 3DSTATE_CONSTANT_BODY. SNB doesn't have a definition of 3DSTATE_CONSTANT_BODY, thats why we got segmentation fault when used INTEL_DEBUG=bat. Fixed by adding of 3DSTATE_CONSTANT_BODY into 3DSTATE_CONSTANT of VS, GS and PS structures. v2: added definition of 3DSTATE_CONSTANT_BODY to the gen6.xml Fixes: 169d8e011ae (intel: Fix 3DSTATE_CONSTANT buffer decoding.) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107190 Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-07-12 15:47:48 +03:00
<struct name="3DSTATE_CONSTANT_BODY" length="4">
<field name="Pointer to Constant Buffer 0" start="5" end="31" type="offset"/>
<field name="Constant Buffer 0 Read Length" start="0" end="4" type="uint"/>
<field name="Pointer to Constant Buffer 1" start="37" end="63" type="address"/>
<field name="Constant Buffer 1 Read Length" start="32" end="36" type="uint"/>
<field name="Pointer to Constant Buffer 2" start="69" end="95" type="address"/>
<field name="Constant Buffer 2 Read Length" start="64" end="68" type="uint"/>
<field name="Pointer to Constant Buffer 3" start="101" end="127" type="address"/>
<field name="Constant Buffer 3 Read Length" start="96" end="100" type="uint"/>
</struct>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_CONSTANT_GS" bias="2" length="5" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="22"/>
<field name="Buffer 3 Valid" start="15" end="15" type="bool"/>
<field name="Buffer 2 Valid" start="14" end="14" type="bool"/>
<field name="Buffer 1 Valid" start="13" end="13" type="bool"/>
<field name="Buffer 0 Valid" start="12" end="12" type="bool"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="MOCS" start="8" end="11" type="uint"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="DWord Length" start="0" end="7" type="uint" default="3"/>
intel/batch_decoder: decoding of 3DSTATE_CONSTANT_BODY. SNB doesn't have a definition of 3DSTATE_CONSTANT_BODY, thats why we got segmentation fault when used INTEL_DEBUG=bat. Fixed by adding of 3DSTATE_CONSTANT_BODY into 3DSTATE_CONSTANT of VS, GS and PS structures. v2: added definition of 3DSTATE_CONSTANT_BODY to the gen6.xml Fixes: 169d8e011ae (intel: Fix 3DSTATE_CONSTANT buffer decoding.) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107190 Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-07-12 15:47:48 +03:00
<field name="Constant Body" start="32" end="159" type="3DSTATE_CONSTANT_BODY"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_CONSTANT_PS" bias="2" length="5" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="23"/>
<field name="Buffer 3 Valid" start="15" end="15" type="bool"/>
<field name="Buffer 2 Valid" start="14" end="14" type="bool"/>
<field name="Buffer 1 Valid" start="13" end="13" type="bool"/>
<field name="Buffer 0 Valid" start="12" end="12" type="bool"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="MOCS" start="8" end="11" type="uint"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="DWord Length" start="0" end="7" type="uint" default="3"/>
intel/batch_decoder: decoding of 3DSTATE_CONSTANT_BODY. SNB doesn't have a definition of 3DSTATE_CONSTANT_BODY, thats why we got segmentation fault when used INTEL_DEBUG=bat. Fixed by adding of 3DSTATE_CONSTANT_BODY into 3DSTATE_CONSTANT of VS, GS and PS structures. v2: added definition of 3DSTATE_CONSTANT_BODY to the gen6.xml Fixes: 169d8e011ae (intel: Fix 3DSTATE_CONSTANT buffer decoding.) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107190 Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-07-12 15:47:48 +03:00
<field name="Constant Body" start="32" end="159" type="3DSTATE_CONSTANT_BODY"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_CONSTANT_VS" bias="2" length="5" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="21"/>
<field name="Buffer 3 Valid" start="15" end="15" type="bool"/>
<field name="Buffer 2 Valid" start="14" end="14" type="bool"/>
<field name="Buffer 1 Valid" start="13" end="13" type="bool"/>
<field name="Buffer 0 Valid" start="12" end="12" type="bool"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="MOCS" start="8" end="11" type="uint"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="DWord Length" start="0" end="7" type="uint" default="3"/>
intel/batch_decoder: decoding of 3DSTATE_CONSTANT_BODY. SNB doesn't have a definition of 3DSTATE_CONSTANT_BODY, thats why we got segmentation fault when used INTEL_DEBUG=bat. Fixed by adding of 3DSTATE_CONSTANT_BODY into 3DSTATE_CONSTANT of VS, GS and PS structures. v2: added definition of 3DSTATE_CONSTANT_BODY to the gen6.xml Fixes: 169d8e011ae (intel: Fix 3DSTATE_CONSTANT buffer decoding.) Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=107190 Signed-off-by: Sergii Romantsov <sergii.romantsov@globallogic.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-07-12 15:47:48 +03:00
<field name="Constant Body" start="32" end="159" type="3DSTATE_CONSTANT_BODY"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_DEPTH_BUFFER" bias="2" length="7" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="5"/>
<field name="DWord Length" start="0" end="7" type="uint" default="5"/>
<field name="Surface Type" start="61" end="63" type="uint">
<value name="SURFTYPE_1D" value="0"/>
<value name="SURFTYPE_2D" value="1"/>
<value name="SURFTYPE_3D" value="2"/>
<value name="SURFTYPE_CUBE" value="3"/>
<value name="SURFTYPE_NULL" value="7"/>
</field>
intel/genxml; Make "Tiled Surface" a boolean Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:50:02 -07:00
<field name="Tiled Surface" start="59" end="59" type="bool"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Tile Walk" start="58" end="58" type="uint">
<value name="TILEWALK_YMAJOR" value="1"/>
</field>
<field name="Software Tiled Rendering Mode" start="55" end="56" type="uint">
<value name="NORMAL" value="0"/>
<value name="STR1" value="1"/>
<value name="STR2" value="3"/>
</field>
<field name="Hierarchical Depth Buffer Enable" start="54" end="54" type="bool"/>
<field name="Separate Stencil Buffer Enable" start="53" end="53" type="bool"/>
<field name="Surface Format" start="50" end="52" type="uint">
<value name="D32_FLOAT_S8X24_UINT" value="0"/>
<value name="D32_FLOAT" value="1"/>
<value name="D24_UNORM_S8_UINT" value="2"/>
<value name="D24_UNORM_X8_UINT" value="3"/>
<value name="D16_UNORM" value="5"/>
</field>
<field name="Surface Pitch" start="32" end="48" type="uint"/>
<field name="Surface Base Address" start="64" end="95" type="address"/>
genxml/gen6: Remove a couple of bogus values Reviewed-by: Chad Versace <chadversary@chromium.org>
2017-03-24 14:10:23 -07:00
<field name="Height" start="115" end="127" type="uint"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Width" start="102" end="114" type="uint"/>
<field name="LOD" start="98" end="101" type="uint"/>
<field name="MIP Map Layout Mode" start="97" end="97" type="uint">
<value name="MIPLAYOUT_BELOW" value="0"/>
<value name="MIPLAYOUT_RIGHT" value="1"/>
</field>
genxml/gen6: Remove a couple of bogus values Reviewed-by: Chad Versace <chadversary@chromium.org>
2017-03-24 14:10:23 -07:00
<field name="Depth" start="149" end="159" type="uint"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Minimum Array Element" start="138" end="148" type="uint"/>
<field name="Render Target View Extent" start="129" end="137" type="uint"/>
<field name="Depth Coordinate Offset Y" start="176" end="191" type="int"/>
<field name="Depth Coordinate Offset X" start="160" end="175" type="int"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="MOCS" start="219" end="223" type="uint"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_DRAWING_RECTANGLE" bias="2" length="4" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="0"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
<field name="Clipped Drawing Rectangle Y Min" start="48" end="63" type="uint"/>
<field name="Clipped Drawing Rectangle X Min" start="32" end="47" type="uint"/>
<field name="Clipped Drawing Rectangle Y Max" start="80" end="95" type="uint"/>
<field name="Clipped Drawing Rectangle X Max" start="64" end="79" type="uint"/>
<field name="Drawing Rectangle Origin Y" start="112" end="127" type="int"/>
<field name="Drawing Rectangle Origin X" start="96" end="111" type="int"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_GS" bias="2" length="7" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="17"/>
<field name="DWord Length" start="0" end="7" type="uint" default="5"/>
<field name="Kernel Start Pointer" start="38" end="63" type="offset"/>
intel/genxml: Make "Single Program Flow" a boolean We also get rid of the "(SPF)" a few places. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:23:16 -07:00
<field name="Single Program Flow" start="95" end="95" type="bool"/>
intel/genxml: Make "Vector Mask Enable" a boolean We also get rid of the "(VME)" a few places Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:28:24 -07:00
<field name="Vector Mask Enable" start="94" end="94" type="bool"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Sampler Count" start="91" end="93" type="uint">
<value name="No Samplers" value="0"/>
<value name="1-4 Samplers" value="1"/>
<value name="5-8 Samplers" value="2"/>
<value name="9-12 Samplers" value="3"/>
<value name="13-16 Samplers" value="4"/>
</field>
<field name="Binding Table Entry Count" start="82" end="89" type="uint"/>
<field name="Thread Priority" start="81" end="81" type="uint">
<value name="Normal Priority" value="0"/>
<value name="High Priority" value="1"/>
</field>
<field name="Floating Point Mode" start="80" end="80" type="uint">
<value name="IEEE-754" value="0"/>
<value name="Alternate" value="1"/>
</field>
<field name="Illegal Opcode Exception Enable" start="77" end="77" type="bool"/>
<field name="Mask Stack Exception Enable" start="75" end="75" type="bool"/>
genxml: Whitespace fixes Some field names had extra spaces and some had places where we should have had a space but didn't. Reviewed-by: Chad Versace <chadversary@chromium.org>
2017-03-24 14:26:20 -07:00
<field name="Software Exception Enable" start="71" end="71" type="bool"/>
genxml: Make ScratchSpaceBasePointer an address instead of an offset While we're here, we also fixup MEDIA_VFE_STATE and rename the field in 3DSTATE_VS on gen6-7.5 to be consistent with the others. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Cc: "12.0" <mesa-stable@lists.freedesktop.org>
2016-06-16 14:58:25 -07:00
<field name="Scratch Space Base Pointer" start="106" end="127" type="address"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Per-Thread Scratch Space" start="96" end="99" type="uint"/>
<field name="Vertex URB Entry Read Length" start="139" end="144" type="uint"/>
<field name="Vertex URB Entry Read Offset" start="132" end="137" type="uint"/>
intel/genxml: Make some VS/GS fields consistent across gens We use the names from gen8+ Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2016-10-21 13:08:48 -07:00
<field name="Dispatch GRF Start Register For URB Data" start="128" end="131" type="uint"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Maximum Number of Threads" start="185" end="191" type="uint"/>
intel/genxml: Make some 3DSTATE_GS fields more consistent Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2016-11-12 09:05:59 -08:00
<field name="Statistics Enable" start="170" end="170" type="bool"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="SO Statistics Enable" start="169" end="169" type="bool"/>
<field name="Rendering Enabled" start="168" end="168" type="uint"/>
genxml: Make "Reorder Mode" fields consistent. Both GS and SOL have these fields. Some were ReorderEnable = true, some were ReorderMode = REORDER_TRAILING, and some were just TRAILING. Signed-off-by: Kenneth Graunke <kenneth@whitecape.org> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2016-09-07 13:46:57 -07:00
<field name="Reorder Mode" start="222" end="222" type="uint">
<value name="LEADING" value="0"/>
<value name="TRAILING" value="1"/>
</field>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Discard Adjacency" start="221" end="221" type="bool"/>
<field name="SVBI Payload Enable" start="220" end="220" type="bool"/>
<field name="SVBI Post-Increment Enable" start="219" end="219" type="bool"/>
<field name="SVBI Post-Increment Value" start="208" end="217" type="uint"/>
genxml: Rename "Function Enable" to "Enable". Rename that field name on genxml for: - 3DSTATE_GS - gen6+ - 3DSTATE_DS - gen7+ - 3DSTATE_HS - gen7+ Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-03-31 15:30:49 -07:00
<field name="Enable" start="207" end="207" type="bool"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_GS_SVB_INDEX" bias="2" length="7" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="11"/>
<field name="DWord Length" start="0" end="7" type="uint" default="5"/>
<field name="Index Number" start="61" end="62" type="uint"/>
<field name="Load Internal Vertex Count" start="32" end="32" type="uint"/>
<field name="Streamed Vertex Buffer Index" start="64" end="95" type="uint"/>
<field name="Maximum Index" start="96" end="127" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_HIER_DEPTH_BUFFER" bias="2" length="3" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="15"/>
genxml/gen6: Add a Surface Base Address field to HIER_DEPTH_BUFFER Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-08-05 16:26:57 -07:00
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="MOCS" start="57" end="60" type="uint"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Surface Pitch" start="32" end="48" type="uint"/>
genxml/gen6: Add a Surface Base Address field to HIER_DEPTH_BUFFER Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-08-05 16:26:57 -07:00
<field name="Surface Base Address" start="64" end="95" type="address"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_INDEX_BUFFER" bias="2" length="3" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="10"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="MOCS" start="12" end="15" type="uint"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Cut Index Enable" start="10" end="10" type="bool"/>
<field name="Index Format" start="8" end="9" type="uint" prefix="INDEX">
<value name="BYTE" value="0"/>
<value name="WORD" value="1"/>
<value name="DWORD" value="2"/>
</field>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Buffer Starting Address" start="32" end="63" type="address"/>
<field name="Buffer Ending Address" start="64" end="95" type="address"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_LINE_STIPPLE" bias="2" length="3" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="8"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Modify Enable (Current Repeat Counter, Current Stipple Index)" start="63" end="63" type="bool"/>
<field name="Current Repeat Counter" start="53" end="61" type="uint"/>
<field name="Current Stipple Index" start="48" end="51" type="uint"/>
<field name="Line Stipple Pattern" start="32" end="47" type="uint"/>
genxml: Update 3DSTATE_LINE_STIPPLE xml on gen6. From the PRM, Line Stipple Inverse Repeat Count is on dw2, bits 31:16, format U1.13. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-05-02 10:01:15 -07:00
<field name="Line Stipple Inverse Repeat Count" start="80" end="95" type="u1.13"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Line Stipple Repeat Count" start="64" end="72" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_MONOFILTER_SIZE" bias="2" length="2" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="17"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Monochrome Filter Width" start="35" end="37" type="uint"/>
<field name="Monochrome Filter Height" start="32" end="34" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_MULTISAMPLE" bias="2" length="3" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="13"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Pixel Location" start="36" end="36" type="uint">
genxml: Normalize xml for 3DSTATE_MULTISAMPLE. Name the options to "Pixel Location": - PIXLOC_CENTER -> CENTER - PIXLOC_UL_CORNER -> UL_CORNER Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-04-19 16:04:12 -07:00
<value name="CENTER" value="0"/>
<value name="UL_CORNER" value="1"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
</field>
<field name="Number of Multisamples" start="33" end="35" type="uint">
<value name="NUMSAMPLES_1" value="0"/>
<value name="NUMSAMPLES_4" value="2"/>
</field>
<field name="Sample3 X Offset" start="92" end="95" type="u0.4"/>
<field name="Sample3 Y Offset" start="88" end="91" type="u0.4"/>
<field name="Sample2 X Offset" start="84" end="87" type="u0.4"/>
<field name="Sample2 Y Offset" start="80" end="83" type="u0.4"/>
<field name="Sample1 X Offset" start="76" end="79" type="u0.4"/>
<field name="Sample1 Y Offset" start="72" end="75" type="u0.4"/>
<field name="Sample0 X Offset" start="68" end="71" type="u0.4"/>
<field name="Sample0 Y Offset" start="64" end="67" type="u0.4"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_POLY_STIPPLE_OFFSET" bias="2" length="2" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="6"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Polygon Stipple X Offset" start="40" end="44" type="uint"/>
<field name="Polygon Stipple Y Offset" start="32" end="36" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_POLY_STIPPLE_PATTERN" bias="2" length="33" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="7"/>
<field name="DWord Length" start="0" end="7" type="uint" default="31"/>
<group count="32" start="32" size="32">
<field name="Pattern Row" start="0" end="31" type="uint"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_SAMPLER_PALETTE_LOAD0" bias="2" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="2"/>
<field name="DWord Length" start="0" end="7" type="uint"/>
<group count="0" start="32" size="32">
<field name="Entry" start="0" end="31" type="PALETTE_ENTRY"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_SAMPLER_PALETTE_LOAD1" bias="2" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="12"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<group count="0" start="32" size="32">
<field name="Palette Alpha[0:N-1]" start="24" end="31" type="uint"/>
<field name="Palette Red[0:N-1]" start="16" end="23" type="uint"/>
<field name="Palette Green[0:N-1]" start="8" end="15" type="uint"/>
<field name="Palette Blue[0:N-1]" start="0" end="7" type="uint"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_SAMPLER_STATE_POINTERS" bias="2" length="4" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="2"/>
<field name="PS Sampler State Change" start="12" end="12" type="uint"/>
<field name="GS Sampler State Change" start="9" end="9" type="uint"/>
<field name="VS Sampler State Change" start="8" end="8" type="uint"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
<field name="Pointer to VS Sampler State" start="37" end="63" type="offset"/>
<field name="Pointer to GS Sampler State" start="69" end="95" type="offset"/>
<field name="Pointer to PS Sampler State" start="101" end="127" type="offset"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_SAMPLE_MASK" bias="2" length="2" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="24"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Sample Mask" start="32" end="35" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_SCISSOR_STATE_POINTERS" bias="2" length="2" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="15"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Scissor Rect Pointer" start="37" end="63" type="offset"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_SF" bias="2" length="20" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="19"/>
<field name="DWord Length" start="0" end="7" type="uint" default="18"/>
<field name="Number of SF Output Attributes" start="54" end="59" type="uint"/>
<field name="Attribute Swizzle Enable" start="53" end="53" type="bool"/>
<field name="Point Sprite Texture Coordinate Origin" start="52" end="52" type="uint">
<value name="UPPERLEFT" value="0"/>
<value name="LOWERLEFT" value="1"/>
</field>
<field name="Vertex URB Entry Read Length" start="43" end="47" type="uint"/>
<field name="Vertex URB Entry Read Offset" start="36" end="41" type="uint"/>
<field name="Legacy Global Depth Bias Enable" start="75" end="75" type="bool"/>
<field name="Statistics Enable" start="74" end="74" type="bool"/>
<field name="Global Depth Offset Enable Solid" start="73" end="73" type="bool"/>
<field name="Global Depth Offset Enable Wireframe" start="72" end="72" type="bool"/>
<field name="Global Depth Offset Enable Point" start="71" end="71" type="bool"/>
<field name="FrontFace Fill Mode" start="69" end="70" type="uint" prefix="FILL_MODE">
<value name="SOLID" value="0"/>
<value name="WIREFRAME" value="1"/>
<value name="POINT" value="2"/>
</field>
<field name="BackFace Fill Mode" start="67" end="68" type="uint" prefix="FILL_MODE">
<value name="SOLID" value="0"/>
<value name="WIREFRAME" value="1"/>
<value name="POINT" value="2"/>
</field>
<field name="Viewport Transform Enable" start="65" end="65" type="bool"/>
<field name="Front Winding" start="64" end="64" type="uint">
<value name="FRONTWINDING_CW" value="0"/>
<value name="FRONTWINDING_CCW" value="1"/>
</field>
genxml: Update xml for 3DSTATE_SF. - Normalize "Anti-Aliasing Enable" - Add "Multisample Rasterization Mode" constants - Rename "Use Point Width on Vertex" to "Vertex" - Rename "Use Point Width from State" to "State" Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-03-31 15:25:20 -07:00
<field name="Anti-Aliasing Enable" start="127" end="127" type="bool"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Cull Mode" start="125" end="126" type="uint" prefix="CULLMODE">
<value name="BOTH" value="0"/>
<value name="NONE" value="1"/>
<value name="FRONT" value="2"/>
<value name="BACK" value="3"/>
</field>
<field name="Line Width" start="114" end="123" type="u3.7"/>
<field name="Line End Cap Antialiasing Region Width" start="112" end="113" type="uint">
<value name="0.5 pixels" value="0"/>
<value name="1.0 pixels" value="1"/>
<value name="2.0 pixels" value="2"/>
<value name="4.0 pixels" value="3"/>
</field>
<field name="Scissor Rectangle Enable" start="107" end="107" type="bool"/>
genxml: Update xml for 3DSTATE_SF. - Normalize "Anti-Aliasing Enable" - Add "Multisample Rasterization Mode" constants - Rename "Use Point Width on Vertex" to "Vertex" - Rename "Use Point Width from State" to "State" Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-03-31 15:25:20 -07:00
<field name="Multisample Rasterization Mode" start="104" end="105" type="uint">
<value name="MSRASTMODE_OFF_PIXEL" value="0"/>
<value name="MSRASTMODE_OFF_PATTERN" value="1"/>
<value name="MSRASTMODE_ON_PIXEL" value="2"/>
<value name="MSRASTMODE_ON_PATTERN" value="3"/>
</field>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Last Pixel Enable" start="159" end="159" type="bool"/>
<field name="Triangle Strip/List Provoking Vertex Select" start="157" end="158" type="uint">
<value name="Vertex 0" value="0"/>
<value name="Vertex 1" value="1"/>
<value name="Vertex 2" value="2"/>
</field>
<field name="Line Strip/List Provoking Vertex Select" start="155" end="156" type="uint">
<value name="Vertex 0" value="0"/>
<value name="Vertex 1" value="1"/>
</field>
<field name="Triangle Fan Provoking Vertex Select" start="153" end="154" type="uint">
<value name="Vertex 0" value="0"/>
<value name="Vertex 1" value="1"/>
<value name="Vertex 2" value="2"/>
</field>
<field name="AA Line Distance Mode" start="142" end="142" type="uint">
<value name="AALINEDISTANCE_TRUE" value="1"/>
</field>
<field name="Vertex Sub Pixel Precision Select" start="140" end="140" type="uint">
<value name="8 Sub-Pixel Precision Bits" value="0"/>
<value name="4 Sub-Pixel Precision Bits" value="1"/>
</field>
genxml: Update xml for 3DSTATE_SF. - Normalize "Anti-Aliasing Enable" - Add "Multisample Rasterization Mode" constants - Rename "Use Point Width on Vertex" to "Vertex" - Rename "Use Point Width from State" to "State" Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-03-31 15:25:20 -07:00
<field name="Point Width Source" start="139" end="139" type="uint">
<value name="Vertex" value="0"/>
<value name="State" value="1"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
</field>
<field name="Point Width" start="128" end="138" type="u8.3"/>
<field name="Global Depth Offset Constant" start="160" end="191" type="float"/>
<field name="Global Depth Offset Scale" start="192" end="223" type="float"/>
<field name="Global Depth Offset Clamp" start="224" end="255" type="float"/>
genxml: Break output detail of 3DSTATE_SF on gen7 into a struct This makes it work like 3DSTATE_SBE[_SWIZ] on gen7+
2016-04-09 17:00:19 -07:00
<group count="16" start="256" size="16">
<field name="Attribute" start="0" end="15" type="SF_OUTPUT_ATTRIBUTE_DETAIL"/>
</group>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Point Sprite Texture Coordinate Enable" start="512" end="543" type="uint"/>
genxml: Fix the name of a 3DSTATE_SF/SBE field on gen6-7.5
2016-04-09 17:02:21 -07:00
<field name="Constant Interpolation Enable" start="544" end="575" type="uint"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Attribute 7 WrapShortest Enables" start="604" end="607" type="uint"/>
<field name="Attribute 6 WrapShortest Enables" start="600" end="603" type="uint"/>
<field name="Attribute 5 WrapShortest Enables" start="596" end="599" type="uint"/>
<field name="Attribute 4 WrapShortest Enables" start="592" end="595" type="uint"/>
<field name="Attribute 3 WrapShortest Enables" start="588" end="591" type="uint"/>
<field name="Attribute 2 WrapShortest Enables" start="584" end="587" type="uint"/>
<field name="Attribute 1 WrapShortest Enables" start="580" end="583" type="uint"/>
<field name="Attribute 0 WrapShortest Enables" start="576" end="579" type="uint"/>
<field name="Attribute 15 WrapShortest Enables" start="636" end="639" type="uint"/>
<field name="Attribute 14 WrapShortest Enables" start="632" end="635" type="uint"/>
<field name="Attribute 13 WrapShortest Enables" start="628" end="631" type="uint"/>
<field name="Attribute 12 WrapShortest Enables" start="624" end="627" type="uint"/>
<field name="Attribute 11 WrapShortest Enables" start="620" end="623" type="uint"/>
<field name="Attribute 10 WrapShortest Enables" start="616" end="619" type="uint"/>
<field name="Attribute 9 WrapShortest Enables" start="612" end="615" type="uint"/>
<field name="Attribute 8 WrapShortest Enables" start="608" end="611" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_STENCIL_BUFFER" bias="2" length="3" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="14"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
genxml: Consistently use a numeric "MOCS" field When we first started using genxml, we decided to represent MOCS as an actual structure, and pack values. However, in many places, it was more convenient to use a numeric value rather than treating it as a struct, so we added secondary setters in a bunch of places as well. We were not entirely consistent, either. Some places only had one. Gen6 had both kinds of setters for STATE_BASE_ADDRESS, but newer gens only had the struct-based setters. The names were sometimes "Constant Buffer Object Control State" instead of "Memory", making it harder to find. Many had prefixes like "Vertex Buffer MOCS"...in a vertex buffer packet...which is a bit redundant. On modern hardware, MOCS is simply an index into a table, but we were still carrying around the structure with an "Index to MOCS Table" field, in addition to the direct numeric setters. This is clunky - we really just want a number on new hardware. This patch eliminates the struct-based setters, and makes the numeric setters be consistently called "MOCS". We leave the struct definition around on Gen7-8 for reference purposes, but it is unused. v2: Drop bonus "Depth Buffer MOCS" fields on Gen7.5 and Gen9 Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2018-12-11 00:34:11 -08:00
<field name="MOCS" start="57" end="60" type="uint"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Surface Pitch" start="32" end="48" type="uint"/>
<field name="Surface Base Address" start="64" end="95" type="address"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_URB" bias="2" length="3" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="5"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="VS URB Entry Allocation Size" start="48" end="55" type="uint"/>
<field name="VS Number of URB Entries" start="32" end="47" type="uint"/>
<field name="GS Number of URB Entries" start="72" end="81" type="uint"/>
<field name="GS URB Entry Allocation Size" start="64" end="66" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_VERTEX_BUFFERS" bias="2" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="8"/>
<field name="DWord Length" start="0" end="7" type="uint" default="3"/>
<group count="0" start="32" size="128">
<field name="Vertex Buffer State" start="0" end="127" type="VERTEX_BUFFER_STATE"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_VERTEX_ELEMENTS" bias="2" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="9"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<group count="0" start="32" size="64">
<field name="Element" start="0" end="63" type="VERTEX_ELEMENT_STATE"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_VF_STATISTICS" bias="1" length="1" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="1"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="11"/>
<field name="Statistics Enable" start="0" end="0" type="bool"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_VIEWPORT_STATE_POINTERS" bias="2" length="4" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="13"/>
<field name="CC Viewport State Change" start="12" end="12" type="uint"/>
<field name="SF Viewport State Change" start="11" end="11" type="uint"/>
<field name="CLIP Viewport State Change" start="10" end="10" type="uint"/>
<field name="DWord Length" start="0" end="7" type="uint" default="2"/>
<field name="Pointer to CLIP_VIEWPORT" start="37" end="63" type="offset"/>
<field name="Pointer to SF_VIEWPORT" start="69" end="95" type="offset"/>
<field name="Pointer to CC_VIEWPORT" start="101" end="127" type="offset"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_VS" bias="2" length="6" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="16"/>
<field name="DWord Length" start="0" end="7" type="uint" default="4"/>
<field name="Kernel Start Pointer" start="38" end="63" type="offset"/>
<field name="Single Vertex Dispatch" start="95" end="95" type="bool"/>
intel/genxml: Make "Vector Mask Enable" a boolean We also get rid of the "(VME)" a few places Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:28:24 -07:00
<field name="Vector Mask Enable" start="94" end="94" type="bool"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Sampler Count" start="91" end="93" type="uint">
<value name="No Samplers" value="0"/>
<value name="1-4 Samplers" value="1"/>
<value name="5-8 Samplers" value="2"/>
<value name="9-12 Samplers" value="3"/>
<value name="13-16 Samplers" value="4"/>
</field>
<field name="Binding Table Entry Count" start="82" end="89" type="uint"/>
<field name="Floating Point Mode" start="80" end="80" type="uint">
<value name="IEEE-754" value="0"/>
<value name="Alternate" value="1"/>
</field>
<field name="Illegal Opcode Exception Enable" start="77" end="77" type="bool"/>
genxml: Whitespace fixes Some field names had extra spaces and some had places where we should have had a space but didn't. Reviewed-by: Chad Versace <chadversary@chromium.org>
2017-03-24 14:26:20 -07:00
<field name="Software Exception Enable" start="71" end="71" type="bool"/>
genxml: Make ScratchSpaceBasePointer an address instead of an offset While we're here, we also fixup MEDIA_VFE_STATE and rename the field in 3DSTATE_VS on gen6-7.5 to be consistent with the others. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Cc: "12.0" <mesa-stable@lists.freedesktop.org>
2016-06-16 14:58:25 -07:00
<field name="Scratch Space Base Pointer" start="106" end="127" type="address"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Per-Thread Scratch Space" start="96" end="99" type="uint"/>
intel/genxml: Make some VS/GS fields consistent across gens We use the names from gen8+ Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com> Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com>
2016-10-21 13:08:48 -07:00
<field name="Dispatch GRF Start Register For URB Data" start="148" end="152" type="uint"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Vertex URB Entry Read Length" start="139" end="144" type="uint"/>
<field name="Vertex URB Entry Read Offset" start="132" end="137" type="uint"/>
<field name="Maximum Number of Threads" start="185" end="191" type="uint"/>
<field name="Statistics Enable" start="170" end="170" type="bool"/>
<field name="Vertex Cache Disable" start="161" end="161" type="bool"/>
genxml: 3DSTATE_VS rename Function Enable to Enable. Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-03-22 16:26:07 -07:00
<field name="Enable" start="160" end="160" type="bool"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="3DSTATE_WM" bias="2" length="9" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="20"/>
genxml/gen6: Fix the length of 3DSTATE_WM Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-08-05 22:28:26 -07:00
<field name="DWord Length" start="0" end="7" type="uint" default="7"/>
genxml: Remove brackets from kernel start pointer names Newer Gens' names don't have the brackets. Having common names will make some later patches simpler. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2017-04-08 15:39:59 -07:00
<field name="Kernel Start Pointer 0" start="38" end="63" type="offset"/>
intel/genxml: Make "Single Program Flow" a boolean We also get rid of the "(SPF)" a few places. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:23:16 -07:00
<field name="Single Program Flow" start="95" end="95" type="bool"/>
intel/genxml: Make "Vector Mask Enable" a boolean We also get rid of the "(VME)" a few places Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:28:24 -07:00
<field name="Vector Mask Enable" start="94" end="94" type="bool"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Sampler Count" start="91" end="93" type="uint"/>
<field name="Binding Table Entry Count" start="82" end="89" type="uint"/>
<field name="Thread Priority" start="81" end="81" type="uint">
<value name="High" value="1"/>
</field>
intel/genxml: Use the same naming convention for Floating Point Mode. In newer gens, this field has a prefix and the non-IEEEE-745 mode is called "Alternate", instead of simply "Alt". Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-13 16:50:08 -07:00
<field name="Floating Point Mode" start="80" end="80" type="uint" prefix="FLOATING_POINT_MODE">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<value name="IEEE-745" value="0"/>
intel/genxml: Use the same naming convention for Floating Point Mode. In newer gens, this field has a prefix and the non-IEEEE-745 mode is called "Alternate", instead of simply "Alt". Signed-off-by: Rafael Antognolli <rafael.antognolli@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2017-06-13 16:50:08 -07:00
<value name="Alternate" value="1"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
</field>
<field name="Illegal Opcode Exception Enable" start="77" end="77" type="bool"/>
<field name="MaskStack Exception Enable" start="75" end="75" type="bool"/>
<field name="Software Exception Enable" start="71" end="71" type="bool"/>
genxml: Make ScratchSpaceBasePointer an address instead of an offset While we're here, we also fixup MEDIA_VFE_STATE and rename the field in 3DSTATE_VS on gen6-7.5 to be consistent with the others. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Cc: "12.0" <mesa-stable@lists.freedesktop.org>
2016-06-16 14:58:25 -07:00
<field name="Scratch Space Base Pointer" start="106" end="127" type="address"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Per Thread Scratch Space" start="96" end="99" type="uint"/>
<field name="Statistics Enable" start="159" end="159" type="bool"/>
<field name="Depth Buffer Clear" start="158" end="158" type="bool"/>
<field name="Depth Buffer Resolve Enable" start="156" end="156" type="bool"/>
<field name="Hierarchical Depth Buffer Resolve Enable" start="155" end="155" type="bool"/>
genxml: Replace "[N]" with "N" Reviewed-by: Chad Versace <chadversary@chromium.org>
2017-03-24 14:25:57 -07:00
<field name="Dispatch GRF Start Register For Constant/Setup Data 0" start="144" end="150" type="uint"/>
<field name="Dispatch GRF Start Register For Constant/Setup Data 1" start="136" end="142" type="uint"/>
<field name="Dispatch GRF Start Register For Constant/Setup Data 2" start="128" end="134" type="uint"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Maximum Number of Threads" start="185" end="191" type="uint"/>
<field name="Legacy Diamond Line Rasterization" start="183" end="183" type="bool"/>
intel/genxml: Make 3DSTATE_WM more consistent across gens Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-11-12 10:46:02 -08:00
<field name="Pixel Shader Kills Pixel" start="182" end="182" type="bool"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Pixel Shader Computed Depth" start="181" end="181" type="bool"/>
<field name="Pixel Shader Uses Source Depth" start="180" end="180" type="bool"/>
<field name="Thread Dispatch Enable" start="179" end="179" type="bool"/>
intel/genxml: Make 3DSTATE_WM more consistent across gens Reviewed-by: Kristian H. Kristensen <hoegsberg@google.com> Reviewed-by: Timothy Arceri <timothy.arceri@collabora.com>
2016-11-12 10:46:02 -08:00
<field name="Line End Cap Antialiasing Region Width" start="176" end="177" type="uint">
<value name="0.5 pixels" value="0"/>
<value name="1.0 pixels" value="1"/>
<value name="2.0 pixels" value="2"/>
<value name="4.0 pixels" value="3"/>
</field>
<field name="Line Antialiasing Region Width" start="174" end="175" type="uint">
<value name="0.5 pixels" value="0"/>
<value name="1.0 pixels" value="1"/>
<value name="2.0 pixels" value="2"/>
<value name="4.0 pixels" value="3"/>
</field>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Polygon Stipple Enable" start="173" end="173" type="bool"/>
<field name="Line Stipple Enable" start="171" end="171" type="bool"/>
<field name="oMask Present to RenderTarget" start="169" end="169" type="bool"/>
<field name="Pixel Shader Uses Source W" start="168" end="168" type="bool"/>
<field name="Dual Source Blend Enable" start="167" end="167" type="bool"/>
<field name="32 Pixel Dispatch Enable" start="162" end="162" type="bool"/>
<field name="16 Pixel Dispatch Enable" start="161" end="161" type="bool"/>
<field name="8 Pixel Dispatch Enable" start="160" end="160" type="bool"/>
<field name="Number of SF Output Attributes" start="212" end="217" type="uint"/>
<field name="Position XY Offset Select" start="210" end="211" type="uint">
<value name="POSOFFSET_NONE" value="0"/>
<value name="POSOFFSET_CENTROID" value="2"/>
<value name="POSOFFSET_SAMPLE" value="3"/>
</field>
<field name="Position ZW Interpolation Mode" start="208" end="209" type="uint">
<value name="INTERP_PIXEL" value="0"/>
<value name="INTERP_CENTROID" value="2"/>
<value name="INTERP_SAMPLE" value="3"/>
</field>
genxml: Add values for Barycentric Interpolation Mode Signed-off-by: Kristian H. Kristensen <hoegsberg@gmail.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net>
2016-11-14 21:10:11 -08:00
<field name="Barycentric Interpolation Mode" start="202" end="207" type="uint">
<value name="BIM_PERSPECTIVE_PIXEL" value="1"/>
<value name="BIM_PERSPECTIVE_CENTROID" value ="2"/>
<value name="BIM_PERSPECTIVE_SAMPLE" value="4"/>
<value name="BIM_LINEAR_PIXEL" value="8"/>
<value name="BIM_LINEAR_CENTROID" value="16"/>
<value name="BIM_LINEAR_SAMPLE" value="32"/>
</field>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Point Rasterization Rule" start="201" end="201" type="uint">
<value name="RASTRULE_UPPER_LEFT" value="0"/>
<value name="RASTRULE_UPPER_RIGHT" value="1"/>
</field>
<field name="Multisample Rasterization Mode" start="193" end="194" type="uint">
<value name="MSRASTMODE_OFF_PIXEL" value="0"/>
<value name="MSRASTMODE_OFF_PATTERN" value="1"/>
<value name="MSRASTMODE_ON_PIXEL" value="2"/>
<value name="MSRASTMODE_ON_PATTERN" value="3"/>
</field>
<field name="Multisample Dispatch Mode" start="192" end="192" type="uint">
<value name="MSDISPMODE_PERSAMPLE" value="0"/>
<value name="MSDISPMODE_PERPIXEL" value="1"/>
</field>
genxml: Remove brackets from kernel start pointer names Newer Gens' names don't have the brackets. Having common names will make some later patches simpler. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Rafael Antognolli <rafael.antognolli@intel.com>
2017-04-08 15:39:59 -07:00
<field name="Kernel Start Pointer 1" start="230" end="255" type="offset"/>
<field name="Kernel Start Pointer 2" start="262" end="287" type="offset"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="MEDIA_CURBE_LOAD" bias="2" length="4" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode" start="16" end="23" type="uint" default="1"/>
<field name="DWord Length" start="0" end="15" type="uint" default="2"/>
<field name="CURBE Total Data Length" start="64" end="80" type="uint"/>
<field name="CURBE Data Start Address" start="96" end="127" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="MEDIA_GATEWAY_STATE" bias="2" length="2" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode" start="16" end="23" type="uint" default="3"/>
<field name="DWord Length" start="0" end="15" type="uint" default="0"/>
<field name="BarrierID" start="48" end="55" type="uint"/>
<field name="Barrier.Byte" start="40" end="47" type="uint"/>
<field name="Barrier.ThreadCount" start="32" end="39" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="MEDIA_INTERFACE_DESCRIPTOR_LOAD" bias="2" length="4" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode" start="16" end="23" type="uint" default="2"/>
<field name="DWord Length" start="0" end="15" type="uint" default="2"/>
<field name="Interface Descriptor Total Length" start="64" end="80" type="uint"/>
<field name="Interface Descriptor Data Start Address" start="96" end="127" type="offset"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="MEDIA_OBJECT" bias="2" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Media Command Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="Media Command Sub-Opcode" start="16" end="23" type="uint" default="0"/>
<field name="DWord Length" start="0" end="15" type="uint" default="4"/>
<field name="Interface Descriptor Offset" start="32" end="36" type="uint"/>
<field name="Children Present" start="95" end="95" type="bool"/>
<field name="Thread Synchronization" start="88" end="88" type="uint">
<value name="No thread synchronization" value="0"/>
<value name="Thread dispatch is synchronized by the 'spawn root thread' message" value="1"/>
</field>
<field name="Use Scoreboard" start="85" end="85" type="uint">
<value name="Not using scoreboard" value="0"/>
<value name="Using scoreboard" value="1"/>
</field>
<field name="Indirect Data Length" start="64" end="80" type="uint"/>
<field name="Indirect Data Start Address" start="96" end="127" type="address"/>
<field name="Scoredboard Y" start="144" end="152" type="uint"/>
<field name="Scoreboard X" start="128" end="136" type="uint"/>
<field name="Scoreboard Color" start="176" end="179" type="uint"/>
<field name="Scoreboard Mask" start="160" end="167" type="uint"/>
<group count="0" start="192" size="32">
<field name="Inline Data" start="0" end="31" type="uint"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="MEDIA_OBJECT_PRT" bias="2" length="16" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode" start="16" end="23" type="uint" default="2"/>
<field name="DWord Length" start="0" end="15" type="uint" default="14"/>
<field name="Interface Descriptor Offset" start="32" end="36" type="uint"/>
<field name="Children Present" start="95" end="95" type="bool"/>
<field name="PRT_Fence Needed" start="87" end="87" type="bool"/>
<field name="PRT_FenceType" start="86" end="86" type="uint">
<value name="Root thread queue" value="0"/>
<value name="VFE state flush" value="1"/>
</field>
<group count="12" start="128" size="32">
<field name="Inline Data" start="0" end="31" type="uint"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="MEDIA_OBJECT_WALKER" bias="2" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode" start="16" end="23" type="uint" default="3"/>
<field name="DWord Length" start="0" end="15" type="uint" default="15"/>
<field name="Interface Descriptor Offset" start="32" end="36" type="uint"/>
<field name="Children Present" start="95" end="95" type="uint"/>
<field name="Thread Synchronization" start="88" end="88" type="uint">
<value name="No thread synchronization" value="0"/>
<value name="Thread dispatch is synchronized by the 'spawn root thread' message" value="1"/>
</field>
<field name="Use Scoreboard" start="85" end="85" type="uint">
<value name="Not using scoreboard" value="0"/>
<value name="Using scoreboard" value="1"/>
</field>
<field name="Indirect Data Length" start="64" end="80" type="uint"/>
<field name="Indirect Data Start Address" start="96" end="127" type="offset"/>
<field name="Scoreboard Mask" start="160" end="167" type="uint"/>
<field name="Dual Mode" start="223" end="223" type="uint"/>
<field name="Repel" start="222" end="222" type="uint"/>
<field name="Color Count Minus One" start="216" end="219" type="uint"/>
<field name="Middle Loop Extra Steps" start="208" end="212" type="uint"/>
<field name="Local Mid-Loop Unit Y" start="204" end="205" type="int"/>
<field name="Mid-Loop Unit X" start="200" end="201" type="int"/>
<field name="Global Loop Exec Count" start="240" end="249" type="uint"/>
<field name="Local Loop Exec Count" start="224" end="233" type="uint"/>
<field name="Block Resolution Y" start="272" end="280" type="uint"/>
<field name="Block Resolution X" start="256" end="264" type="uint"/>
<field name="Local Start Y" start="304" end="312" type="uint"/>
<field name="Local Start X" start="288" end="296" type="uint"/>
<field name="Local End Y" start="336" end="344" type="uint"/>
<field name="Local End X" start="320" end="328" type="uint"/>
<field name="Local Outer Loop Stride Y" start="368" end="377" type="int"/>
<field name="Local Outer Loop Stride X" start="352" end="361" type="int"/>
<field name="Local Inner Loop Unit Y" start="400" end="409" type="int"/>
<field name="Local Inner Loop Unit X" start="384" end="393" type="int"/>
<field name="Global Resolution Y" start="432" end="440" type="uint"/>
<field name="Global Resolution X" start="416" end="424" type="uint"/>
<field name="Global Start Y" start="464" end="473" type="int"/>
<field name="Global Start X" start="448" end="457" type="int"/>
<field name="Global Outer Loop Stride Y" start="496" end="505" type="int"/>
<field name="Global Outer Loop Stride X" start="480" end="489" type="int"/>
<field name="Global Inner Loop Unit Y" start="528" end="537" type="int"/>
<field name="Global Inner Loop Unit X" start="512" end="521" type="int"/>
<group count="0" start="544" size="32">
<field name="Inline Data" start="0" end="31" type="uint"/>
</group>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="MEDIA_STATE_FLUSH" bias="2" length="2" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode" start="16" end="23" type="uint" default="4"/>
<field name="DWord Length" start="0" end="15" type="uint" default="0"/>
<field name="Thread Count WaterMark" start="48" end="55" type="uint"/>
<field name="Barrier Mask" start="32" end="47" type="uint">
<value name="Not Waiting" value="0"/>
<value name="Waiting" value="1"/>
</field>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="MEDIA_VFE_STATE" bias="2" length="8" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode" start="16" end="23" type="uint" default="0"/>
<field name="DWord Length" start="0" end="15" type="uint" default="6"/>
genxml: Make ScratchSpaceBasePointer an address instead of an offset While we're here, we also fixup MEDIA_VFE_STATE and rename the field in 3DSTATE_VS on gen6-7.5 to be consistent with the others. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Cc: "12.0" <mesa-stable@lists.freedesktop.org>
2016-06-16 14:58:25 -07:00
<field name="Scratch Space Base Pointer" start="42" end="63" type="address"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Per Thread Scratch Space" start="32" end="35" type="uint"/>
<field name="Maximum Number of Threads" start="80" end="95" type="uint"/>
<field name="Number of URB Entries" start="72" end="79" type="uint"/>
<field name="Reset Gateway Timer" start="71" end="71" type="uint">
<value name="Maintaining the existing timestamp state" value="0"/>
<value name="Resetting relative timer and latching the global timestamp" value="1"/>
</field>
<field name="Bypass Gateway Control" start="70" end="70" type="uint">
<value name="Maintaining OpenGateway/ForwardMsg/CloseGateway protocol (legacy mode)" value="0"/>
<value name="Bypassing OpenGateway/CloseGateway protocol" value="1"/>
</field>
<field name="Fast Preempt" start="69" end="69" type="uint">
<value name="Preempt only _PRT" value="0"/>
</field>
<field name="URB Entry Allocation Size" start="144" end="159" type="uint"/>
<field name="CURBE Allocation Size" start="128" end="143" type="uint"/>
<field name="Scoreboard Enable" start="191" end="191" type="uint">
<value name="Scoreboard disabled" value="0"/>
<value name="Scoreboard enabled" value="1"/>
</field>
<field name="Scoreboard Type" start="190" end="190" type="uint">
<value name="Stalling Scoreboard" value="0"/>
</field>
<field name="Scoreboard Mask" start="160" end="167" type="uint"/>
<field name="Scoreboard 3 Delta Y" start="220" end="223" type="int"/>
<field name="Scoreboard 3 Delta X" start="216" end="219" type="int"/>
<field name="Scoreboard 2 Delta Y" start="212" end="215" type="int"/>
<field name="Scoreboard 2 Delta X" start="208" end="211" type="int"/>
<field name="Scoreboard 1 Delta Y" start="204" end="207" type="int"/>
<field name="Scoreboard 1 Delta X" start="200" end="203" type="int"/>
<field name="Scoreboard 0 Delta Y" start="196" end="199" type="int"/>
<field name="Scoreboard 0 Delta X" start="192" end="195" type="int"/>
<field name="Scoreboard 7 Delta Y" start="252" end="255" type="int"/>
<field name="Scoreboard 7 Delta X" start="248" end="251" type="int"/>
<field name="Scoreboard 6 Delta Y" start="244" end="247" type="int"/>
<field name="Scoreboard 6 Delta X" start="240" end="243" type="int"/>
<field name="Scoreboard 5 Delta Y" start="236" end="239" type="int"/>
<field name="Scoreboard 5 Delta X" start="232" end="235" type="int"/>
<field name="Scoreboard 4 Delta Y" start="228" end="231" type="int"/>
<field name="Scoreboard 4 Delta X" start="224" end="227" type="int"/>
</instruction>
intel/genxml: Media instructions and structures for gen6 v2: Fixed MI_WAIT_FOR_EVENT to be for blitter and video also Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-01-16 13:52:11 +02:00
<instruction name="MFC_AVC_FQM_STATE" bias="2" length="113" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="2"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="2"/>
<field name="DWord Length" start="0" end="11" type="uint" default="111"/>
<group count="8" start="32" size="32">
<field name="Luma4x4 Intra InvWeightScale" start="0" end="31" type="uint"/>
</group>
<group count="8" start="288" size="32">
<field name="Cb4x4 Intra InvWeightScale" start="0" end="31" type="uint"/>
</group>
<group count="8" start="544" size="32">
<field name="Cr4x4 Intra InvWeightScale" start="0" end="31" type="uint"/>
</group>
<group count="6" start="800" size="32">
<field name="Luma4x4 Inter InvWeightScale" start="0" end="31" type="uint"/>
</group>
<group count="10" start="992" size="32">
<field name="Cb4x4 Inter InvWeightScale" start="0" end="31" type="uint"/>
</group>
<group count="8" start="1312" size="32">
<field name="Cr4x4 Inter InvWeightScale" start="0" end="31" type="uint"/>
</group>
<group count="32" start="1568" size="32">
<field name="Luma8x8 Intra InvWeightScale" start="0" end="31" type="uint"/>
</group>
<group count="32" start="2592" size="32">
<field name="Luma8x8 Inter InvWeightScale" start="0" end="31" type="uint"/>
</group>
</instruction>
<instruction name="MFC_AVC_PAK_INSERT_OBJECT" bias="2" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="2"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="8"/>
<field name="DWord Length" start="0" end="11" type="uint" default="0"/>
<field name="Data Byte Offset" start="48" end="49" type="uint"/>
<field name="Data Bits In Last DW" start="40" end="45" type="uint"/>
<field name="Skip Emulation Byte Count" start="36" end="39" type="uint"/>
<field name="Emulation Byte Bits Insert Enable" start="35" end="35" type="bool"/>
<field name="Last Header" start="34" end="34" type="bool"/>
<field name="End of Slice" start="33" end="33" type="bool"/>
<field name="Bitstream Start Reset" start="32" end="32" type="bool"/>
<group count="0" start="64" size="32">
<field name="Insert Data PayLoad" start="0" end="31" type="uint"/>
</group>
</instruction>
<instruction name="MFC_AVC_PAK_OBJECT" bias="2" length="11" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="2"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="9"/>
<field name="DWord Length" start="0" end="11" type="uint" default="9"/>
<field name="Indirect PAK-MV Data Length" start="32" end="41" type="uint"/>
<field name="Indirect PAK-MV Data Start Address Offset" start="64" end="92" type="offset"/>
<group count="8" start="96" size="32">
<field name="Inline Data" start="0" end="31" type="uint"/>
</group>
</instruction>
<instruction name="MFC_STITCH_OBJECT" bias="2" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="2"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="10"/>
<field name="DWord Length" start="0" end="11" type="uint"/>
<field name="Src Data Starting Byte Offset" start="48" end="49" type="uint"/>
<field name="SrC Data Ending Bit Inclusion" start="40" end="45" type="uint"/>
<field name="Last Src Header Data Insert Command" start="34" end="34" type="bool"/>
<field name="Last Dst Data Insert Command" start="33" end="33" type="bool"/>
<field name="Indirect Data Length" start="64" end="82" type="uint"/>
<field name="Indirect Data Start Address" start="96" end="127" type="address"/>
<group count="0" start="128" size="32">
<field name="Insert Data PayLoad" start="0" end="31" type="uint"/>
</group>
</instruction>
<instruction name="MFD_AVC_BSD_OBJECT" bias="2" length="6" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="1"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="8"/>
<field name="DWord Length" start="0" end="11" type="uint" default="4"/>
<field name="Indirect BSD Data Length" start="32" end="53" type="uint"/>
<field name="Indirect BSD Data Start Address" start="64" end="92" type="address"/>
<group count="3" start="96" size="32">
<field name="Inline Data" start="0" end="31" type="uint"/>
</group>
</instruction>
<instruction name="MFD_IT_OBJECT" bias="2" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="1"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="9"/>
<field name="DWord Length" start="0" end="11" type="uint" default="12"/>
<field name="Indirect IT-MV Data Length" start="32" end="41" type="uint"/>
<field name="Indirect IT-MV Data Start Address Offset" start="64" end="92" type="offset"/>
<field name="Indirect IT-COEFF Data Length" start="96" end="107" type="uint"/>
<field name="Indirect IT-COEFF Data Start Address Offset" start="128" end="156" type="offset"/>
<field name="Indirect IT-DBLK Control Data Length" start="160" end="165" type="uint"/>
<field name="Indirect IT-DBLK Control Data Start Address Offset" start="192" end="220" type="offset"/>
<group count="0" start="224" size="32">
<field name="Inline Data" start="0" end="31" type="uint"/>
</group>
</instruction>
<instruction name="MFD_MPEG2_BSD_OBJECT" bias="2" length="5" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="3"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="1"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="8"/>
<field name="DWord Length" start="0" end="11" type="uint" default="3"/>
<field name="Indirect Data Length" start="32" end="48" type="uint"/>
<field name="Indirect Data Start Address" start="64" end="92" type="address"/>
<group count="2" start="96" size="32">
<field name="Inline Data" start="0" end="31" type="uint"/>
</group>
</instruction>
<instruction name="MFD_VC1_BSD_OBJECT" bias="2" length="4" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="2"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="1"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="8"/>
<field name="DWord Length" start="0" end="11" type="uint" default="2"/>
<field name="Indirect Data Length" start="32" end="53" type="uint"/>
<field name="Indirect Data Start Address" start="64" end="92" type="address"/>
<field name="Slice Start Vertical Position" start="120" end="127" type="uint"/>
<field name="Next Slice Start Vertical Position" start="112" end="119" type="uint"/>
<field name="First MB Bit Offset" start="96" end="98" type="uint"/>
</instruction>
<instruction name="MFX_AVC_DIRECTMODE_STATE" bias="2" length="69" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="2"/>
<field name="DWord Length" start="0" end="11" type="uint" default="67"/>
<group count="32" start="32" size="32">
<field name="Direct MV Buffer - Address" start="6" end="31" type="address"/>
<field name="Direct MV Buffer - Arbitration Priority Control" start="4" end="5" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Direct MV Buffer - Graphics Data Type" start="2" end="2" type="uint"/>
<field name="Direct MV Buffer - Cacheability Control" start="0" end="1" type="uint">
<value name="GTT entry" value="0"/>
<value name="Not in LLC or MLC" value="1"/>
<value name="In LLC but not MLC" value="2"/>
<value name="Both LLC and MLC" value="3"/>
</field>
</group>
<group count="2" start="1056" size="32">
<field name="Direct MV Buffer (Write) - Address" start="6" end="31" type="address"/>
<field name="Direct MV Buffer (Write) - Arbitration Priority Control" start="4" end="5" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Direct MV Buffer (Write) - Graphics Data Type" start="2" end="2" type="uint"/>
<field name="Direct MV Buffer (Write) - Cacheability Control" start="0" end="1" type="uint">
<value name="GTT entry" value="0"/>
<value name="Not in LLC or MLC" value="1"/>
<value name="In LLC but not MLC" value="2"/>
<value name="Both LLC and MLC" value="3"/>
</field>
</group>
<group count="34" start="1120" size="32">
<field name="POC List" start="0" end="31" type="uint"/>
</group>
</instruction>
<instruction name="MFX_AVC_IMG_STATE" bias="2" length="13" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="0"/>
<field name="DWord Length" start="0" end="11" type="uint" default="11"/>
<field name="Frame Size" start="32" end="47" type="uint"/>
<field name="Frame Height" start="80" end="87" type="uint"/>
<field name="Frame Width" start="64" end="71" type="uint"/>
<field name="Second Chroma QP Offset" start="120" end="124" type="uint"/>
<field name="Intra MB Conformance" start="110" end="110" type="bool"/>
<field name="Inter MB Conformance" start="109" end="109" type="bool"/>
<field name="Monochrome PWT Decoding Mode" start="108" end="108" type="bool"/>
<field name="QM Present" start="106" end="106" type="bool"/>
<field name="Image Structure" start="104" end="105" type="uint">
<value name="Frame Picture" value="0"/>
<value name="Top Field Picture" value="1"/>
<value name="Bottom Field Picture" value="3"/>
<value name="Invalid, not allowed" value="2"/>
</field>
<field name="Current Decoded Image Frame Store ID" start="96" end="103" type="uint"/>
<field name="Minimum Frame Size" start="144" end="159" type="uint"/>
<field name="MB Status Read" start="143" end="143" type="bool"/>
<field name="Load Bitstream Pointer Per Slice" start="142" end="142" type="bool"/>
<field name="MV Unpacked Enable" start="140" end="140" type="bool"/>
<field name="Chroma Format IDC" start="138" end="139" type="uint">
<value name="Monochrome picture" value="0"/>
<value name="4:2:0 picture" value="1"/>
<value name="4:2:2 picture (not supported)" value="2"/>
<value name="4:4:4 picture (not supported)" value="3"/>
</field>
<field name="Entropy Coding" start="135" end="135" type="bool"/>
<field name="Non-Reference Picture" start="134" end="134" type="bool"/>
<field name="Constrained Intra Prediction" start="133" end="133" type="bool"/>
<field name="Direct 8x8 Inference" start="132" end="132" type="bool"/>
<field name="8x8 IDCT Transform Mode" start="131" end="131" type="bool"/>
<field name="Frame MB Only" start="130" end="130" type="bool"/>
<field name="MBAFF Mode" start="129" end="129" type="bool"/>
<field name="Field Picture" start="128" end="128" type="bool"/>
<field name="Frame Size Rate Control" start="176" end="176" type="bool"/>
<field name="Inter MB Force CBP to Zero Control" start="172" end="172" type="bool"/>
<field name="MB Level Rate Control" start="169" end="169" type="bool"/>
<field name="Force IPCM Control" start="167" end="167" type="bool"/>
<field name="Frame Bitrate Min Report" start="163" end="163" type="bool"/>
<field name="Frame Bitrate Max Report" start="162" end="162" type="bool"/>
<field name="Inter MB Max Bit Control" start="161" end="161" type="bool"/>
<field name="Intra MB Max Bit Control" start="160" end="160" type="bool"/>
<field name="Inter MB Conformance Max Size" start="208" end="219" type="uint"/>
<field name="Intra MB Conformance Max Size" start="192" end="203" type="uint"/>
<field name="Slice Delta QP Max[3]" start="280" end="287" type="int"/>
<field name="Slice Delta QP Max[2]" start="272" end="279" type="int"/>
<field name="Slice Delta QP Max[1]" start="264" end="271" type="int"/>
<field name="Slice Delta QP Max[0]" start="256" end="263" type="int"/>
<field name="Slice Delta QP Min[3]" start="312" end="319" type="int"/>
<field name="Slice Delta QP Min[2]" start="304" end="311" type="int"/>
<field name="Slice Delta QP Min[1]" start="296" end="303" type="int"/>
<field name="Slice Delta QP Min[0]" start="288" end="295" type="int"/>
<field name="Frame Bitrate Max Unit" start="351" end="351" type="uint"/>
<field name="Frame Bitrate Max" start="336" end="347" type="uint"/>
<field name="Frame Bitrate Min Unit" start="335" end="335" type="uint"/>
<field name="Frame Bitrate Min" start="320" end="331" type="uint"/>
<field name="Frame Bitrate Max Delta" start="368" end="379" type="uint"/>
<field name="Frame Bitrate Min Delta" start="352" end="363" type="uint"/>
</instruction>
<instruction name="MFX_AVC_QM_STATE" bias="2" length="2" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="1"/>
<field name="DWord Length" start="0" end="11" type="uint" default="0"/>
<field name="Use built-in Default QM Flags for the current Slice" start="40" end="47" type="uint"/>
<field name="QM List Present Flags for the current Slice" start="32" end="39" type="uint"/>
<group count="4" start="64" size="32">
<field name="Luma4x4 Intra Weight Scale" start="0" end="31" type="uint"/>
</group>
<group count="4" start="192" size="32">
<field name="Cb4x4 Intra Weight Scale" start="0" end="31" type="uint"/>
</group>
<group count="4" start="320" size="32">
<field name="Cr4x4 Intra Weight Scale" start="0" end="31" type="uint"/>
</group>
<group count="4" start="448" size="32">
<field name="Luma4x4 Inter Weight Scale" start="0" end="31" type="uint"/>
</group>
<group count="4" start="576" size="32">
<field name="Cb4x4 Inter Weight Scale" start="0" end="31" type="uint"/>
</group>
<group count="4" start="704" size="32">
<field name="Cr4x4 Inter Weight Scale" start="0" end="31" type="uint"/>
</group>
<group count="4" start="832" size="128">
<field name="Luma8x8 Intra Weight Scale" start="0" end="127" type="uint"/>
</group>
<group count="4" start="1344" size="128">
<field name="Luma8x8 Inter Weight Scale" start="0" end="127" type="uint"/>
</group>
</instruction>
<instruction name="MFX_AVC_REF_IDX_STATE" bias="2" length="10" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="4"/>
<field name="DWord Length" start="0" end="11" type="uint" default="8"/>
<field name="Reference Picture List Select" start="32" end="32" type="uint"/>
<group count="32" start="64" size="8">
<field name="Reference List Entry" start="0" end="7" type="uint"/>
</group>
</instruction>
<instruction name="MFX_AVC_SLICE_STATE" bias="2" length="10" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="3"/>
<field name="DWord Length" start="0" end="11" type="uint" default="8"/>
<field name="Slice Type" start="32" end="35" type="uint">
<value name="P Slice" value="0"/>
<value name="B Slice" value="1"/>
<value name="I Slice" value="2"/>
</field>
<field name="Number of Reference Pictures in Inter-prediction List 1" start="88" end="93" type="uint"/>
<field name="Number of Reference Pictures in Inter-prediction List 0" start="80" end="85" type="uint"/>
<field name="Log2 Weight Denominator Chroma" start="72" end="74" type="uint"/>
<field name="Log2 Weight Denominator Luma" start="64" end="66" type="uint"/>
<field name="Weighted Prediction Indicator" start="126" end="127" type="uint"/>
<field name="Direct Prediction Type" start="125" end="125" type="uint">
<value name="Temporal" value="0"/>
<value name="Spatial" value="1"/>
</field>
<field name="Disable Deblocking Filter Indicator" start="123" end="124" type="uint"/>
<field name="CABAC Init IDC" start="120" end="121" type="uint"/>
<field name="Slice Quantization Parameter" start="112" end="117" type="uint"/>
<field name="Slice Beta Offset Div2" start="104" end="107" type="int"/>
<field name="Slice Alpha C0 Offset Div2" start="96" end="99" type="int"/>
<field name="Slice Vertical Position" start="152" end="159" type="uint"/>
<field name="Slice Horizontal Position" start="144" end="151" type="uint"/>
<field name="Slice Start MB Number" start="128" end="142" type="uint"/>
<field name="Next Slice Vertical Position" start="176" end="183" type="uint"/>
<field name="Next Slice Horizontal Position" start="160" end="167" type="uint"/>
<field name="Rate Control Counter Enable" start="223" end="223" type="bool"/>
<field name="Reset Rate Control Counter" start="222" end="222" type="bool"/>
<field name="Rate Control Triggle Mode" start="220" end="221" type="uint">
<value name="Always Rate Control" value="0"/>
<value name="Gentle Rate Control" value="1"/>
<value name="Loose Rate Control" value="2"/>
</field>
<field name="Rate Control Stable Tolerance" start="216" end="219" type="uint"/>
<field name="Rate Control Panic Enable" start="215" end="215" type="bool"/>
<field name="Rate Control Panic Type" start="214" end="214" type="uint">
<value name="QP Panic" value="0"/>
<value name="CBP Panic" value="1"/>
</field>
<field name="MB Type Direct Conversion Disable" start="213" end="213" type="bool"/>
<field name="MB Type Skip Conversion Disable" start="212" end="212" type="bool"/>
<field name="Last Slice Group" start="211" end="211" type="bool"/>
<field name="Header Insertion Present" start="209" end="209" type="bool"/>
<field name="Slice Data Insertion Present" start="208" end="208" type="bool"/>
<field name="Tail Insertion Present" start="207" end="207" type="bool"/>
<field name="Emulation Byte Slice Insert Enable" start="205" end="205" type="bool"/>
<field name="CABAC Zero Word Insertion Enable" start="204" end="204" type="bool"/>
<field name="Slice ID" start="196" end="199" type="uint"/>
<field name="Stream ID" start="192" end="193" type="uint"/>
<field name="Indirect PAK-BSE Data Start Address" start="224" end="252" type="offset"/>
<field name="QP Max Negative Modifier Magnitude" start="280" end="287" type="uint"/>
<field name="QP Max Positive Modifier Magnitude" start="272" end="279" type="uint"/>
<field name="Shrink Resistance" start="268" end="271" type="uint"/>
<field name="Shrink Init" start="264" end="267" type="uint"/>
<field name="Grow Resistance" start="260" end="263" type="uint"/>
<field name="Grow Init" start="256" end="259" type="uint"/>
<field name="Correct 6" start="308" end="311" type="uint"/>
<field name="Correct 5" start="304" end="307" type="uint"/>
<field name="Correct 4" start="300" end="303" type="uint"/>
<field name="Correct 3" start="296" end="299" type="uint"/>
<field name="Correct 2" start="292" end="295" type="uint"/>
<field name="Correct 1" start="288" end="291" type="uint"/>
<field name="CV7" start="348" end="351" type="uint"/>
<field name="CV6" start="344" end="347" type="uint"/>
<field name="CV5" start="340" end="343" type="uint"/>
<field name="CV4" start="336" end="339" type="uint"/>
<field name="CV3" start="332" end="335" type="uint"/>
<field name="CV2" start="328" end="331" type="uint"/>
<field name="CV1" start="324" end="327" type="uint"/>
<field name="CV0" start="320" end="323" type="uint"/>
</instruction>
<instruction name="MFX_AVC_WEIGHTOFFSET_STATE" bias="2" length="50" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="5"/>
<field name="DWord Length" start="0" end="11" type="uint" default="48"/>
<field name="Weight and Offset Select" start="32" end="32" type="uint">
<value name="L0 table" value="0"/>
<value name="L1 table" value="1"/>
</field>
<group count="96" start="64" size="32">
<field name="Weight Offset" start="0" end="31" type="uint"/>
</group>
</instruction>
<instruction name="MFX_BSP_BUF_BASE_ADDR_STATE" bias="2" length="4" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="4"/>
<field name="DWord Length" start="0" end="11" type="uint" default="2"/>
<field name="BSD/MPC Row Store Scratch Buffer - Address" start="38" end="63" type="address"/>
<field name="BSD/MPC Row Store Scratch Buffer - Arbitration Priority Control" start="36" end="37" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="BSP Row Store Scratch Buffer - Graphics Data Type" start="34" end="34" type="uint"/>
<field name="BSP Row Store Scratch Buffer - Cacheability Control" start="32" end="33" type="uint">
<value name="GTT entry" value="0"/>
<value name="Not in LLC or MLC" value="1"/>
<value name="In LLC but not MLC" value="2"/>
<value name="Both LLC and MLC" value="3"/>
</field>
<field name="MPR Row Store Scratch Buffer - Address" start="70" end="95" type="address"/>
<field name="MPR Row Store Scratch Buffer - Arbitration Priority Control" start="68" end="69" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="MPR Row Store Scratch Buffer - Graphics Data Type" start="66" end="66" type="uint"/>
<field name="MPR Row Store Scratch Buffer - Cacheability Control" start="64" end="65" type="uint">
<value name="GTT entry" value="0"/>
<value name="Not in LLC or MLC" value="1"/>
<value name="In LLC but not MLC" value="2"/>
<value name="Both LLC and MLC" value="3"/>
</field>
<field name="Bitplane Read Buffer - Address" start="102" end="127" type="address"/>
<field name="Bitplane Read Buffer - Arbitration Priority Control" start="100" end="101" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Bitplane Read Buffer - Graphics Data Type" start="98" end="98" type="uint"/>
<field name="Bitplane Read Buffer - Cacheability Control" start="96" end="97" type="uint">
<value name="GTT entry" value="0"/>
<value name="Not in LLC or MLC" value="1"/>
<value name="In LLC but not MLC" value="2"/>
<value name="Both LLC and MLC" value="3"/>
</field>
</instruction>
<instruction name="MFX_IND_OBJ_BASE_ADDR_STATE" bias="2" length="11" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="3"/>
<field name="DWord Length" start="0" end="11" type="uint" default="9"/>
<field name="MFX Indirect Bitstream Object - Address" start="44" end="63" type="address"/>
<field name="MFX Indirect Bitstream Object - Arbitration Priority Control" start="36" end="37" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="MFX Indirect Bitstream Object - Graphics Data Type" start="34" end="34" type="uint"/>
<field name="MFX Indirect Bitstream Object - Cacheability Control" start="32" end="33" type="uint">
<value name="GTT entry" value="0"/>
<value name="Not in LLC or MLC" value="1"/>
<value name="In LLC but not MLC" value="2"/>
<value name="Both LLC and MLC" value="3"/>
</field>
<field name="MFX Indirect Bitstream Object - Access Upper Bound" start="76" end="95" type="address"/>
<field name="MFX Indirect MV Object - Address" start="108" end="127" type="address"/>
<field name="MFX Indirect MV Object - Arbitration Priority Control" start="100" end="101" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="MFX Indirect MV Object - Graphics Data Type" start="98" end="98" type="uint"/>
<field name="MFX Indirect MV Object - Cacheability Control" start="96" end="97" type="uint">
<value name="GTT entry" value="0"/>
<value name="Not in LLC or MLC" value="1"/>
<value name="In LLC but not MLC" value="2"/>
<value name="Both LLC and MLC" value="3"/>
</field>
<field name="MFX Indirect MV Object - Access Upper Bound" start="140" end="159" type="address"/>
<field name="MFD Indirect IT-COEFF Object - Address" start="172" end="191" type="address"/>
<field name="MFD Indirect IT-COEFF Object - Arbitration Priority Control" start="164" end="165" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="MFD Indirect IT-COEFF Object - Graphics Data Type" start="162" end="162" type="uint"/>
<field name="MFD Indirect IT-COEFF Object - Cacheability Control" start="160" end="161" type="uint">
<value name="GTT entry" value="0"/>
<value name="Not in LLC or MLC" value="1"/>
<value name="In LLC but not MLC" value="2"/>
<value name="Both LLC and MLC" value="3"/>
</field>
<field name="MFD Indirect IT-COEFF Object - Access Upper Bound" start="204" end="223" type="address"/>
<field name="MFD Indirect IT-DBLK Object - Address" start="236" end="255" type="address"/>
<field name="MFD Indirect IT-DBLK Object - Arbitration Priority Control" start="228" end="229" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="MFD Indirect IT-DBLK Object - Graphics Data Type" start="226" end="226" type="uint"/>
<field name="MFD Indirect IT-DBLK Object - Cacheability Control" start="224" end="225" type="uint">
<value name="GTT entry" value="0"/>
<value name="Not in LLC or MLC" value="1"/>
<value name="In LLC but not MLC" value="2"/>
<value name="Both LLC and MLC" value="3"/>
</field>
<field name="MFD Indirect IT-DBLK Object - Access Upper Bound" start="268" end="287" type="address"/>
<field name="MFC Indirect PAK-BSE Object - Address" start="300" end="319" type="address"/>
<field name="MFC Indirect PAK-BSE Object - Arbitration Priority Control" start="292" end="293" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="MFC Indirect PAK-BSE Object - Graphics Data Type" start="290" end="290" type="uint"/>
<field name="MFC Indirect PAK-BSE Object - Cacheability Control" start="288" end="289" type="uint">
<value name="GTT entry" value="0"/>
<value name="Not in LLC or MLC" value="1"/>
<value name="In LLC but not MLC" value="2"/>
<value name="Both LLC and MLC" value="3"/>
</field>
<field name="MFC Indirect PAK-BSE Object - Access Upper Bound" start="332" end="351" type="address"/>
</instruction>
<instruction name="MFX_MPEG2_PIC_STATE" bias="2" length="3" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="3"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="0"/>
<field name="DWord Length" start="0" end="11" type="uint" default="1"/>
<field name="F_code[1][1]" start="60" end="63" type="uint"/>
<field name="F_code[1][0]" start="56" end="59" type="uint"/>
<field name="F_code[0][1]" start="52" end="55" type="uint"/>
<field name="F_code[0][0]" start="48" end="51" type="uint"/>
<field name="Intra DC Precision" start="46" end="47" type="uint"/>
<field name="Picture Structure" start="44" end="45" type="uint">
<value name="MPEG_TOP_FIELD" value="1"/>
<value name="MPEG_BOTTOM_FIELD" value="2"/>
<value name="MPEG_FRAME" value="3"/>
</field>
<field name="Top Field First" start="43" end="43" type="bool"/>
<field name="Frame Prediction Frame DCT" start="42" end="42" type="uint"/>
<field name="Concealment MV" start="41" end="41" type="bool"/>
<field name="Quantizer Scale Type" start="40" end="40" type="uint">
<value name="MPEG_QSCALE_LINEAR" value="0"/>
<value name="MPEG_QSCALE_NONLINEAR" value="1"/>
</field>
<field name="Intra VLC Format" start="39" end="39" type="uint"/>
<field name="Scan Order" start="38" end="38" type="uint">
<value name="MPEG_ZIGZAG_SCAN" value="0"/>
<value name="MPEG_ALTERNATE_VERTICAL_SCAN" value="1"/>
</field>
<field name="Picture Coding Type" start="64" end="74" type="uint">
<value name="MPEG_I_PICTURE" value="1"/>
<value name="MPEG_P_PICTURE" value="2"/>
<value name="MPEG_B_PICTURE" value="3"/>
</field>
<field name="Frame Height In MBs" start="112" end="119" type="uint"/>
<field name="Frame Width In MBs" start="96" end="103" type="uint"/>
</instruction>
<instruction name="MFX_MPEG2_QM_STATE" bias="2" length="18" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="3"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="1"/>
<field name="DWord Length" start="0" end="11" type="uint" default="16"/>
<field name="QM Type" start="32" end="32" type="uint">
<value name="MPEG_INTRA_QUANTIZER_MATRIX" value="0"/>
<value name="MPEG_NON_INTRA_QUANTIZER_MATRIX" value="1"/>
</field>
<group count="16" start="64" size="32">
<field name="Quantizer Matrix" start="0" end="31" type="uint"/>
</group>
</instruction>
<instruction name="MFX_PIPE_BUF_ADDR_STATE" bias="2" length="24" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="2"/>
<field name="DWord Length" start="0" end="11" type="uint" default="22"/>
<field name="Pre Deblocking - Address" start="38" end="63" type="address"/>
<field name="Pre Deblocking - Arbitration Priority Control" start="36" end="37" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Pre Deblocking - Graphics Data Type" start="34" end="34" type="uint"/>
<field name="Pre Deblocking - Cacheability Control" start="32" end="33" type="uint">
<value name="GTT entry" value="0"/>
<value name="Not in LLC or MLC" value="1"/>
<value name="In LLC but not MLC" value="2"/>
<value name="Both LLC and MLC" value="3"/>
</field>
<field name="Post Deblocking - Address" start="70" end="95" type="address"/>
<field name="Post Deblocking - Arbitration Priority Control" start="68" end="69" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Post Deblocking - Graphics Data Type" start="66" end="66" type="uint"/>
<field name="Post Deblocking - Cacheability Control" start="64" end="65" type="uint">
<value name="GTT entry" value="0"/>
<value name="Not in LLC or MLC" value="1"/>
<value name="In LLC but not MLC" value="2"/>
<value name="Both LLC and MLC" value="3"/>
</field>
<field name="Original Uncompressed Picture Source - Address" start="102" end="127" type="address"/>
<field name="Original Uncompressed Picture Source - Arbitration Priority Control" start="100" end="101" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Original Uncompressed Picture Source - Graphics Data Type" start="98" end="98" type="uint"/>
<field name="Original Uncompressed Picture Source - Cacheability Control" start="96" end="97" type="uint">
<value name="GTT entry" value="0"/>
<value name="Not in LLC or MLC" value="1"/>
<value name="In LLC but not MLC" value="2"/>
<value name="Both LLC and MLC" value="3"/>
</field>
<field name="Stream-Out Data Destination - Address" start="134" end="159" type="offset"/>
<field name="Stream-Out Data Destination - Arbitration Priority Control" start="132" end="133" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Stream-Out Data Destination - Graphics Data Type" start="130" end="130" type="uint"/>
<field name="Stream-Out Data Destination - Cacheability Control" start="128" end="129" type="uint">
<value name="GTT entry" value="0"/>
<value name="Not in LLC or MLC" value="1"/>
<value name="In LLC but not MLC" value="2"/>
<value name="Both LLC and MLC" value="3"/>
</field>
<field name="Intra Row Store Scratch Buffer - Address" start="166" end="191" type="address"/>
<field name="Intra Row Store Scratch Buffer - Arbitration Priority Control" start="164" end="165" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Intra Row Store Scratch Buffer - Graphics Data Type" start="162" end="162" type="uint"/>
<field name="Intra Row Store Scratch Buffer - Cacheability Control" start="160" end="161" type="uint">
<value name="GTT entry" value="0"/>
<value name="Not in LLC or MLC" value="1"/>
<value name="In LLC but not MLC" value="2"/>
<value name="Both LLC and MLC" value="3"/>
</field>
<field name="Deblocking Filter Row Store Scratch Buffer - Address" start="198" end="223" type="address"/>
<field name="Deblocking Filter Row Store Scratch Buffer - Arbitration Priority Control" start="196" end="197" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Deblocking Filter Row Store Scratch Buffer - Graphics Data Type" start="194" end="194" type="uint"/>
<field name="Deblocking Filter Row Store Scratch Buffer - Cacheability Control" start="192" end="193" type="uint">
<value name="GTT entry" value="0"/>
<value name="Not in LLC or MLC" value="1"/>
<value name="In LLC but not MLC" value="2"/>
<value name="Both LLC and MLC" value="3"/>
</field>
<group count="16" start="224" size="32">
<field name="Reference Picture - Address" start="6" end="31" type="address"/>
<field name="Reference Picture - Arbitration Priority Control" start="4" end="5" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Reference Picture - Graphics Data Type" start="2" end="2" type="uint"/>
<field name="Reference Picture - Cacheability Control" start="0" end="1" type="uint">
<value name="GTT entry" value="0"/>
<value name="Not in LLC or MLC" value="1"/>
<value name="In LLC but not MLC" value="2"/>
<value name="Both LLC and MLC" value="3"/>
</field>
</group>
<field name="MB Status Buffer - Address" start="742" end="767" type="address"/>
<field name="MB Status Buffer - Arbitration Priority Control" start="740" end="741" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="MB Status Buffer - Graphics Data Type" start="738" end="738" type="uint"/>
<field name="MB Status Buffer - Cacheability Control" start="736" end="737" type="uint">
<value name="GTT entry" value="0"/>
<value name="Not in LLC or MLC" value="1"/>
<value name="In LLC but not MLC" value="2"/>
<value name="Both LLC and MLC" value="3"/>
</field>
</instruction>
<instruction name="MFX_PIPE_MODE_SELECT" bias="2" length="4" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="0"/>
<field name="DWord Length" start="0" end="11" type="uint" default="2"/>
<field name="Decoder Mode select" start="48" end="48" type="uint">
<value name="LD Mode" value="0"/>
<value name="IT Mode" value="1"/>
</field>
<field name="Stream-Out Enable" start="42" end="42" type="bool"/>
<field name="Post Deblocking Output Enable" start="41" end="41" type="bool"/>
<field name="Pre Deblocking Output Enable" start="40" end="40" type="bool"/>
<field name="ZLR TLB Prefetch Enable" start="39" end="39" type="bool"/>
<field name="Stitch Mode" start="37" end="37" type="bool"/>
<field name="Codec Select" start="36" end="36" type="uint">
<value name="Decode" value="0"/>
<value name="Encode" value="1"/>
</field>
<field name="Standard Select" start="32" end="33" type="uint" prefix="SS">
<value name="VC1" value="1"/>
<value name="AVC" value="2"/>
</field>
<field name="Slice PB Rounding" start="84" end="84" type="uint"/>
<field name="Intra 8x8 Rounding" start="83" end="83" type="uint"/>
<field name="Clock Gate Enable at Slice-level" start="70" end="70" type="bool"/>
<field name="AVC MV/POC Table Error Disable" start="68" end="68" type="uint">
<value name="Terminates" value="0"/>
<value name="Will not terminate" value="1"/>
</field>
<field name="AVC Mbdata Error Disable" start="67" end="67" type="uint"/>
<field name="AVC CABAC/CAVLC Decode Error Disable" start="66" end="66" type="uint">
<value name="Terminate" value="0"/>
<value name="Will not terminate" value="1"/>
</field>
<field name="AVC Long Field MV" start="65" end="65" type="uint">
<value name="13 bits precision" value="0"/>
<value name="12 bits precision" value="1"/>
</field>
<field name="AVC ILDB Boundary Strength Calculation" start="64" end="64" type="uint">
<value name="Calculated only when post-filter is ON" value="0"/>
<value name="Calculated all the time" value="1"/>
</field>
</instruction>
<instruction name="MFX_STATE_POINTER" bias="2" length="2" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="6"/>
<field name="DWord Length" start="0" end="11" type="uint" default="0"/>
<field name="State Pointer" start="37" end="63" type="uint"/>
<field name="State Pointer Index" start="32" end="33" type="uint">
<value name="Indirect state pointer 0" value="0"/>
<value name="Indirect state pointer 1" value="1"/>
<value name="Indirect state pointer 2" value="2"/>
<value name="Indirect state pointer 3" value="3"/>
</field>
</instruction>
<instruction name="MFX_SURFACE_STATE" bias="2" length="6" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="0"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="2"/>
<field name="DWord Length" start="0" end="11" type="uint" default="4"/>
<field name="Height" start="83" end="95" type="uint"/>
<field name="Width" start="70" end="82" type="uint"/>
<field name="Cr(V)/Cb(U) Pixel Offset V Direction" start="64" end="65" type="uint"/>
<field name="Surface Format" start="124" end="127" type="uint">
<value name="YCRCB_NORMAL" value="0"/>
<value name="YCRCB_SWAPUVY" value="1"/>
<value name="YCRCB_SWAPUV" value="2"/>
<value name="YCRCB_SWAPY" value="3"/>
<value name="PLANAR_420_8" value="4"/>
<value name="PLANAR_411_8" value="5"/>
<value name="PLANAR_422_8" value="6"/>
<value name="STMM_DN_STATISTICS" value="7"/>
<value name="R10G10B10A2_UNORM" value="8"/>
<value name="R8G8B8A8_UNORM" value="9"/>
<value name="R8B8_UNORM (CrCb)" value="10"/>
<value name="R8_UNORM (Cr/Cb)" value="11"/>
<value name="Y8_UNORM" value="12"/>
</field>
<field name="Interleave Chroma" start="123" end="123" type="bool"/>
<field name="Surface Pitch" start="99" end="115" type="uint"/>
<field name="Half Pitch for Chroma" start="98" end="98" type="bool"/>
<field name="Tiled Surface" start="97" end="97" type="bool"/>
<field name="Tile Walk" start="96" end="96" type="uint" prefix="TW">
<value name="XMAJOR" value="0"/>
<value name="YMAJOR" value="1"/>
</field>
<field name="X Offset for U(Cb)" start="144" end="156" type="uint"/>
<field name="Y Offset for U(Cb)" start="128" end="140" type="uint"/>
<field name="X Offset for V(Cr)" start="176" end="188" type="uint"/>
<field name="Y Offset for V(Cr)" start="160" end="172" type="uint"/>
</instruction>
<instruction name="MFX_VC1_DIRECTMODE_STATE" bias="2" length="3" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="2"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="2"/>
<field name="DWord Length" start="0" end="11" type="uint" default="1"/>
<field name="Direct MV Write Buffer - Address" start="38" end="63" type="address"/>
<field name="Direct MV Write Buffer - Arbitration Priority Control" start="36" end="37" type="uint">
<value name="Highest Priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest Priority" value="3"/>
</field>
<field name="Direct MV Write Buffer - Graphics Data Type" start="34" end="34" type="uint"/>
<field name="Direct MV Write Buffer - Cacheability Control" start="32" end="33" type="uint">
<value name="GTT entry" value="0"/>
<value name="Not in in LLC or MLC" value="1"/>
<value name="In LLC but not MLC" value="2"/>
<value name="Both LLC and MLC" value="3"/>
</field>
<field name="Direct MV Read Buffer - Address" start="70" end="95" type="address"/>
<field name="Direct MV Read Buffer - Arbitration Priority Control" start="68" end="69" type="uint">
<value name="Highest priority" value="0"/>
<value name="Second highest priority" value="1"/>
<value name="Third highest priority" value="2"/>
<value name="Lowest priority" value="3"/>
</field>
<field name="Direct MV Read Buffer - Graphics Data Type" start="66" end="66" type="uint"/>
<field name="Direct MV Read Buffer - Cacheability Control" start="64" end="65" type="uint">
<value name="GTT entry" value="0"/>
<value name="Not in LLC or MLC" value="1"/>
<value name="In LLC but not MLC" value="2"/>
<value name="Both LLC and MLC" value="3"/>
</field>
</instruction>
<instruction name="MFX_VC1_PIC_STATE" bias="2" length="6" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="2"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="0"/>
<field name="DWord Length" start="0" end="11" type="uint" default="4"/>
<field name="Picture Height in MBs" start="48" end="55" type="uint"/>
<field name="Picture Width in MBs" start="32" end="39" type="uint"/>
<field name="Sync Marker" start="95" end="95" type="bool"/>
<field name="Concealment Enable" start="93" end="93" type="bool"/>
<field name="Alternative PQ Value" start="88" end="92" type="uint"/>
<field name="Loop Filter Enable" start="87" end="87" type="bool"/>
<field name="Overlap Smoothing Enable" start="86" end="86" type="bool"/>
<field name="Implicit Quantizer" start="85" end="85" type="bool"/>
<field name="PQ Value" start="80" end="84" type="uint"/>
<field name="Alternative PQ Edge Mask" start="76" end="79" type="uint"/>
<field name="Alternative PQ Configuration" start="74" end="75" type="uint"/>
<field name="Half QP" start="73" end="73" type="uint"/>
<field name="PQ Uniform" start="72" end="72" type="bool"/>
<field name="CONDOVER" start="70" end="71" type="uint"/>
<field name="Second Field" start="69" end="69" type="bool"/>
<field name="Picture Type" start="66" end="68" type="uint"/>
<field name="Frame Coding Mode" start="64" end="65" type="uint">
<value name="Progressive Frame Picture" value="0"/>
<value name="Interlaced Frame Picture" value="1"/>
<value name="Field Picture with Top Field First" value="2"/>
<value name="Field Picture with Bottom Field First" value="3"/>
</field>
<field name="Bitplane Buffer Present" start="119" end="119" type="bool"/>
<field name="FORWARDMB Raw" start="118" end="118" type="bool"/>
<field name="MVTYPEMB Raw" start="117" end="117" type="bool"/>
<field name="SKIPMB Raw" start="116" end="116" type="bool"/>
<field name="DIRECTMB Raw" start="115" end="115" type="bool"/>
<field name="OVERFLAGS Raw" start="114" end="114" type="bool"/>
<field name="ACPRED Raw" start="113" end="113" type="bool"/>
<field name="FIELDTX Raw" start="112" end="112" type="bool"/>
<field name="Extended DMV Range" start="110" end="111" type="uint"/>
<field name="Extended MV Range" start="108" end="109" type="uint"/>
<field name="Four MV Switch" start="107" end="107" type="uint">
<value name="Only 1-MV" value="0"/>
<value name="1, 2, or 4 MVs" value="1"/>
</field>
<field name="Fast UV Motion Compensation" start="106" end="106" type="uint">
<value name="No Rounding" value="0"/>
<value name="Quarter-Pel offsets to Half/Full pel positions" value="1"/>
</field>
<field name="Unified MV Mode" start="104" end="105" type="uint">
<value name="1-MV half-pel bilinear" value="3"/>
<value name="1-MV" value="1"/>
<value name="1-MV half-pel" value="2"/>
<value name="Mixed MV" value="0"/>
</field>
<field name="Reference Field Picture Polarity" start="102" end="102" type="uint">
<value name="Top (even) Field" value="0"/>
<value name="Bottom (odd) Field" value="1"/>
</field>
<field name="Number of References" start="101" end="101" type="uint">
<value name="One field referenced" value="0"/>
<value name="Two fields referenced" value="1"/>
</field>
<field name="FRFD Reference Distance" start="96" end="100" type="uint"/>
<field name="Scale Factor" start="152" end="159" type="uint"/>
<field name="MV Table" start="148" end="150" type="uint"/>
<field name="4-MV Block Pattern Table" start="146" end="147" type="uint"/>
<field name="2-MV Block Pattern Table" start="144" end="145" type="uint"/>
<field name="Picture-level Transform Type" start="140" end="141" type="uint">
<value name="8x8 Transform" value="0"/>
<value name="8x4 Transform" value="1"/>
<value name="4x8 Transform" value="2"/>
<value name="4x4 Transform" value="3"/>
</field>
<field name="MB Transform Type" start="139" end="139" type="uint"/>
<field name="MB Mode Table" start="136" end="138" type="uint"/>
<field name="Picture-level Transform Luma AC Coding Set Index" start="134" end="135" type="uint"/>
<field name="Picture-level Transform Chroma AC Coding Set Index" start="132" end="133" type="uint"/>
<field name="Intra Transform DC Table" start="131" end="131" type="uint"/>
<field name="Coded Block Pattern Table" start="128" end="130" type="uint"/>
<field name="DMV Surface Valid" start="173" end="173" type="bool"/>
<field name="BRFD Reference Distance" start="168" end="172" type="uint"/>
<field name="Bitplane Buffer Pitch" start="160" end="167" type="uint"/>
</instruction>
<instruction name="MFX_VC1_PRED_PIPE_STATE" bias="2" length="4" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Pipeline" start="27" end="28" type="uint" default="2"/>
<field name="Media Command Opcode" start="24" end="26" type="uint" default="2"/>
<field name="SubOpcode A" start="21" end="23" type="uint" default="0"/>
<field name="SubOpcode B" start="16" end="20" type="uint" default="1"/>
<field name="DWord Length" start="0" end="11" type="uint" default="2"/>
<field name="Reference Frame Boundary Replication Mode" start="40" end="43" type="uint">
<value name="Progressive Frame Replication" value="0"/>
<value name="Interlace Frame Replication" value="1"/>
</field>
<field name="Interpolation Rounder Control" start="36" end="36" type="uint"/>
<field name="VC1 Profile" start="34" end="35" type="uint">
<value name="Simple Profile" value="0"/>
<value name="Main Profile" value="1"/>
<value name="Advanced Profile" value="2"/>
</field>
<field name="LumShift2 - single - FWD" start="88" end="93" type="uint"/>
<field name="LumShift1 - single - FWD" start="80" end="85" type="uint"/>
<field name="LumScale2 - single - FWD" start="72" end="77" type="uint"/>
<field name="LumScale1 - single - FWD" start="64" end="69" type="uint"/>
<field name="LumShift2 - double - FWD" start="120" end="125" type="uint"/>
<field name="LumShift1 - double - FWD" start="112" end="117" type="uint"/>
<field name="LumScale2 - double - FWD" start="104" end="109" type="uint"/>
<field name="LumScale1 - double - FWD" start="96" end="101" type="uint"/>
<field name="LumShift2 - single - BWD" start="152" end="157" type="uint"/>
<field name="LumShift1 - single - BWD" start="144" end="149" type="uint"/>
<field name="LumScale2 - single - BWD" start="136" end="141" type="uint"/>
<field name="LumScale1 - single - BWD" start="128" end="133" type="uint"/>
<field name="LumShift2 - double - BWD" start="184" end="189" type="uint"/>
<field name="LumShift1 - double - BWD" start="176" end="181" type="uint"/>
<field name="LumScale2 - double - BWD" start="168" end="173" type="uint"/>
<field name="LumScale1 - double - BWD" start="160" end="165" type="uint"/>
<field name="MV Mode" start="211" end="212" type="uint">
<value name="Half-pel bicubic" value="0"/>
<value name="Quarter-pel bicubic" value="1"/>
</field>
<field name="Fast UV Compensation" start="210" end="210" type="bool"/>
<field name="Range Reduction Scale" start="209" end="209" type="uint"/>
<field name="Range Reduction" start="208" end="208" type="bool"/>
<field name="Vin Intensity Compensation Double Forward Enable" start="198" end="199" type="uint"/>
<field name="Vin Intensity Compensation Double Backward Enable" start="196" end="197" type="uint"/>
<field name="Vin Intensity Compensation Single Forward Enable" start="194" end="195" type="uint"/>
<field name="Vin Intensity Compensation Single Backward Enable" start="192" end="193" type="uint"/>
</instruction>
<instruction name="MFX_WAIT" bias="1" length="1" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command Subtype" start="27" end="28" type="uint" default="1"/>
<field name="SubOpcode" start="16" end="26" type="uint" default="0"/>
<field name="MFX Sync Control Flag" start="8" end="8" type="bool"/>
<field name="DWord Length" start="0" end="5" type="uint" default="0"/>
</instruction>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<instruction name="MI_ARB_CHECK" bias="1" length="1">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="5"/>
</instruction>
<instruction name="MI_ARB_ON_OFF" bias="1" length="1">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="8"/>
<field name="Arbitration Enable" start="0" end="0" type="bool"/>
</instruction>
<instruction name="MI_BATCH_BUFFER_END" bias="1" length="1">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="10"/>
</instruction>
<instruction name="MI_BATCH_BUFFER_START" bias="2" length="2">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="49"/>
<field name="Clear Command Buffer Enable" start="11" end="11" type="bool"/>
<field name="Address Space Indicator" start="8" end="8" type="uint" prefix="ASI">
<value name="GGTT" value="0"/>
<value name="PPGTT" value="1"/>
</field>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Batch Buffer Start Address" start="34" end="63" type="address"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="MI_CLFLUSH" bias="2" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="39"/>
intel/genxml; Make "Use Global GTT a boolean We also remove the redundant zero defaults since everything without an explicit default gets zeroed automatically. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:55:21 -07:00
<field name="Use Global GTT" start="22" end="22" type="bool"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="DWord Length" start="0" end="5" type="uint" default="0"/>
<field name="Page Base Address" start="44" end="63" type="address"/>
<field name="Starting Cacheline Offset" start="38" end="43" type="uint"/>
<group count="0" start="64" size="32">
<field name="DW Representing a Half Cache Line" start="0" end="31" type="uint"/>
</group>
</instruction>
<instruction name="MI_CONDITIONAL_BATCH_BUFFER_END" bias="2" length="2">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="54"/>
intel/genxml; Make "Use Global GTT a boolean We also remove the redundant zero defaults since everything without an explicit default gets zeroed automatically. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:55:21 -07:00
<field name="Use Global GTT" start="22" end="22" type="bool"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Compare Semaphore" start="21" end="21" type="uint" default="0"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Compare Data Dword" start="32" end="63" type="uint"/>
<field name="Compare Address" start="67" end="95" type="address"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="MI_FLUSH" bias="1" length="1" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="4"/>
<field name="Indirect State Pointers Disable" start="5" end="5" type="bool"/>
<field name="Generic Media State Clear" start="4" end="4" type="bool"/>
<field name="Global Snapshot Count Reset" start="3" end="3" type="uint">
<value name="Don't Reset" value="0"/>
<value name="Reset" value="1"/>
</field>
<field name="Render Cache Flush Inhibit" start="2" end="2" type="uint">
<value name="Flush" value="0"/>
<value name="Don't Flush" value="1"/>
</field>
<field name="State/Instruction Cache Invalidate" start="1" end="1" type="uint">
<value name="Don't Invalidate" value="0"/>
<value name="Invalidate" value="1"/>
</field>
</instruction>
intel/genxml: Media instructions and structures for gen6 v2: Fixed MI_WAIT_FOR_EVENT to be for blitter and video also Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-01-16 13:52:11 +02:00
<instruction name="MI_FLUSH_DW" bias="2" length="4" engine="video">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="38"/>
<field name="Store Data Index" start="21" end="21" type="bool"/>
<field name="TLB Invalidate" start="18" end="18" type="bool"/>
<field name="Synchronize GFDT Surface" start="17" end="17" type="bool"/>
<field name="Post-Sync Operation" start="14" end="15" type="uint"/>
<field name="Notify Enable" start="8" end="8" type="bool"/>
<field name="Video Pipeline Cache Invalidate" start="7" end="7" type="bool"/>
<field name="DWord Length" start="0" end="5" type="uint"/>
<field name="Address" start="35" end="63" type="address"/>
<field name="Destination Address Type" start="34" end="34" type="uint" prefix="DAT">
<value name="PPGTT" value="0"/>
<value name="GGTT" value="1"/>
</field>
<group count="2" start="64" size="32">
<field name="Immediate Data" start="0" end="31" type="uint"/>
</group>
</instruction>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<instruction name="MI_LOAD_REGISTER_IMM" bias="2" length="3">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="34"/>
<field name="Byte Write Disables" start="8" end="11" type="uint"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Register Offset" start="34" end="54" type="offset"/>
<field name="Data DWord" start="64" end="95" type="uint"/>
intel: genxml: decode variable length MI_LRI MI_LOAD_REGISTER_IMM can load multiple (register, value) tuples in one command. In our drivers we only use one tuple at a time, but the kernel might load more than one at a time. Instead of making all the tuple part of a group, we leave out the first tuple (the one we use in the generated packing structures). This is particularly useful for looking at error stats generated by the kernel. Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Scott D Phillips <scott.d.phillips@intel.com>
2018-04-03 11:21:31 +01:00
<group count="0" start="96" size="64">
<field name="Register Offset" start="2" end="22" type="offset"/>
<field name="Data DWord" start="32" end="63" type="uint"/>
</group>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="MI_LOAD_SCAN_LINES_EXCL" bias="2" length="2" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="19"/>
<field name="Display (Plane) Select" start="19" end="21" type="uint">
<value name="Display Plane A" value="0"/>
<value name="Display Plane B" value="1"/>
<value name="Display Plane C" value="4"/>
</field>
<field name="DWord Length" start="0" end="5" type="uint" default="0"/>
<field name="Start Scan Line Number" start="48" end="60" type="uint"/>
<field name="End Scan Line Number" start="32" end="44" type="uint"/>
</instruction>
<instruction name="MI_NOOP" bias="1" length="1">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="0"/>
<field name="Identification Number Register Write Enable" start="22" end="22" type="bool"/>
<field name="Identification Number" start="0" end="21" type="uint"/>
</instruction>
<instruction name="MI_REPORT_HEAD" bias="1" length="1">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="7"/>
</instruction>
<instruction name="MI_SEMAPHORE_MBOX" bias="2" length="3">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="22"/>
<field name="Register Select" start="16" end="17" type="uint">
<value name="RVSYNC" value="0"/>
<value name="RBSYNC" value="2"/>
<value name="Use General Register Select" value="3"/>
</field>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Semaphore Data Dword" start="32" end="63" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="MI_SET_CONTEXT" bias="2" length="2" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="24"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Logical Context Address" start="44" end="63" type="address"/>
<field name="HD DVD Context" start="41" end="41" type="bool"/>
<field name="Reserved, Must be 1" start="40" end="40" type="uint"/>
<field name="Extended State Save Enable" start="35" end="35" type="bool"/>
<field name="Extended State Restore Enable" start="34" end="34" type="bool"/>
<field name="Force Restore" start="33" end="33" type="uint"/>
<field name="Restore Inhibit" start="32" end="32" type="uint"/>
</instruction>
<instruction name="MI_STORE_DATA_IMM" bias="2" length="4">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="32"/>
intel/genxml; Make "Use Global GTT a boolean We also remove the redundant zero defaults since everything without an explicit default gets zeroed automatically. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:55:21 -07:00
<field name="Use Global GTT" start="22" end="22" type="bool"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="DWord Length" start="0" end="5" type="uint" default="2"/>
genxml: Make MI_STORE_DATA_IMM more consistent Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Cc: "13.0 17.0" <mesa-stable@lists.freedesktop.org>
2017-02-18 15:18:31 -08:00
<field name="Address" start="66" end="95" type="address"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Core Mode Enable" start="64" end="64" type="uint"/>
genxml: Make MI_STORE_DATA_IMM have a single 64-bit data field This is way more convenient than having two separate dword fields. Reviewed-By: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2017-03-14 16:22:00 -07:00
<field name="Immediate Data" start="96" end="159" type="uint"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
</instruction>
<instruction name="MI_STORE_DATA_INDEX" bias="2" length="3">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="33"/>
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Offset" start="34" end="43" type="uint"/>
<field name="Data DWord 0" start="64" end="95" type="uint"/>
<field name="Data DWord 1" start="96" end="127" type="uint"/>
</instruction>
<instruction name="MI_STORE_REGISTER_MEM" bias="2" length="3">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="36"/>
intel/genxml; Make "Use Global GTT a boolean We also remove the redundant zero defaults since everything without an explicit default gets zeroed automatically. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 22:55:21 -07:00
<field name="Use Global GTT" start="22" end="22" type="bool"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="DWord Length" start="0" end="7" type="uint" default="1"/>
<field name="Register Address" start="34" end="54" type="offset"/>
<field name="Memory Address" start="66" end="95" type="address"/>
</instruction>
<instruction name="MI_SUSPEND_FLUSH" bias="1" length="1">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="11"/>
<field name="Suspend Flush" start="0" end="0" type="bool"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="MI_URB_CLEAR" bias="2" length="2" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="25"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="URB Clear Length" start="48" end="60" type="uint"/>
<field name="URB Address" start="32" end="45" type="offset"/>
</instruction>
<instruction name="MI_USER_INTERRUPT" bias="1" length="1">
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="2"/>
</instruction>
intel/genxml: Media instructions and structures for gen6 v2: Fixed MI_WAIT_FOR_EVENT to be for blitter and video also Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2019-01-16 13:52:11 +02:00
<instruction name="MI_WAIT_FOR_EVENT" bias="1" length="1" engine="render|blitter|video">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="0"/>
<field name="MI Command Opcode" start="23" end="28" type="uint" default="3"/>
<field name="Condition Code Wait Select" start="16" end="19" type="uint">
<value name="Not enabled" value="0"/>
</field>
<field name="Display Pipe B Horizontal Blank Wait Enable" start="13" end="13" type="bool"/>
<field name="Display Pipe B Vertical Blank Wait Enable" start="11" end="11" type="bool"/>
<field name="Display Sprite B Flip Pending Wait Enable" start="10" end="10" type="bool"/>
<field name="Display Plane B Flip Pending Wait Enable" start="9" end="9" type="bool"/>
<field name="Display Pipe B Scan Line Wait Enable" start="8" end="8" type="bool"/>
<field name="Display Pipe A Horizontal Blank Wait Enable" start="5" end="5" type="bool"/>
<field name="Display Pipe A Vertical Blank Wait Enable" start="3" end="3" type="bool"/>
<field name="Display Sprite A Flip Pending Wait Enable" start="2" end="2" type="bool"/>
<field name="Display Plane A Flip Pending Wait Enable" start="1" end="1" type="bool"/>
<field name="Display Pipe A Scan Line Wait Enable" start="0" end="0" type="bool"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="PIPELINE_SELECT" bias="1" length="1" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="1"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="4"/>
<field name="Pipeline Selection" start="0" end="1" type="uint">
<value name="3D" value="0"/>
<value name="Media" value="1"/>
</field>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="PIPE_CONTROL" bias="2" length="5" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="3"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="2"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="0"/>
<field name="DWord Length" start="0" end="7" type="uint" default="3"/>
<field name="Store Data Index" start="53" end="53" type="uint"/>
genxml: Make PIPE_CONTROL::CommandStreamerStallEnable a boolean This has been declared as a uint since SNB but it's only one bit. Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>
2016-05-20 12:07:53 -07:00
<field name="Command Streamer Stall Enable" start="52" end="52" type="bool"/>
intel/genxml: Make some PIPE_CONTROL fields booleans Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-10-14 23:09:38 -07:00
<field name="Global Snapshot Count Reset" start="51" end="51" type="bool"/>
<field name="TLB Invalidate" start="50" end="50" type="bool"/>
<field name="Synchronize GFDT Surface" start="49" end="49" type="bool"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Generic Media State Clear" start="48" end="48" type="bool"/>
<field name="Post Sync Operation" start="46" end="47" type="uint">
<value name="No Write" value="0"/>
<value name="Write Immediate Data" value="1"/>
<value name="Write PS Depth Count" value="2"/>
<value name="Write Timestamp" value="3"/>
</field>
<field name="Depth Stall Enable" start="45" end="45" type="bool"/>
<field name="Render Target Cache Flush Enable" start="44" end="44" type="bool"/>
<field name="Instruction Cache Invalidate Enable" start="43" end="43" type="bool"/>
<field name="Texture Cache Invalidation Enable" start="42" end="42" type="bool"/>
<field name="Indirect State Pointers Disable" start="41" end="41" type="bool"/>
<field name="Notify Enable" start="40" end="40" type="bool"/>
<field name="VF Cache Invalidation Enable" start="36" end="36" type="bool"/>
<field name="Constant Cache Invalidation Enable" start="35" end="35" type="bool"/>
<field name="State Cache Invalidation Enable" start="34" end="34" type="bool"/>
<field name="Stall At Pixel Scoreboard" start="33" end="33" type="bool"/>
<field name="Depth Cache Flush Enable" start="32" end="32" type="bool"/>
<field name="Address" start="67" end="95" type="address"/>
<field name="Destination Address Type" start="66" end="66" type="uint" prefix="DAT">
<value name="GGTT" value="1"/>
</field>
<field name="Immediate Data" start="96" end="159" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="STATE_BASE_ADDRESS" bias="2" length="10" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="0"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="1"/>
<field name="DWord Length" start="0" end="7" type="uint" default="8"/>
<field name="General State Base Address" start="44" end="63" type="address"/>
genxml/gen6: Add uint MOCS fields for most things Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-08-05 14:17:18 -07:00
<field name="General State MOCS" start="40" end="43" type="uint"/>
<field name="Stateless Data Port Access MOCS" start="36" end="39" type="uint"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Stateless Data Port Access Force Write Thru" start="35" end="35" type="uint"/>
<field name="General State Base Address Modify Enable" start="32" end="32" type="bool"/>
<field name="Surface State Base Address" start="76" end="95" type="address"/>
genxml/gen6: Add uint MOCS fields for most things Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-08-05 14:17:18 -07:00
<field name="Surface State MOCS" start="72" end="75" type="uint"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Surface State Base Address Modify Enable" start="64" end="64" type="bool"/>
<field name="Dynamic State Base Address" start="108" end="127" type="address"/>
genxml/gen6: Add uint MOCS fields for most things Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-08-05 14:17:18 -07:00
<field name="Dynamic State MOCS" start="104" end="107" type="uint"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Dynamic State Base Address Modify Enable" start="96" end="96" type="bool"/>
<field name="Indirect Object Base Address" start="140" end="159" type="address"/>
genxml/gen6: Add uint MOCS fields for most things Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-08-05 14:17:18 -07:00
<field name="Indirect Object MOCS" start="136" end="139" type="uint"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Indirect Object Base Address Modify Enable" start="128" end="128" type="bool"/>
<field name="Instruction Base Address" start="172" end="191" type="address"/>
genxml/gen6: Add uint MOCS fields for most things Signed-off-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2016-08-05 14:17:18 -07:00
<field name="Instruction MOCS" start="168" end="171" type="uint"/>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Instruction Base Address Modify Enable" start="160" end="160" type="bool"/>
<field name="General State Access Upper Bound" start="204" end="223" type="address"/>
<field name="General State Access Upper Bound Modify Enable" start="192" end="192" type="bool"/>
<field name="Dynamic State Access Upper Bound" start="236" end="255" type="address"/>
<field name="Dynamic State Access Upper Bound Modify Enable" start="224" end="224" type="bool"/>
<field name="Indirect Object Access Upper Bound" start="268" end="287" type="address"/>
<field name="Indirect Object Access Upper Bound Modify Enable" start="256" end="256" type="bool"/>
<field name="Instruction Access Upper Bound" start="300" end="319" type="address"/>
<field name="Instruction Access Upper Bound Modify Enable" start="288" end="288" type="bool"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="STATE_PREFETCH" bias="2" length="2" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="0"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="0"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="3"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="Prefetch Pointer" start="38" end="63" type="address"/>
<field name="Prefetch Count" start="32" end="34" type="uint"/>
</instruction>
intel/genxml: Add engine definition to render engine instructions (gen6) Instructions meant for the render engine now have a definition specifying that so that can differentiate instructions meant for different engines due to shared opcodes. v2: Divided into individual patches for each gen v3: Added additional engine definitions v4: Added missing engine to MEDIA_GATEWAY_STATE Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-11-08 17:23:06 +02:00
<instruction name="STATE_SIP" bias="2" length="2" engine="render">
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
<field name="Command Type" start="29" end="31" type="uint" default="3"/>
<field name="Command SubType" start="27" end="28" type="uint" default="0"/>
<field name="3D Command Opcode" start="24" end="26" type="uint" default="1"/>
<field name="3D Command Sub Opcode" start="16" end="23" type="uint" default="2"/>
<field name="DWord Length" start="0" end="7" type="uint" default="0"/>
<field name="System Instruction Pointer" start="36" end="63" type="offset"/>
</instruction>
intel: genxml: add INSTDONE registers Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-03-09 11:58:19 +00:00
<register name="BCS_INSTDONE" length="1" num="0x2206c">
<field name="Ring Enable" start="0" end="0" type="bool"/>
<field name="Blitter IDLE" start="1" end="1" type="bool" default="1"/>
<field name="GAB IDLE" start="2" end="2" type="bool" default="1"/>
<field name="BCS Done" start="3" end="3" type="bool" default="1"/>
</register>
<register name="INSTDONE_1" length="1" num="0x206c">
<field name="PRB0 Ring Enable" start="0" end="0" type="bool"/>
<field name="AVS Done" start="1" end="1" type="bool"/>
<field name="HIZ Done" start="2" end="2" type="bool"/>
<field name="GW Done" start="3" end="3" type="bool"/>
<field name="TS Done" start="4" end="4" type="bool"/>
<field name="TD Done" start="6" end="6" type="bool"/>
<field name="VFE Done" start="7" end="7" type="bool"/>
<field name="IEF Done" start="8" end="8" type="bool"/>
<field name="VSC Done" start="9" end="9" type="bool"/>
<field name="ISC2/3 Done" start="10" end="10" type="bool"/>
<field name="ISC1/0 Done" start="11" end="11" type="bool"/>
<field name="IC0 Done" start="12" end="12" type="bool"/>
<field name="IC1 Done" start="13" end="13" type="bool"/>
<field name="IC2 Done" start="14" end="14" type="bool"/>
<field name="IC3 Done" start="15" end="15" type="bool"/>
<field name="EU00 Done" start="16" end="16" type="bool"/>
<field name="EU01 Done" start="17" end="17" type="bool"/>
<field name="EU02 Done" start="18" end="18" type="bool"/>
<field name="MA0 Done" start="19" end="19" type="bool"/>
<field name="EU10 Done" start="20" end="20" type="bool"/>
<field name="EU11 Done" start="21" end="21" type="bool"/>
<field name="EU12 Done" start="22" end="22" type="bool"/>
<field name="MA1 Done" start="23" end="23" type="bool"/>
<field name="EU20 Done" start="24" end="24" type="bool"/>
<field name="EU21 Done" start="25" end="25" type="bool"/>
<field name="EU22 Done" start="26" end="26" type="bool"/>
<field name="MA2 Done" start="27" end="27" type="bool"/>
<field name="EU30 Done" start="28" end="28" type="bool"/>
<field name="EU31 Done" start="29" end="29" type="bool"/>
<field name="EU32 Done" start="30" end="30" type="bool"/>
<field name="MA3 Done" start="31" end="31" type="bool"/>
</register>
<register name="INSTDONE_2" length="1" num="0x207c">
<field name="VF Done" start="0" end="0" type="bool"/>
<field name="VS0 Done" start="1" end="1" type="bool"/>
<field name="GS Done" start="2" end="2" type="bool"/>
<field name="CL Done" start="3" end="3" type="bool"/>
<field name="SF Done" start="4" end="4" type="bool"/>
<field name="VME Done" start="5" end="5" type="bool"/>
<field name="PL Done" start="6" end="6" type="bool"/>
<field name="SO Done" start="7" end="7" type="bool"/>
<field name="SI Done" start="8" end="8" type="bool"/>
<field name="DG Done" start="9" end="9" type="bool"/>
<field name="FT Done" start="10" end="10" type="bool"/>
<field name="DM Done" start="11" end="11" type="bool"/>
<field name="SC Done" start="12" end="12" type="bool"/>
<field name="FL Done" start="13" end="13" type="bool"/>
<field name="QC Done" start="14" end="14" type="bool"/>
<field name="SVSM Done" start="15" end="15" type="bool"/>
<field name="WMFE Done" start="16" end="16" type="bool"/>
<field name="IZ Done" start="17" end="17" type="bool"/>
<field name="PSD Done" start="18" end="18" type="bool"/>
<field name="DAP Done" start="19" end="19" type="bool"/>
<field name="RCZ Done" start="20" end="20" type="bool"/>
<field name="VDI Done" start="21" end="21" type="bool"/>
<field name="RCPBE Done" start="22" end="22" type="bool"/>
<field name="RCPFE Done" start="23" end="23" type="bool"/>
<field name="MT Done" start="24" end="24" type="bool"/>
<field name="ISC Done" start="25" end="25" type="bool"/>
<field name="SVG Done" start="26" end="26" type="bool"/>
<field name="RCC Done" start="27" end="27" type="bool"/>
<field name="SVRW Done" start="28" end="28" type="bool"/>
<field name="WMBE Done" start="29" end="29" type="bool"/>
<field name="CS Done" start="30" end="30" type="bool"/>
<field name="GAM Done" start="31" end="31" type="bool"/>
</register>
<register name="VCS_INSTDONE" length="1" num="0x1206c">
<field name="Ring Enable" start="0" end="0" type="bool"/>
<field name="USB Done" start="1" end="1" type="bool"/>
<field name="QRC Done" start="2" end="2" type="bool"/>
<field name="SEC Done" start="3" end="3" type="bool"/>
<field name="MPC Done" start="4" end="4" type="bool"/>
<field name="VFT Done" start="5" end="5" type="bool"/>
<field name="BSP Done" start="6" end="6" type="bool"/>
<field name="VLF Done" start="7" end="7" type="bool"/>
<field name="VOP Done" start="8" end="8" type="bool"/>
<field name="VMC Done" start="9" end="9" type="bool"/>
<field name="VIP Done" start="10" end="10" type="bool"/>
<field name="VIT Done" start="11" end="11" type="bool"/>
<field name="VDS Done" start="12" end="12" type="bool"/>
<field name="VMX Done" start="13" end="13" type="bool"/>
<field name="VCP Done" start="14" end="14" type="bool"/>
<field name="VCD Done" start="15" end="15" type="bool"/>
<field name="VAD Done" start="16" end="16" type="bool"/>
<field name="VMD Done" start="17" end="17" type="bool"/>
<field name="VIS Done" start="18" end="18" type="bool"/>
<field name="VAC Done" start="19" end="19" type="bool"/>
<field name="VAM Done" start="20" end="20" type="bool"/>
<field name="JPG Done" start="21" end="21" type="bool"/>
<field name="VBP Done" start="22" end="22" type="bool"/>
<field name="VHR Done" start="23" end="23" type="bool"/>
<field name="VCI Done" start="24" end="24" type="bool"/>
<field name="VCR Done" start="25" end="25" type="bool"/>
<field name="VIN Done" start="26" end="26" type="bool"/>
<field name="VPR Done" start="27" end="27" type="bool"/>
<field name="VTQ Done" start="28" end="28" type="bool"/>
<field name="VCS Done" start="30" end="30" type="bool"/>
<field name="GAC Done" start="31" end="31" type="bool"/>
</register>
intel: genxml: add GFX_ARB_ERROR_RPT register Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-03-09 15:38:20 +00:00
<register name="GFX_ARB_ERROR_RPT" length="1" num="0x40a0">
<field name="TLB Page Fault Error" start="0" end="0" type="bool"/>
<field name="Context Page Fault Error" start="1" end="1" type="bool"/>
<field name="Invalid Page Directory entry error" start="2" end="2" type="bool"/>
<field name="Hardware Status Page Fault Error" start="3" end="3" type="bool"/>
<field name="TLB Page VTD Translation Error" start="4" end="4" type="bool"/>
<field name="Context Page VTD Translation Error" start="5" end="5" type="bool"/>
<field name="Page Directory Entry VTD Translation Error" start="6" end="6" type="bool"/>
<field name="Hardware Status Page VTD Translation Error" start="7" end="7" type="bool"/>
<field name="Unloaded PD Error" start="8" end="8" type="bool"/>
</register>
intel: genxml: add FAULT_REG register Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-03-10 14:27:53 +00:00
<register name="BCS_FAULT_REG" length="1" num="0x4294">
<field name="Valid Bit" start="0" end="0" type="bool"/>
<field name="Fault Type" start="1" end="2" type="uint">
<value name="Page Fault" value="0"/>
<value name="Invalid PD Fault" value="1"/>
<value name="Unloaded PD Fault" value="2"/>
<value name="Invalid and Unloaded PD fault" value="3"/>
</field>
<field name= "SRCID of Fault" start="3" end="10" type="uint"/>
intel/genxml: Fix a few invalid field widths A couple of typos found by inspecting field.end - field.start, revealed a few wide integers declared as bool and some that ended before they started. Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-05-05 19:36:25 +01:00
<field name="GTTSEL" start="11" end="11" type="uint">
intel: genxml: add FAULT_REG register Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-03-10 14:27:53 +00:00
<value name="PPGTT" value="0"/>
<value name="GGTT" value="1"/>
</field>
<field name="Virtual Address of Fault" start="12" end="31" type="address"/>
</register>
<register name="RCS_FAULT_REG" length="1" num="0x4094">
<field name="Valid Bit" start="0" end="0" type="bool"/>
<field name="Fault Type" start="1" end="2" type="uint">
<value name="Page Fault" value="0"/>
<value name="Invalid PD Fault" value="1"/>
<value name="Unloaded PD Fault" value="2"/>
<value name="Invalid and Unloaded PD fault" value="3"/>
</field>
<field name= "SRCID of Fault" start="3" end="10" type="uint"/>
intel/genxml: Fix a few invalid field widths A couple of typos found by inspecting field.end - field.start, revealed a few wide integers declared as bool and some that ended before they started. Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-05-05 19:36:25 +01:00
<field name="GTTSEL" start="11" end="11" type="uint">
intel: genxml: add FAULT_REG register Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-03-10 14:27:53 +00:00
<value name="PPGTT" value="0"/>
<value name="GGTT" value="1"/>
</field>
<field name="Virtual Address of Fault" start="12" end="31" type="address"/>
</register>
<register name="VCS_FAULT_REG" length="1" num="0x4194">
<field name="Valid Bit" start="0" end="0" type="bool"/>
<field name="Fault Type" start="1" end="2" type="uint">
<value name="Page Fault" value="0"/>
<value name="Invalid PD Fault" value="1"/>
<value name="Unloaded PD Fault" value="2"/>
<value name="Invalid and Unloaded PD fault" value="3"/>
</field>
<field name= "SRCID of Fault" start="3" end="10" type="uint"/>
intel/genxml: Fix a few invalid field widths A couple of typos found by inspecting field.end - field.start, revealed a few wide integers declared as bool and some that ended before they started. Cc: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-05-05 19:36:25 +01:00
<field name="GTTSEL" start="11" end="11" type="uint">
intel: genxml: add FAULT_REG register Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-03-10 14:27:53 +00:00
<value name="PPGTT" value="0"/>
<value name="GGTT" value="1"/>
</field>
<field name="Virtual Address of Fault" start="12" end="31" type="address"/>
</register>
intel: genxml: add RING_BUFFER_CTL registers Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Matt Turner <mattst88@gmail.com>
2017-03-10 17:27:01 +00:00
<register name="BCS_RING_BUFFER_CTL" length="1" num="0x2203c">
<field name="Ring Buffer Enable" start="0" end="0" type="bool"/>
<field name="Automatic Report Head Pointer" start="1" end="2" type="uint">
<value name="MI_AUTOREPORT_OFF" value="0"/>
<value name="MI_AUTOREPORT_64KB" value="1"/>
<value name="MI_AUTOREPORT_4KB" value="2"/>
<value name="MI_AUTOREPORT_128KB" value="3"/>
</field>
<field name="Disable Register Accesses" start="8" end="8" type="bool"/>
<field name="Semaphore Wait" start="10" end="10" type="bool"/>
<field name="RBWait" start="11" end="11" type="bool"/>
<field name="Buffer Length (in pages - 1)" start="12" end="20" type="uint"/>
</register>
<register name="RCS_RING_BUFFER_CTL" length="1" num="0x203c">
<field name="Ring Buffer Enable" start="0" end="0" type="bool"/>
<field name="Automatic Report Head Pointer" start="1" end="2" type="uint">
<value name="MI_AUTOREPORT_OFF" value="0"/>
<value name="MI_AUTOREPORT_64KBMI_AUTOREPORT_4KB" value="1"/>
<value name="MI_AUTOREPORT_128KB" value="3"/>
</field>
<field name="Semaphore Wait" start="10" end="10" type="bool"/>
<field name="RBWait" start="11" end="11" type="bool"/>
<field name="Buffer Length (in pages - 1)" start="12" end="20" type="uint"/>
</register>
<register name="VCS_RING_BUFFER_CTL" length="1" num="0x1203c">
<field name="Ring Buffer Enable" start="0" end="0" type="bool"/>
<field name="Automatic Report Head Pointer" start="1" end="2" type="uint">
<value name="MI_AUTOREPORT_OFF" value="0"/>
<value name="MI_AUTOREPORT_64KB" value="1"/>
<value name="MI_AUTOREPORT_4KB" value="2"/>
<value name="MI_AUTOREPORT_128KB" value="3"/>
</field>
<field name="Disable Register Accesses" start="8" end="8" type="bool"/>
<field name="Semaphore Wait" start="10" end="10" type="bool"/>
<field name="RBWait" start="11" end="11" type="bool"/>
<field name="Buffer Length (in pages - 1)" start="12" end="20" type="uint"/>
</register>
intel: genxml: add INSTPM/CS_DEBUG_MODE2 registers Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-03-02 16:44:14 +00:00
<register name="INSTPM" length="1" num="0x20c0">
<field name="3D State Instruction Disable" start="1" end="1" type="bool"/>
<field name="3D Rendering Instruction Disable" start="2" end="2" type="bool"/>
<field name="Media Instruction Disable" start="3" end="3" type="bool"/>
<field name="CONSTANT_BUFFER Address Offset Disable" start="6" end="6" type="bool"/>
intel/genxml: Add bitmasks for CS_DEBUG_MODE2/INSTPM. Reviewed-by: Jason Ekstrand <jason@jlekstrand.net> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
2018-06-15 11:43:45 -07:00
<field name="3D State Instruction Disable Mask" start="17" end="17" type="bool"/>
<field name="3D Rendering Instruction Disable Mask" start="18" end="18" type="bool"/>
<field name="Media Instruction Disable Mask" start="19" end="19" type="bool"/>
<field name="CONSTANT_BUFFER Address Offset Disable Mask" start="22" end="22" type="bool"/>
intel: genxml: add INSTPM/CS_DEBUG_MODE2 registers Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
2018-03-02 16:44:14 +00:00
</register>
genxml: Add GEN6 genxml Not used yet, but let's put it here for now.
2016-04-06 17:07:08 -07:00
</genxml>
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