2017-09-14 17:57:17 -07:00
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# Copyright © 2017 Intel Corporation
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# Permission is hereby granted, free of charge, to any person obtaining a copy
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# of this software and associated documentation files (the "Software"), to deal
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# in the Software without restriction, including without limitation the rights
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# to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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# copies of the Software, and to permit persons to whom the Software is
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# furnished to do so, subject to the following conditions:
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# The above copyright notice and this permission notice shall be included in
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# all copies or substantial portions of the Software.
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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# FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE
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# AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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# LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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# OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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# SOFTWARE.
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2023-11-01 12:51:33 -07:00
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intel_nir_files = files(
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'intel_nir.h',
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'intel_nir.c',
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2023-11-01 15:15:43 -07:00
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'intel_nir_blockify_uniform_loads.c',
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'intel_nir_clamp_image_1d_2d_array_sizes.c',
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'intel_nir_clamp_per_vertex_loads.c',
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'intel_nir_lower_conversions.c',
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'intel_nir_lower_non_uniform_barycentric_at_sample.c',
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'intel_nir_lower_non_uniform_resource_intel.c',
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2023-09-05 16:11:56 +03:00
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'intel_nir_lower_printf.c',
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2023-11-01 15:15:43 -07:00
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'intel_nir_lower_shading_rate_output.c',
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'intel_nir_lower_sparse.c',
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'intel_nir_lower_texture.c',
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'intel_nir_opt_peephole_ffma.c',
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'intel_nir_opt_peephole_imul32x16.c',
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'intel_nir_tcs_workarounds.c',
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2023-11-01 12:51:33 -07:00
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)
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2024-02-09 15:37:14 -08:00
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libintel_compiler_brw_files = files(
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2017-09-14 17:57:17 -07:00
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'brw_cfg.cpp',
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'brw_cfg.h',
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2024-02-14 18:17:59 -08:00
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'brw_compile_gs.cpp',
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'brw_compile_tcs.cpp',
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'brw_compile_vs.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_compiler.c',
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'brw_compiler.h',
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'brw_dead_control_flow.cpp',
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2019-04-15 21:59:50 -07:00
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'brw_debug_recompile.c',
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2023-11-16 01:16:45 -08:00
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'brw_def_analysis.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_disasm.c',
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2024-02-29 17:53:53 -08:00
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'brw_disasm_info.cpp',
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2017-11-16 11:43:51 -08:00
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'brw_disasm_info.h',
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2022-06-30 01:47:09 -07:00
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'brw_eu.c',
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2017-09-14 17:57:17 -07:00
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'brw_eu_compact.c',
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'brw_eu_defines.h',
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'brw_eu_emit.c',
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'brw_eu.h',
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'brw_eu_validate.c',
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2017-06-15 15:23:57 -07:00
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'brw_fs_bank_conflicts.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_fs_builder.h',
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'brw_fs_cmod_propagation.cpp',
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'brw_fs_combine_constants.cpp',
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'brw_fs_copy_propagation.cpp',
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'brw_fs.cpp',
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'brw_fs_cse.cpp',
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'brw_fs_dead_code_eliminate.cpp',
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'brw_fs_generator.cpp',
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'brw_fs.h',
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'brw_fs_live_variables.cpp',
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'brw_fs_live_variables.h',
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2024-01-04 23:27:04 -08:00
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'brw_fs_lower.cpp',
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2023-10-10 15:35:46 -07:00
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'brw_fs_lower_dpas.cpp',
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2024-01-04 22:07:17 -08:00
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'brw_fs_lower_integer_multiplication.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_fs_lower_pack.cpp',
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2018-12-29 04:00:13 -08:00
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'brw_fs_lower_regioning.cpp',
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2024-01-04 22:33:59 -08:00
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'brw_fs_lower_simd_width.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_fs_nir.cpp',
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2024-01-04 17:31:42 -08:00
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'brw_fs_opt.cpp',
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2024-01-04 23:26:50 -08:00
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'brw_fs_opt_algebraic.cpp',
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2024-01-04 17:54:25 -08:00
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'brw_fs_opt_virtual_grfs.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_fs_reg_allocate.cpp',
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'brw_fs_register_coalesce.cpp',
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'brw_fs_saturate_propagation.cpp',
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2018-11-09 14:13:37 -08:00
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'brw_fs_scoreboard.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_fs_sel_peephole.cpp',
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2022-08-19 12:40:20 -07:00
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'brw_fs_thread_payload.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_fs_validate.cpp',
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'brw_fs_visitor.cpp',
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2024-01-04 22:39:57 -08:00
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'brw_fs_workaround.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_inst.h',
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2016-03-06 18:13:59 -08:00
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'brw_ir.h',
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2017-09-14 17:57:17 -07:00
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'brw_ir_allocator.h',
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2016-03-06 18:11:20 -08:00
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'brw_ir_analysis.h',
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2017-09-14 17:57:17 -07:00
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'brw_ir_fs.h',
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2020-03-26 14:59:02 -07:00
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'brw_ir_performance.h',
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'brw_ir_performance.cpp',
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2022-06-29 14:25:19 -07:00
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'brw_isa_info.h',
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2022-06-27 12:24:58 -07:00
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'brw_lower_logical_sends.cpp',
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2021-10-29 12:27:45 -07:00
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'brw_mesh.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_nir.h',
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'brw_nir.c',
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'brw_nir_analyze_ubo_ranges.c',
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2023-06-13 19:45:49 -07:00
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'brw_nir_lower_cooperative_matrix.c',
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2017-10-06 10:08:11 -07:00
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'brw_nir_lower_cs_intrinsics.c',
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2019-09-27 16:23:46 -07:00
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'brw_nir_lower_alpha_to_coverage.c',
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2020-08-06 16:22:15 -05:00
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'brw_nir_lower_intersection_shader.c',
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2021-06-21 13:44:53 +03:00
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'brw_nir_lower_ray_queries.c',
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2020-08-06 12:59:49 -05:00
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'brw_nir_lower_rt_intrinsics.c',
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2020-08-06 13:53:34 -05:00
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'brw_nir_lower_shader_calls.c',
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2021-02-03 11:34:46 -08:00
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'brw_nir_lower_storage_image.c',
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2020-08-06 12:59:49 -05:00
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'brw_nir_rt.h',
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2020-08-06 13:20:07 -05:00
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'brw_nir_rt.c',
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2020-08-06 12:44:57 -05:00
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'brw_nir_rt_builder.h',
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2017-09-14 17:57:17 -07:00
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'brw_packed_float.c',
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'brw_predicated_break.cpp',
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2022-06-29 15:19:57 -07:00
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'brw_prim.h',
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2021-10-06 22:37:42 -07:00
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'brw_private.h',
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2017-09-14 17:57:17 -07:00
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'brw_reg.h',
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'brw_reg_type.c',
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'brw_reg_type.h',
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2020-08-06 12:53:47 -05:00
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'brw_rt.h',
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2017-09-14 17:57:17 -07:00
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'brw_schedule_instructions.cpp',
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'brw_shader.cpp',
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2022-11-07 17:35:16 -08:00
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'brw_simd_selection.cpp',
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2017-09-14 17:57:17 -07:00
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'brw_vue_map.c',
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)
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2024-02-09 15:30:57 -08:00
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brw_device_sha1_gen_src = custom_target('brw_device_sha1_gen.c',
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input : ['brw_device_sha1_gen_c.py', '../dev/intel_device_info.py'],
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output : ['brw_device_sha1_gen.c'],
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command : [prog_python, '@INPUT0@', '--outdir', meson.current_build_dir()])
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intel/brw: Handle fsign optimization in a NIR algebraic pass
This is a lot less code, and it makes it easier to experiment with other
pattern-based optimizations in the future.
The results here are nearly identical to the results I got from Ken's
"intel/brw: Make fsign (for 16/32-bit) in SSA form"... which are not
particularly good.
In this commit and in Ken's, all of the shader-db shaders hurt for
spills and fills are from Deus Ex Mankind Divided. Each shader has a
bunch of texture instructions with a single fsign between the
blocks. With the dependency on the flag removed, the scheduler puts all
of the texture instructions at the start... and there are a LOT of them.
shader-db:
All Intel platforms had similar results. (Meteor Lake shown)
total instructions in shared programs: 19647060 -> 19650207 (0.02%)
instructions in affected programs: 734718 -> 737865 (0.43%)
helped: 382 / HURT: 1984
total cycles in shared programs: 823238442 -> 822785913 (-0.05%)
cycles in affected programs: 426901157 -> 426448628 (-0.11%)
helped: 3408 / HURT: 3671
total spills in shared programs: 3887 -> 3891 (0.10%)
spills in affected programs: 256 -> 260 (1.56%)
helped: 0 / HURT: 4
total fills in shared programs: 3236 -> 3306 (2.16%)
fills in affected programs: 882 -> 952 (7.94%)
helped: 0 / HURT: 12
LOST: 37
GAINED: 34
fossil-db:
DG2 and Meteor Lake had similar results. (Meteor Lake shown)
Totals:
Instrs: 154005469 -> 154008294 (+0.00%); split: -0.00%, +0.00%
Cycle count: 17551859277 -> 17554293955 (+0.01%); split: -0.02%, +0.04%
Spill count: 142078 -> 142090 (+0.01%)
Fill count: 266761 -> 266729 (-0.01%); split: -0.02%, +0.01%
Max live registers: 32593578 -> 32593858 (+0.00%)
Max dispatch width: 5535944 -> 5536816 (+0.02%); split: +0.02%, -0.01%
Totals from 5867 (0.93% of 631350) affected shaders:
Instrs: 5475544 -> 5478369 (+0.05%); split: -0.04%, +0.09%
Cycle count: 1649032029 -> 1651466707 (+0.15%); split: -0.24%, +0.39%
Spill count: 26411 -> 26423 (+0.05%)
Fill count: 57364 -> 57332 (-0.06%); split: -0.10%, +0.04%
Max live registers: 431561 -> 431841 (+0.06%)
Max dispatch width: 49784 -> 50656 (+1.75%); split: +2.38%, -0.63%
Tiger Lake
Totals:
Instrs: 149530671 -> 149533588 (+0.00%); split: -0.00%, +0.00%
Cycle count: 15261418953 -> 15264764921 (+0.02%); split: -0.00%, +0.03%
Spill count: 60317 -> 60316 (-0.00%); split: -0.02%, +0.01%
Max live registers: 32249201 -> 32249464 (+0.00%)
Max dispatch width: 5540608 -> 5540584 (-0.00%)
Totals from 5862 (0.93% of 630309) affected shaders:
Instrs: 4740800 -> 4743717 (+0.06%); split: -0.04%, +0.10%
Cycle count: 566531248 -> 569877216 (+0.59%); split: -0.13%, +0.72%
Spill count: 11709 -> 11708 (-0.01%); split: -0.09%, +0.08%
Max live registers: 424560 -> 424823 (+0.06%)
Max dispatch width: 50304 -> 50280 (-0.05%)
Ice Lake
Totals:
Instrs: 150499705 -> 150502608 (+0.00%); split: -0.00%, +0.00%
Cycle count: 15105629116 -> 15105425880 (-0.00%); split: -0.00%, +0.00%
Spill count: 60087 -> 60090 (+0.00%)
Fill count: 100542 -> 100541 (-0.00%); split: -0.00%, +0.00%
Max live registers: 32605215 -> 32605495 (+0.00%)
Max dispatch width: 5617752 -> 5617792 (+0.00%); split: +0.00%, -0.00%
Totals from 5882 (0.93% of 634934) affected shaders:
Instrs: 4737206 -> 4740109 (+0.06%); split: -0.04%, +0.10%
Cycle count: 598882104 -> 598678868 (-0.03%); split: -0.08%, +0.05%
Spill count: 10278 -> 10281 (+0.03%)
Fill count: 22504 -> 22503 (-0.00%); split: -0.01%, +0.01%
Max live registers: 424184 -> 424464 (+0.07%)
Max dispatch width: 50216 -> 50256 (+0.08%); split: +0.25%, -0.18%
Skylake
Totals:
Instrs: 139092612 -> 139095257 (+0.00%); split: -0.00%, +0.00%
Cycle count: 14533550285 -> 14533544716 (-0.00%); split: -0.00%, +0.00%
Spill count: 58176 -> 58172 (-0.01%)
Fill count: 95877 -> 95796 (-0.08%)
Max live registers: 31924594 -> 31924874 (+0.00%)
Max dispatch width: 5484568 -> 5484552 (-0.00%); split: +0.00%, -0.00%
Totals from 5789 (0.93% of 625512) affected shaders:
Instrs: 4481987 -> 4484632 (+0.06%); split: -0.04%, +0.10%
Cycle count: 578310124 -> 578304555 (-0.00%); split: -0.05%, +0.05%
Spill count: 9248 -> 9244 (-0.04%)
Fill count: 19677 -> 19596 (-0.41%)
Max live registers: 415340 -> 415620 (+0.07%)
Max dispatch width: 49720 -> 49704 (-0.03%); split: +0.10%, -0.13%
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095>
2024-05-01 21:02:13 -07:00
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brw_nir_lower_fsign = custom_target(
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'brw_nir_lower_fsign.c',
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input : 'brw_nir_lower_fsign.py',
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output : 'brw_nir_lower_fsign.c',
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command : [
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prog_python, '@INPUT@', '-p', dir_compiler_nir,
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],
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depend_files : nir_algebraic_depends,
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capture : true,
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)
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2017-09-14 17:57:17 -07:00
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brw_nir_trig = custom_target(
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'brw_nir_trig_workarounds.c',
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input : 'brw_nir_trig_workarounds.py',
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output : 'brw_nir_trig_workarounds.c',
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2017-12-11 15:56:08 -08:00
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command : [
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2022-08-10 02:04:51 +03:00
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prog_python, '@INPUT@', '-p', dir_compiler_nir,
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2017-12-11 15:56:08 -08:00
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],
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2022-02-16 14:02:16 -08:00
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depend_files : nir_algebraic_depends,
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2017-09-14 17:57:17 -07:00
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capture : true,
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)
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2024-02-09 15:37:14 -08:00
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libintel_compiler_brw = static_library(
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2017-09-14 17:57:17 -07:00
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'intel_compiler',
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intel/brw: Handle fsign optimization in a NIR algebraic pass
This is a lot less code, and it makes it easier to experiment with other
pattern-based optimizations in the future.
The results here are nearly identical to the results I got from Ken's
"intel/brw: Make fsign (for 16/32-bit) in SSA form"... which are not
particularly good.
In this commit and in Ken's, all of the shader-db shaders hurt for
spills and fills are from Deus Ex Mankind Divided. Each shader has a
bunch of texture instructions with a single fsign between the
blocks. With the dependency on the flag removed, the scheduler puts all
of the texture instructions at the start... and there are a LOT of them.
shader-db:
All Intel platforms had similar results. (Meteor Lake shown)
total instructions in shared programs: 19647060 -> 19650207 (0.02%)
instructions in affected programs: 734718 -> 737865 (0.43%)
helped: 382 / HURT: 1984
total cycles in shared programs: 823238442 -> 822785913 (-0.05%)
cycles in affected programs: 426901157 -> 426448628 (-0.11%)
helped: 3408 / HURT: 3671
total spills in shared programs: 3887 -> 3891 (0.10%)
spills in affected programs: 256 -> 260 (1.56%)
helped: 0 / HURT: 4
total fills in shared programs: 3236 -> 3306 (2.16%)
fills in affected programs: 882 -> 952 (7.94%)
helped: 0 / HURT: 12
LOST: 37
GAINED: 34
fossil-db:
DG2 and Meteor Lake had similar results. (Meteor Lake shown)
Totals:
Instrs: 154005469 -> 154008294 (+0.00%); split: -0.00%, +0.00%
Cycle count: 17551859277 -> 17554293955 (+0.01%); split: -0.02%, +0.04%
Spill count: 142078 -> 142090 (+0.01%)
Fill count: 266761 -> 266729 (-0.01%); split: -0.02%, +0.01%
Max live registers: 32593578 -> 32593858 (+0.00%)
Max dispatch width: 5535944 -> 5536816 (+0.02%); split: +0.02%, -0.01%
Totals from 5867 (0.93% of 631350) affected shaders:
Instrs: 5475544 -> 5478369 (+0.05%); split: -0.04%, +0.09%
Cycle count: 1649032029 -> 1651466707 (+0.15%); split: -0.24%, +0.39%
Spill count: 26411 -> 26423 (+0.05%)
Fill count: 57364 -> 57332 (-0.06%); split: -0.10%, +0.04%
Max live registers: 431561 -> 431841 (+0.06%)
Max dispatch width: 49784 -> 50656 (+1.75%); split: +2.38%, -0.63%
Tiger Lake
Totals:
Instrs: 149530671 -> 149533588 (+0.00%); split: -0.00%, +0.00%
Cycle count: 15261418953 -> 15264764921 (+0.02%); split: -0.00%, +0.03%
Spill count: 60317 -> 60316 (-0.00%); split: -0.02%, +0.01%
Max live registers: 32249201 -> 32249464 (+0.00%)
Max dispatch width: 5540608 -> 5540584 (-0.00%)
Totals from 5862 (0.93% of 630309) affected shaders:
Instrs: 4740800 -> 4743717 (+0.06%); split: -0.04%, +0.10%
Cycle count: 566531248 -> 569877216 (+0.59%); split: -0.13%, +0.72%
Spill count: 11709 -> 11708 (-0.01%); split: -0.09%, +0.08%
Max live registers: 424560 -> 424823 (+0.06%)
Max dispatch width: 50304 -> 50280 (-0.05%)
Ice Lake
Totals:
Instrs: 150499705 -> 150502608 (+0.00%); split: -0.00%, +0.00%
Cycle count: 15105629116 -> 15105425880 (-0.00%); split: -0.00%, +0.00%
Spill count: 60087 -> 60090 (+0.00%)
Fill count: 100542 -> 100541 (-0.00%); split: -0.00%, +0.00%
Max live registers: 32605215 -> 32605495 (+0.00%)
Max dispatch width: 5617752 -> 5617792 (+0.00%); split: +0.00%, -0.00%
Totals from 5882 (0.93% of 634934) affected shaders:
Instrs: 4737206 -> 4740109 (+0.06%); split: -0.04%, +0.10%
Cycle count: 598882104 -> 598678868 (-0.03%); split: -0.08%, +0.05%
Spill count: 10278 -> 10281 (+0.03%)
Fill count: 22504 -> 22503 (-0.00%); split: -0.01%, +0.01%
Max live registers: 424184 -> 424464 (+0.07%)
Max dispatch width: 50216 -> 50256 (+0.08%); split: +0.25%, -0.18%
Skylake
Totals:
Instrs: 139092612 -> 139095257 (+0.00%); split: -0.00%, +0.00%
Cycle count: 14533550285 -> 14533544716 (-0.00%); split: -0.00%, +0.00%
Spill count: 58176 -> 58172 (-0.01%)
Fill count: 95877 -> 95796 (-0.08%)
Max live registers: 31924594 -> 31924874 (+0.00%)
Max dispatch width: 5484568 -> 5484552 (-0.00%); split: +0.00%, -0.00%
Totals from 5789 (0.93% of 625512) affected shaders:
Instrs: 4481987 -> 4484632 (+0.06%); split: -0.04%, +0.10%
Cycle count: 578310124 -> 578304555 (-0.00%); split: -0.05%, +0.05%
Spill count: 9248 -> 9244 (-0.04%)
Fill count: 19677 -> 19596 (-0.41%)
Max live registers: 415340 -> 415620 (+0.07%)
Max dispatch width: 49720 -> 49704 (-0.03%); split: +0.10%, -0.13%
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/29095>
2024-05-01 21:02:13 -07:00
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[libintel_compiler_brw_files, intel_nir_files, brw_nir_lower_fsign, brw_nir_trig, ir_expression_operation_h, [brw_device_sha1_gen_src]],
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2023-08-02 19:24:14 +08:00
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include_directories : [inc_include, inc_src, inc_intel],
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2020-04-24 13:10:41 -07:00
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c_args : [no_override_init_args],
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gnu_symbol_visibility : 'hidden',
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2023-02-15 10:09:57 -08:00
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dependencies : [idep_nir_headers, idep_mesautil, idep_intel_dev],
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2017-09-14 17:57:17 -07:00
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build_by_default : false,
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)
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2024-02-28 17:38:04 -08:00
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idep_intel_compiler_brw = declare_dependency(
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link_with : [libintel_compiler_brw],
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2024-02-28 17:41:46 -08:00
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dependencies : [
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idep_nir,
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],
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2024-02-28 17:38:04 -08:00
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)
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2021-02-19 10:34:49 -06:00
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# For now this tool is only going to be used by Anv
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2023-08-31 13:16:29 -04:00
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if get_option('intel-clc') == 'system'
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prog_intel_clc = find_program('intel_clc', native : true)
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dep_prog_intel_clc = []
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elif with_intel_clc
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2021-02-19 10:34:49 -06:00
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prog_intel_clc = executable(
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'intel_clc',
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2024-02-14 15:59:45 -08:00
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[
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'intel_clc.c',
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'brw_kernel.c',
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# Use just the nir_options part of ELK instead of fully linking.
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'elk/elk_nir_options.h',
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'elk/elk_nir_options.c',
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],
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2024-05-10 22:40:52 +03:00
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link_with : [libisl],
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2023-08-02 19:24:14 +08:00
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include_directories : [inc_include, inc_src, inc_intel],
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2021-02-19 10:34:49 -06:00
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c_args : [pre_args, no_override_init_args],
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2022-10-01 00:36:59 -07:00
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link_args : [ld_args_build_id],
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2024-02-28 17:38:04 -08:00
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dependencies : [idep_nir, idep_vtn, idep_mesaclc, idep_mesautil, idep_intel_dev,
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idep_intel_compiler_brw],
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2024-03-07 13:18:46 +02:00
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# If we can run host binaries directly, just build intel_clc for the host.
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# Most commonly this happens when doing a cross compile from an x86_64 build
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# machine to an x86 host
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native : not meson.can_run_host_binaries(),
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2024-02-12 15:06:06 +02:00
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install : get_option('install-intel-clc'),
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2021-02-19 10:34:49 -06:00
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)
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2023-08-31 13:16:29 -04:00
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dep_prog_intel_clc = [prog_intel_clc]
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2021-02-19 10:34:49 -06:00
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endif
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2017-09-14 17:57:17 -07:00
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if with_tests
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2021-10-11 23:27:53 -07:00
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test(
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2024-02-09 15:37:14 -08:00
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'intel_compiler_brw_tests',
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2021-10-11 23:27:53 -07:00
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executable(
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2024-02-09 15:37:14 -08:00
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'intel_compiler_brw_tests',
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2021-10-11 23:27:53 -07:00
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files(
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2023-11-03 22:41:59 -07:00
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'test_predicated_break.cpp',
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2021-10-11 23:27:53 -07:00
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'test_eu_compact.cpp',
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'test_eu_validate.cpp',
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'test_fs_cmod_propagation.cpp',
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2024-01-17 18:32:11 -08:00
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'test_fs_combine_constants.cpp',
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2021-10-11 23:27:53 -07:00
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'test_fs_copy_propagation.cpp',
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'test_fs_saturate_propagation.cpp',
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'test_fs_scoreboard.cpp',
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2021-10-06 22:37:42 -07:00
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'test_simd_selection.cpp',
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2021-10-11 23:27:53 -07:00
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'test_vf_float_conversions.cpp',
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2018-11-19 13:44:15 -08:00
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),
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2021-10-11 23:27:53 -07:00
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ir_expression_operation_h,
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2023-08-02 19:24:14 +08:00
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include_directories : [inc_include, inc_src, inc_intel],
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2024-05-10 22:40:52 +03:00
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link_with : libisl,
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2024-02-28 17:38:04 -08:00
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dependencies : [idep_gtest, idep_nir, idep_mesautil, idep_intel_dev,
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idep_intel_compiler_brw],
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2021-10-11 23:27:53 -07:00
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),
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suite : ['intel'],
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2023-02-23 10:49:37 +00:00
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protocol : 'gtest',
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2021-10-11 23:27:53 -07:00
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)
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2017-09-14 17:57:17 -07:00
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endif
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2024-02-09 13:55:14 -08:00
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if with_intel_tools
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bison_command = []
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if yacc_is_bison
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bison_command = [
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prog_bison, '@INPUT@', '--defines=@OUTPUT1@',
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'--output=@OUTPUT0@'
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]
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else
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bison_command = [
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prog_bison, '-H', '@OUTPUT1@',
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'-o', '@OUTPUT0@', '@INPUT@'
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]
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endif
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brw_gram_tab = custom_target(
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'brw_gram.tab.[ch]',
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input : 'brw_gram.y',
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output : ['brw_gram.tab.c', 'brw_gram.tab.h'],
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command : bison_command
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)
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brw_lex_yy_c = custom_target(
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'brw_lex.yy.c',
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input : 'brw_lex.l',
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output : 'brw_lex.yy.c',
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command : [prog_flex, '-o', '@OUTPUT@', '@INPUT@']
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)
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brw_asm_tool = executable(
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'brw_asm',
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['brw_asm_tool.c', brw_gram_tab[0], brw_gram_tab[1], brw_lex_yy_c],
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2024-02-28 17:38:04 -08:00
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dependencies : [idep_mesautil, dep_thread, idep_intel_dev,
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idep_intel_compiler_brw],
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2024-02-09 13:55:14 -08:00
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include_directories : [inc_include, inc_src, inc_intel],
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c_args : [no_override_init_args],
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gnu_symbol_visibility : 'hidden',
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install : true
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)
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asm_testcases = [
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['skl', 'gfx9'],
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['icl', 'gfx11'],
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['tgl', 'gfx12'],
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['dg2', 'gfx12.5'],
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]
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test_runner = find_program('tests/run-test.py')
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foreach testcase : asm_testcases
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_gen_name = testcase[0]
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_gen_num = testcase[1]
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_gen_folder = join_paths(meson.current_source_dir(), 'tests',
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_gen_num.replace('gfx', 'gen'))
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test(
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'brw_asm_' + _gen_num, test_runner,
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args : [
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'--brw_asm', brw_asm_tool,
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'--gen_name', _gen_name,
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|
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'--gen_folder', _gen_folder,
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],
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suite : 'intel',
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)
|
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endforeach
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|
brw_disasm_tool = executable(
|
|
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|
'brw_disasm',
|
|
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files('brw_disasm_tool.c'),
|
2024-02-28 17:38:04 -08:00
|
|
|
dependencies : [idep_mesautil, dep_thread, idep_intel_dev,
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|
|
|
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idep_intel_compiler_brw],
|
2024-02-09 13:55:14 -08:00
|
|
|
include_directories : [inc_include, inc_src, inc_intel],
|
|
|
|
|
c_args : [no_override_init_args],
|
|
|
|
|
gnu_symbol_visibility : 'hidden',
|
|
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|
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install : true
|
|
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)
|
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endif
|
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|
2024-01-19 11:44:58 -08:00
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subdir('elk')
|