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mesa/src/asahi/lib/cmdbuf.xml

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asahi: Use a header more like Intel's GenXML We're trying to converge on a common schema. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>
2022-09-30 21:16:35 -04:00
<?xml version="1.0" ?>
<genxml>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
<enum name="Channel">
<value name="R" value="0"/>
<value name="G" value="1"/>
<value name="B" value="2"/>
<value name="A" value="3"/>
<value name="1" value="4"/>
<value name="0" value="5"/>
</enum>
<enum name="ZS Func">
<value name="Never" value="0"/>
<value name="Less" value="1"/>
<value name="Equal" value="2"/>
<value name="Lequal" value="3"/>
<value name="Greater" value="4"/>
<value name="Not Equal" value="5"/>
<value name="Gequal" value="6"/>
<value name="Always" value="7"/>
</enum>
<enum name="Compare func">
<value name="Lequal" value="0"/>
<value name="Gequal" value="1"/>
<value name="Less" value="2"/>
<value name="Greater" value="3"/>
<value name="Equal" value="4"/>
<value name="Not Equal" value="5"/>
<value name="Always" value="6"/>
<value name="Never" value="7"/>
</enum>
<enum name="Stencil Op">
<value name="Keep" value="0"/>
<value name="Zero" value="1"/>
<value name="Replace" value="2"/>
<value name="Incr Sat" value="3"/>
<value name="Decr Sat" value="4"/>
<value name="Invert" value="5"/>
<value name="Incr Wrap" value="6"/>
<value name="Decr Wrap" value="7"/>
</enum>
asahi: Add XML used for visibility tests Aka occlusion queries. There is an annoying limitation in the hardware (reflected in Metal) that only a single buffer may be bound per render pass, with the per-draw settings merely specifying an offset. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-04-02 14:58:44 -04:00
<enum name="Visibility Mode">
<value name="None" value="0"/>
<value name="Counting" value="2"/>
<value name="Boolean" value="3"/>
</enum>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
<enum name="Polygon Mode">
<value name="Fill" value="0"/>
<value name="Line" value="1"/>
<value name="Point" value="2"/>
</enum>
<enum name="Primitive">
<value name="Points" value="0"/>
<value name="Lines" value="1"/>
<value name="Line strip" value="3"/>
<value name="Line loop" value="5"/>
<value name="Triangles" value="6"/>
<value name="Triangle strip" value="9"/>
<value name="Triangle fan" value="10"/>
<value name="Quads" value="14"/> <!-- guess, confirm with piglit later XXX -->
<value name="Quad strip" value="15"/> <!-- guess, confirm with piglit later XXX -->
</enum>
asahi: Identify object type field via PowerVR src/imagination/csbgen/rogue_ppp.xml STATE_ISPA bits 28. Looks like that got split into two structs in AGX (with info duplicated?) but yeah I have a lot to work with here. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 14:43:18 -04:00
<enum name="Object Type">
<value name="Triangle" value="0"/>
<value name="Line" value="1"/>
<value name="Point sprite UV=10" value="2"/>
<value name="Point sprite UV=01" value="4"/>
</enum>
asahi: Add layout enum to XML Used for textures and render targets. There are more values here, probably for other tiling schemes and compression. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11086>
2021-05-31 03:19:35 +05:30
<enum name="Layout">
<value name="Linear" value="0"/>
asahi: Fix using multiple textures/samplers The counts for textures/samplers are specified in the bind texture/sampler packets. What's in the bind pipeline appear to be... hints? of some kind? It's a direct function of the numbers of textures and samplers, but much more coarse. Unknown purpose. This should be correct for up to 48 textures and at least 8 samplers. For more than 48 textures, Metal switches to a "bindless" mode, where the textures are instead bound with a bind uniform packet, ts* is no longer read in the shader, and instead registers and immediates are used to index the texture with a substantial preshader. Details TBD. We don't need to worry about that for a long while, though. Fixes a number of dEQPs. dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.array_in_struct.sampler2D_samplerCube_both,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.array_in_struct.sampler2D_samplerCube_fragment,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.array_in_struct.sampler2D_samplerCube_vertex,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.nested_structs_arrays.sampler2D_samplerCube_both,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.nested_structs_arrays.sampler2D_samplerCube_fragment,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.nested_structs_arrays.sampler2D_samplerCube_vertex,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.array_in_struct.sampler2D_samplerCube_both,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.array_in_struct.sampler2D_samplerCube_fragment,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.array_in_struct.sampler2D_samplerCube_vertex,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.nested_structs_arrays.sampler2D_samplerCube_both,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.nested_structs_arrays.sampler2D_samplerCube_fragment,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.nested_structs_arrays.sampler2D_samplerCube_vertex,Crash Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-01-18 21:54:22 -05:00
<!-- Default layout if no other layout is set -->
<value name="Null" value="1"/>
asahi: Rename 'tiled 64x64' to 'twiddled' To account for non-64x64 tile sizes, as well as the other forms of tiling that may come up with compression. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>
2022-08-20 13:10:49 -04:00
<!-- Morton order -->
<value name="Twiddled" value="2"/>
asahi: Identify compressed render target fields We won't be implementing AGX compression for a while, but this gets some unknowns out of the way when looking at dumps from Metal that use it. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>
2022-06-12 11:08:07 -04:00
<!-- With a metadata buffer -->
<value name="Compressed" value="3"/>
asahi: Add layout enum to XML Used for textures and render targets. There are more values here, probably for other tiling schemes and compression. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11086>
2021-05-31 03:19:35 +05:30
</enum>
asahi: Add format enums Split it up into the underlying parts. Now we can decode every format accessible in Metal. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11086>
2021-05-31 14:37:06 -04:00
<enum name="Channels">
<value name="R8" value="0x00"/>
<value name="R16" value="0x09"/>
<value name="R8G8" value="0x0A"/>
<value name="R5G6B5" value="0x0B"/>
<value name="R4G4B4A4" value="0x0C"/>
<value name="A1R5G5B5" value="0x0D"/>
<value name="R5G5B5A1" value="0x0E"/>
<value name="R32" value="0x21"/>
<value name="R16G16" value="0x23"/>
<value name="R11G11B10" value="0x25"/>
<value name="R10G10B10A2" value="0x26"/>
<value name="R9G9B9E5" value="0x27"/>
<value name="R8G8B8A8" value="0x28"/>
<value name="R32G32" value="0x31"/>
<value name="R16G16B16A16" value="0x32"/>
<value name="R32G32B32A32" value="0x38"/>
<value name="GBGR 422" value="0x40"/> <!-- Subsampled, swizzle BRG1 -->
<value name="BGRG 422" value="0x41"/> <!-- Subsampled, swizzle BRG1 -->
<!-- Compressed -->
<value name="PVRTC 2bpp" value="0x50"/>
<value name="PVRTC 4bpp" value="0x51"/>
<value name="ETC2 RGB8" value="0x58"/>
<value name="ETC2 RGBA8" value="0x59"/>
<value name="ETC2 RGB8A1" value="0x5A"/>
<value name="EAC R11" value="0x5B"/>
<value name="EAC RG11" value="0x5C"/>
asahi: Fix ASTC enums The ASTC enum only encodes the block width/height. By contrast the LDR/HDR/sRGB distinction is encoded as UNORM/Float and via the sRGB bit. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>
2022-08-20 12:26:58 -04:00
<!-- For LDR use with UNORM/no-sRGB, for sRGB use with UNORM/sRGB, for HDR
use with FLOAT/no-sRGB -->
<value name="ASTC 4x4" value="0x60"/>
<value name="ASTC 5x4" value="0x61"/>
<value name="ASTC 5x5" value="0x62"/>
<value name="ASTC 6x5" value="0x63"/>
<value name="ASTC 6x6" value="0x64"/>
<value name="ASTC 8x5" value="0x65"/>
<value name="ASTC 8x6" value="0x66"/>
<value name="ASTC 8x8" value="0x67"/>
<value name="ASTC 10x5" value="0x68"/>
<value name="ASTC 10x6" value="0x69"/>
<value name="ASTC 10x8" value="0x6A"/>
<value name="ASTC 10x10" value="0x6B"/>
<value name="ASTC 12x10" value="0x6C"/>
<value name="ASTC 12x12" value="0x6D"/>
asahi: Add format enums Split it up into the underlying parts. Now we can decode every format accessible in Metal. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11086>
2021-05-31 14:37:06 -04:00
<value name="BC1" value="0x74"/>
<value name="BC2" value="0x75"/>
<value name="BC3" value="0x76"/>
<value name="BC4" value="0x77"/>
<value name="BC5" value="0x78"/>
<value name="BC6H" value="0x79"/>
<value name="BC6H Ufloat" value="0x7A"/>
<value name="BC7" value="0x7B"/>
</enum>
<enum name="Texture Type">
<value name="Unorm" value="0"/>
<value name="Snorm" value="1"/>
<value name="Uint" value="2"/>
<value name="Sint" value="3"/>
<value name="Float" value="4"/>
<value name="XR" value="5"/>
</enum>
asahi: Fix varying XML Lots of changes from reverse-engineering harder the interactions with fp16 and noperspective and such, and comparing against the PowerVR driver code in Mesa that's been released since this XML was originally written. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-06-19 18:10:09 -04:00
<struct name="CF binding header" size="4">
<field name="Number of 32-bit slots" size="8" start="0:0" type="uint"/>
<field name="Number of coefficient registers" size="8" start="0:8" type="uint"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
</struct>
asahi: Fix varying XML Lots of changes from reverse-engineering harder the interactions with fp16 and noperspective and such, and comparing against the PowerVR driver code in Mesa that's been released since this XML was originally written. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-06-19 18:10:09 -04:00
<enum name="Shade model">
<value name="Flat vertex 0" value="0"/>
<value name="Flat vertex 2" value="2"/>
<value name="Gouraud" value="3"/>
asahi: Identify varying descriptor fields Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11718>
2021-06-06 13:22:50 -04:00
</enum>
asahi: Fix varying XML Lots of changes from reverse-engineering harder the interactions with fp16 and noperspective and such, and comparing against the PowerVR driver code in Mesa that's been released since this XML was originally written. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-06-19 18:10:09 -04:00
<struct name="CF binding" size="4">
asahi: Identify varying descriptor fields Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11718>
2021-06-06 13:22:50 -04:00
<field name="Components" size="2" start="0" type="uint" modifier="minus(1)"/>
asahi: Fix varying XML Lots of changes from reverse-engineering harder the interactions with fp16 and noperspective and such, and comparing against the PowerVR driver code in Mesa that's been released since this XML was originally written. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-06-19 18:10:09 -04:00
<field name="Shade model" size="2" start="2" type="Shade model"/>
<field name="Perspective" size="1" start="4" type="bool"/>
<field name="Fragcoord Z" size="1" start="5" type="bool"/>
<field name="Point sprite" size="1" start="6" type="bool"/>
<field name="Base slot" size="8" start="8" type="uint"/>
<field name="Base coefficient register" size="8" start="16" type="uint"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
</struct>
asahi: Identify Dimension for Render Target Metal uses when rendering to multisampled 2D. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-10-23 12:20:52 -04:00
<enum name="Texture dimension">
<value name="1D" value="0"/>
<value name="1D Array" value="1"/>
<value name="2D" value="2"/>
<value name="2D Array" value="3"/>
<value name="2D Multisampled" value="4"/>
<value name="3D" value="5"/>
<value name="Cube" value="6"/>
<value name="Cube Array" value="7"/>
<value name="2D Array Multisampled" value="8"/>
</enum>
asahi: Identify PBE sample count Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-10-23 12:28:48 -04:00
<enum name="Sample Count">
<value name="2" value="0"/>
<value name="4" value="1"/>
</enum>
asahi: Dump all textures&samplers This confirms the actual size of the texture descriptor -- 24 bytes. The last 8 bytes have so far only been zeroed. It also confirms we got the sampler descriptor size right. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-05-22 23:02:29 -04:00
<struct name="Render Target" size="24">
asahi: Identify Dimension for Render Target Metal uses when rendering to multisampled 2D. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-10-23 12:20:52 -04:00
<field name="Dimension" size="4" start="0" type="Texture dimension" default="2D"/>
asahi: Add format enums Split it up into the underlying parts. Now we can decode every format accessible in Metal. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11086>
2021-05-31 14:37:06 -04:00
<field name="Layout" size="2" start="4" type="Layout"/>
asahi: Eliminate "Pixel Format" type from GenXML This is leaky and hurts compatibility with upstream GenXML. Just use the actual hardware fields. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>
2022-09-30 21:03:02 -04:00
<field name="Channels" size="7" start="6" type="Channels"/>
<field name="Type" size="3" start="13" type="Texture Type"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
<field name="Swizzle R" size="2" start="16" type="Channel"/>
<field name="Swizzle G" size="2" start="18" type="Channel"/>
<field name="Swizzle B" size="2" start="20" type="Channel"/>
<field name="Swizzle A" size="2" start="22" type="Channel"/>
<field name="Width" size="14" start="24" type="uint" modifier="minus(1)"/>
<field name="Height" size="14" start="38" type="uint" modifier="minus(1)"/>
<field name="Unk 52" size="1" start="52" type="bool"/>
<field name="Rotate 90" size="1" start="53" type="bool" default="false"/>
<field name="Flip vertical" size="1" start="54" type="bool" default="false"/>
asahi: Identify PBE sample count Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-10-23 12:28:48 -04:00
<field name="Samples" size="1" start="56" type="Sample Count"/>
<field name="Unk mipmapped" size="1" start="58" type="bool"/>
asahi: Identify compression-related XML Signed-off-by: Asahi Lina <lina@asahilina.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19999>
2022-11-23 22:21:18 +09:00
<field name="Compressed 1" size="1" start="59" type="bool"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
<field name="Buffer" size="36" start="64" type="address" modifier="shr(4)"/>
asahi: Note that "render target" lacks an sRGB bit sRGB is handled through other mechanisms. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11086>
2021-05-31 04:09:51 +05:30
<!-- N.b. sRGB is not specified here -->
asahi: Identify Level field of render target descriptor Hardware support for rendering into nonzero mip levels. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903>
2022-02-06 09:30:26 -05:00
<field name="Level" size="4" start="100" type="uint"/>
asahi: Fix "stride" for tiled textures It doesn't exist, but there's a count of mip levels for writeable image descs. Setting that appropriately matters at high mip levels. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-02 23:19:54 -04:00
asahi: Add XML for layered rendering We don't need to support this for a while but it's good to know the mechanism. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
2022-11-18 22:46:55 -05:00
<!-- If layout is not linear. Layers must be zero unless rendering to an
array texture (with a layered framebuffer) -->
<field name="Levels" size="4" start="104" type="uint" modifier="minus(1)"/>
<field name="Layers" size="14" start="108" type="uint" modifier="minus(1)" default="1"/>
asahi: Pass through layer alignment flag to the hardware Signed-off-by: Asahi Lina <lina@asahilina.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20031>
2022-11-28 17:29:45 +09:00
<field name="Page-aligned layers" size="1" start="124" type="bool"/>
asahi: Identify compression-related XML Signed-off-by: Asahi Lina <lina@asahilina.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19999>
2022-11-23 22:21:18 +09:00
<field name="Compressed 2" size="1" start="127" type="bool"/>
asahi: Fix "stride" for tiled textures It doesn't exist, but there's a count of mip levels for writeable image descs. Setting that appropriately matters at high mip levels. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-02 23:19:54 -04:00
<!-- If layout is linear. Off by 4? -->
<field name="Stride" size="24" start="104" type="hex"/>
asahi: Identify compressed render target fields We won't be implementing AGX compression for a while, but this gets some unknowns out of the way when looking at dumps from Metal that use it. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>
2022-06-12 11:08:07 -04:00
<!-- If layout is compressed -->
asahi: Identify compression-related XML Signed-off-by: Asahi Lina <lina@asahilina.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19999>
2022-11-23 22:21:18 +09:00
<field name="Acceleration buffer" size="64" start="128" type="address" modifier="shr(4)"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
</struct>
asahi: Dump all textures&samplers This confirms the actual size of the texture descriptor -- 24 bytes. The last 8 bytes have so far only been zeroed. It also confirms we got the sampler descriptor size right. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-05-22 23:02:29 -04:00
<struct name="Texture" size="24">
agx: Make empty texture pack to all-zeroes So we can do partial textures. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20013>
2022-11-23 21:33:46 -05:00
<field name="Dimension" size="4" start="0" type="Texture dimension"/>
asahi: Add format enums Split it up into the underlying parts. Now we can decode every format accessible in Metal. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11086>
2021-05-31 14:37:06 -04:00
<field name="Layout" size="2" start="4" type="Layout"/>
asahi: Eliminate "Pixel Format" type from GenXML This is leaky and hurts compatibility with upstream GenXML. Just use the actual hardware fields. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>
2022-09-30 21:03:02 -04:00
<field name="Channels" size="7" start="6" type="Channels"/>
<field name="Type" size="3" start="13" type="Texture Type"/>
agx: Make empty texture pack to all-zeroes So we can do partial textures. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20013>
2022-11-23 21:33:46 -05:00
<field name="Swizzle R" size="3" start="16" type="Channel"/>
<field name="Swizzle G" size="3" start="19" type="Channel"/>
<field name="Swizzle B" size="3" start="22" type="Channel"/>
<field name="Swizzle A" size="3" start="25" type="Channel"/>
<field name="Width" size="14" start="28" type="uint" modifier="minus(1)" default="1"/>
<field name="Height" size="14" start="42" type="uint" modifier="minus(1)" default="1"/>
asahi: Identify and use first level field of texture As we recently discovered, the layout of level L of a mipmapped 2D image of size WxH is /not/ the same as the layout of a non-mipmapped 2D image of size minify(W, L) x minify(H, L). The difference occurs due to subtleties of the "power of two" miptrees which can force a level to use a larger tile size than it would have required at root level. To handle this quirk correctly, the driver must not implement texture views with address arithmetic -- it must supply instead the base width/height of a texture and use first/last level fields on the texture descriptor to map it. Similar issues occur when writing a particular level of a mipmapped texture, which was handled correctly in the colour case but not the Z/S case. Fixes dEQP-GLES2.functional.texture.mipmap.cube.generate.* Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18380>
2022-09-03 11:53:46 -04:00
<field name="First level" size="4" start="56" type="uint"/>
<field name="Last level" size="4" start="60" type="uint"/>
asahi: Add XML for multisampled textures Metal supports MSAA 2x and MSAA 4x, neither at the same time as mipmapping. That matches the GL spec requirement. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>
2022-08-20 21:15:07 -04:00
<field name="Samples" size="1" start="64" type="Sample Count"/>
asahi: Identify texture address field Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
2021-07-24 13:55:05 -04:00
<field name="Address" size="36" start="66" type="hex" modifier="shr(4)"/>
asahi: Add mipmapping state to the XML Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11086>
2021-05-31 20:08:37 -04:00
<!-- Unknown bit set by Metal when mipmapping. Might relate to a mechanism
to switch tile size (or disable tiling altogether?) at small mip levels to
reduce wasted memory due to padding. Causing test flakiness when set. -->
<field name="Unk mipmapped" size="1" start="102" type="bool"/>
asahi: Identify compression-related XML Signed-off-by: Asahi Lina <lina@asahilina.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19999>
2022-11-23 22:21:18 +09:00
<field name="Compressed 1" size="1" start="103" type="bool"/>
asahi: Fix using multiple textures/samplers The counts for textures/samplers are specified in the bind texture/sampler packets. What's in the bind pipeline appear to be... hints? of some kind? It's a direct function of the numbers of textures and samplers, but much more coarse. Unknown purpose. This should be correct for up to 48 textures and at least 8 samplers. For more than 48 textures, Metal switches to a "bindless" mode, where the textures are instead bound with a bind uniform packet, ts* is no longer read in the shader, and instead registers and immediates are used to index the texture with a substantial preshader. Details TBD. We don't need to worry about that for a long while, though. Fixes a number of dEQPs. dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.array_in_struct.sampler2D_samplerCube_both,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.array_in_struct.sampler2D_samplerCube_fragment,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.array_in_struct.sampler2D_samplerCube_vertex,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.nested_structs_arrays.sampler2D_samplerCube_both,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.nested_structs_arrays.sampler2D_samplerCube_fragment,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.nested_structs_arrays.sampler2D_samplerCube_vertex,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.array_in_struct.sampler2D_samplerCube_both,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.array_in_struct.sampler2D_samplerCube_fragment,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.array_in_struct.sampler2D_samplerCube_vertex,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.nested_structs_arrays.sampler2D_samplerCube_both,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.nested_structs_arrays.sampler2D_samplerCube_fragment,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.nested_structs_arrays.sampler2D_samplerCube_vertex,Crash Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-01-18 21:54:22 -05:00
<!-- This is set when no texture is bound, with layout 1 -->
<field name="Null" size="1" start="105" type="bool"/>
asahi: Rename 'tiled 64x64' to 'twiddled' To account for non-64x64 tile sizes, as well as the other forms of tiling that may come up with compression. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>
2022-08-20 13:10:49 -04:00
<field name="Compression" size="2" start="106" type="hex"/> <!-- 0 for uncompressed -->
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
<field name="sRGB" size="1" start="108" type="bool"/>
asahi: Handle 2-channel sRGB textures I'm not sure why we need to set this magic bit, but this fixes the non-depth_component portion of dEQP-GLES3.functional.texture.format.sized.*, e.g dEQP-GLES3.functional.texture.format.sized.cube.srgb_rg8_pot Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>
2022-08-18 22:22:21 -04:00
<field name="sRGB 2-channel" size="1" start="109" type="bool"/>
asahi: Identify line stride in texture/RT XML The off-by-four is concerning. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11086>
2021-05-31 03:31:43 +05:30
<field name="Stride" size="18" start="110" type="hex" modifier="shr(4)"/>
asahi: Support 2D array and 3D textures As far as I can tell, these *must* be tiled. Other than that, the implementation is completely routine. Passes dEQP-GLES3.functional.texture.format.unsized.*2d_array* Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903>
2022-01-18 14:16:12 -05:00
<!-- Note that 3D/arrays cannot be linear. -->
<field name="Depth" size="14" start="110" type="uint" modifier="minus(1)" default="1"/>
asahi: Pass through layer alignment flag to the hardware Signed-off-by: Asahi Lina <lina@asahilina.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20031>
2022-11-28 17:29:45 +09:00
<field name="Page-aligned layers" size="1" start="126" type="bool"/>
asahi: Identify compression-related XML Signed-off-by: Asahi Lina <lina@asahilina.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19999>
2022-11-23 22:21:18 +09:00
<field name="Compressed 2" size="1" start="127" type="bool"/>
<!-- If layout is compressed -->
<field name="Acceleration buffer" size="64" start="128" type="address" modifier="shr(4)"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
</struct>
<enum name="Wrap">
<value name="Clamp to edge" value="0"/>
<value name="Repeat" value="1"/>
<value name="Mirrored repeat" value="2"/>
<value name="Clamp to border" value="3"/>
</enum>
<enum name="Mip filter">
<value name="None" value="0"/>
<value name="Nearest" value="1"/>
<value name="Linear" value="2"/>
</enum>
<enum name="Border colour">
<value name="Transparent black" value="0"/>
<value name="Opaque black" value="1"/>
<value name="Opaque white" value="2"/>
</enum>
<struct name="Sampler" size="8">
asahi: Identify minimum/maximum LOD fields Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14903>
2022-02-06 15:04:45 -05:00
<field name="Minimum LOD" size="10" start="0" type="lod" default="0.0"/>
<field name="Maximum LOD" size="10" start="10" type="lod" default="INFINITY"/>
asahi: Identify XML for anisotropic filtering Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20123>
2022-11-23 15:24:05 -05:00
<field name="Maximum anisotropy" size="3" start="20" type="uint" default="1" modifier="log2"/>
asahi: Fix sampler filtering flag Typo in the XML. Fixes broken filtering. Still chasing an off-by-one. Fixes: cad54e2721d ("asahi: Add command buffer XML definitions") Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/12053>
2021-07-24 13:20:13 -04:00
<field name="Magnify linear" size="1" start="23" type="bool"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
<field name="Minify linear" size="1" start="25" type="bool"/>
<field name="Mip filter" size="2" start="27" type="Mip filter"/>
<field name="Wrap S" size="3" start="29" type="Wrap"/>
<field name="Wrap T" size="3" start="32" type="Wrap"/>
<field name="Wrap R" size="3" start="35" type="Wrap"/>
<field name="Pixel coordinates" size="1" start="38" type="bool"/>
<field name="Compare func" size="3" start="39" type="Compare func"/>
<field name="Unk 3" size="1" start="42" type="hex" default="1"/>
<field name="Border colour" size="2" start="55" type="Border colour"/>
</struct>
<!--- Pointed to from the command buffer -->
<struct name="Scissor" size="16">
asahi: Fix scissor descriptor definition Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11084>
2021-05-27 22:29:02 -04:00
<field name="Max X" size="16" start="0:0" type="uint"/>
<field name="Min X" size="16" start="0:16" type="uint"/>
<field name="Max Y" size="16" start="1:0" type="uint"/>
<field name="Min Y" size="16" start="1:16" type="uint"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
<field name="Min Z" size="32" start="2:0" type="float"/>
<field name="Max Z" size="32" start="3:0" type="float"/>
</struct>
asahi: Add a depth bias structure This is simple and corresponds directly to the Metal inputs. However, the alignment is a bit tricky, so let's add formal XML for it. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-04-02 21:09:27 -04:00
<!-- Note: this structure is not padded. It really is 12 bytes -->
<struct name="Depth bias" size="12">
<field name="Depth bias" size="32" start="0:0" type="float"/>
<field name="Slope scale" size="32" start="1:0" type="float"/>
<field name="Clamp" size="32" start="2:0" type="float"/>
</struct>
asahi: Match PPP data structures with PowerVR Looking at PowerVR's PPP definitions in tree in Mesa (src/imagination/csbgen/), we find that AGX's "tagged" data structures are actually sequences of state items prefixed by a header specifying which state follows. Rather than hardcoding the sequences in which Apple's driver chooses to bundle state, we need the XML to be flexible enough to encode or decode any valid combination of state. That means reworking the XML. While doing so, we find a number of fields that are identical between RGX and AGX, and fix the names while at it (for example, the W Clamp floating point). Names are from the PowerVR code in Mesa where sensible. Once we've reworked the XML, we need to rework the decoder. Instead of reading tags and printing the combined state packets, the decoder now must unpack the header and print the individual state items specified by the header, with slightly more complicated bounds checking. Finally, state emission in the driver becomes much more flexible. To prove the flexibility actually works, we now emit all PPP state (except for viewport and scissor state) as a single PPP update. This works. After this we can move onto more interesting arrangements of state for lower driver overhead. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 15:17:22 -04:00
<!-- PPP state starts -->
<struct name="PPP Header" size="4">
<field name="Fragment control" size="1" start="0" type="bool"/>
<field name="Fragment control 2" size="1" start="1" type="bool"/>
<field name="Fragment front face" size="1" start="2" type="bool"/>
<field name="Fragment front face 2" size="1" start="3" type="bool"/>
<field name="Fragment front stencil" size="1" start="4" type="bool"/>
<field name="Fragment back face" size="1" start="5" type="bool"/>
<field name="Fragment back face 2" size="1" start="6" type="bool"/>
<field name="Fragment back stencil" size="1" start="7" type="bool"/>
<field name="Depth bias/scissor" size="1" start="8" type="bool"/>
<field name="Region clip" size="1" start="10" type="bool"/>
<field name="Viewport" size="1" start="11" type="bool"/>
<field name="W clamp" size="1" start="16" type="bool"/>
<field name="Output select" size="1" start="17" type="bool"/>
<field name="Varying word 0" size="1" start="18" type="bool"/>
<field name="Varying word 1" size="1" start="19" type="bool"/>
<field name="Cull" size="1" start="21" type="bool"/>
<field name="Cull 2" size="1" start="22" type="bool"/>
<field name="Fragment shader" size="1" start="23" type="bool"/>
<field name="Occlusion query" size="1" start="24" type="bool"/>
<field name="Occlusion query 2" size="1" start="25" type="bool"/>
<field name="Output unknown" size="1" start="26" type="bool"/>
<field name="Output size" size="1" start="27" type="bool"/>
<field name="Varying word 2" size="1" start="28" type="bool"/>
</struct>
<!-- Acts like a scissor at 32x32 tile boundaries, ignored unless clip tile is set -->
<struct name="Region clip" size="12">
<field name="Max X" size="9" start="0" type="uint" modifier="minus(1)"/>
<field name="Min X" size="9" start="16" type="uint"/>
<field name="Enable" size="1" start="31" type="bool"/>
<field name="Max Y" size="9" start="32" type="uint" modifier="minus(1)"/>
<field name="Min Y" size="9" start="48" type="uint"/>
</struct>
<!-- Used to convert clip space coordinates to NDC, does not clip -->
<struct name="Viewport" size="24">
<field name="Translate X" size="32" start="0:0" type="float"/>
<field name="Scale X" size="32" start="1:0" type="float"/>
<field name="Translate Y" size="32" start="2:0" type="float"/>
<field name="Scale Y" size="32" start="3:0" type="float"/>
<field name="Translate Z" size="32" start="4:0" type="float"/>
<field name="Scale Z" size="32" start="5:0" type="float"/>
</struct>
<struct name="Fragment face" size="4">
asahi: Split RASTERIZER into constituent words As done in the PowerVR driver. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 13:42:05 -04:00
<field name="Stencil reference" size="8" start="0" type="hex"/>
asahi: Implement wide lines Identify line width field and route through the Gallium line width. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11086>
2021-05-30 22:48:37 +05:30
<!-- line width is 4:4 fixed point with off-by-one applied -->
asahi: Split RASTERIZER into constituent words As done in the PowerVR driver. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 13:42:05 -04:00
<field name="Line width" size="8" start="8" type="hex"/>
<field name="Polygon mode" size="2" start="18" type="Polygon Mode"/>
<field name="Disable depth write" size="1" start="21" type="bool"/>
<field name="Unk - visibility test internal" size="2" start="22" type="hex"/>
<field name="Depth function" size="3" start="24" type="ZS Func"/>
</struct>
asahi: Identify more depth-related fields in XML Needed for gl_FragDepth writes. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
2022-11-18 22:47:28 -05:00
<enum name="Conservative depth">
<value name="Any" value="0"/>
<value name="Greater" value="1"/>
<value name="Less" value="2"/>
<value name="Unchanged" value="3"/>
</enum>
asahi: Match PPP data structures with PowerVR Looking at PowerVR's PPP definitions in tree in Mesa (src/imagination/csbgen/), we find that AGX's "tagged" data structures are actually sequences of state items prefixed by a header specifying which state follows. Rather than hardcoding the sequences in which Apple's driver chooses to bundle state, we need the XML to be flexible enough to encode or decode any valid combination of state. That means reworking the XML. While doing so, we find a number of fields that are identical between RGX and AGX, and fix the names while at it (for example, the W Clamp floating point). Names are from the PowerVR code in Mesa where sensible. Once we've reworked the XML, we need to rework the decoder. Instead of reading tags and printing the combined state packets, the decoder now must unpack the header and print the individual state items specified by the header, with slightly more complicated bounds checking. Finally, state emission in the driver becomes much more flexible. To prove the flexibility actually works, we now emit all PPP state (except for viewport and scissor state) as a single PPP update. This works. After this we can move onto more interesting arrangements of state for lower driver overhead. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 15:17:22 -04:00
<struct name="Fragment face 2" size="4">
asahi: Identify more depth-related fields in XML Needed for gl_FragDepth writes. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
2022-11-18 22:47:28 -05:00
<!-- If either disable is zeroed, depth is written -->
<field name="Disable depth write" size="1" start="21" type="bool" default="true"/>
<!-- If depth written from FS -->
<field name="Conservative depth" size="2" start="22" type="Conservative depth" default="Unchanged"/>
<!-- Both depth functions must pass -->
<field name="Depth function" size="3" start="24" type="ZS Func" default="Always"/>
asahi: Match PPP data structures with PowerVR Looking at PowerVR's PPP definitions in tree in Mesa (src/imagination/csbgen/), we find that AGX's "tagged" data structures are actually sequences of state items prefixed by a header specifying which state follows. Rather than hardcoding the sequences in which Apple's driver chooses to bundle state, we need the XML to be flexible enough to encode or decode any valid combination of state. That means reworking the XML. While doing so, we find a number of fields that are identical between RGX and AGX, and fix the names while at it (for example, the W Clamp floating point). Names are from the PowerVR code in Mesa where sensible. Once we've reworked the XML, we need to rework the decoder. Instead of reading tags and printing the combined state packets, the decoder now must unpack the header and print the individual state items specified by the header, with slightly more complicated bounds checking. Finally, state emission in the driver becomes much more flexible. To prove the flexibility actually works, we now emit all PPP state (except for viewport and scissor state) as a single PPP update. This works. After this we can move onto more interesting arrangements of state for lower driver overhead. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 15:17:22 -04:00
<field name="Object type" size="4" start="28" type="Object Type"/>
</struct>
<struct name="Fragment stencil" size="4">
asahi: Split RASTERIZER into constituent words As done in the PowerVR driver. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 13:42:05 -04:00
<field name="Write mask" size="8" start="0" type="hex"/>
<field name="Read mask" size="8" start="8" type="hex"/>
<field name="Depth pass" size="3" start="16" type="Stencil Op"/>
<field name="Depth fail" size="3" start="19" type="Stencil Op"/>
<field name="Stencil fail" size="3" start="22" type="Stencil Op"/>
<field name="Compare" size="3" start="25" type="ZS Func"/>
</struct>
asahi: Match PPP data structures with PowerVR Looking at PowerVR's PPP definitions in tree in Mesa (src/imagination/csbgen/), we find that AGX's "tagged" data structures are actually sequences of state items prefixed by a header specifying which state follows. Rather than hardcoding the sequences in which Apple's driver chooses to bundle state, we need the XML to be flexible enough to encode or decode any valid combination of state. That means reworking the XML. While doing so, we find a number of fields that are identical between RGX and AGX, and fix the names while at it (for example, the W Clamp floating point). Names are from the PowerVR code in Mesa where sensible. Once we've reworked the XML, we need to rework the decoder. Instead of reading tags and printing the combined state packets, the decoder now must unpack the header and print the individual state items specified by the header, with slightly more complicated bounds checking. Finally, state emission in the driver becomes much more flexible. To prove the flexibility actually works, we now emit all PPP state (except for viewport and scissor state) as a single PPP update. This works. After this we can move onto more interesting arrangements of state for lower driver overhead. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 15:17:22 -04:00
<struct name="Fragment control" size="4">
asahi: Split RASTERIZER into constituent words As done in the PowerVR driver. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 13:42:05 -04:00
<field name="Unk 1" size="1" start="9" type="hex" default="0x1"/>
<field name="Visibility mode" size="2" start="14" type="Visibility Mode"/>
<field name="Scissor enable" size="1" start="16" type="bool"/>
<field name="Depth bias enable" size="1" start="17" type="bool"/>
<field name="Stencil test enable" size="1" start="18" type="bool"/>
<field name="Two-sided stencil" size="1" start="19" type="bool"/>
<field name="Unk fill lines" size="1" start="26" type="hex" default="0x0"/> <!-- set when drawing LINES -->
</struct>
asahi: Identify the pass type enum Via PowerVR. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-10-23 13:43:25 -04:00
<enum name="Pass type">
<value name="Opaque" value="0"/>
<value name="Translucent" value="1"/>
<value name="Punch through" value="2"/>
<value name="Translucent punch through" value="3"/>
<!-- See PASSTYPE in rogue_ppp.xml if more values are observed on AGX...
Translucent punch through seems notably different though? -->
</enum>
asahi: Match PPP data structures with PowerVR Looking at PowerVR's PPP definitions in tree in Mesa (src/imagination/csbgen/), we find that AGX's "tagged" data structures are actually sequences of state items prefixed by a header specifying which state follows. Rather than hardcoding the sequences in which Apple's driver chooses to bundle state, we need the XML to be flexible enough to encode or decode any valid combination of state. That means reworking the XML. While doing so, we find a number of fields that are identical between RGX and AGX, and fix the names while at it (for example, the W Clamp floating point). Names are from the PowerVR code in Mesa where sensible. Once we've reworked the XML, we need to rework the decoder. Instead of reading tags and printing the combined state packets, the decoder now must unpack the header and print the individual state items specified by the header, with slightly more complicated bounds checking. Finally, state emission in the driver becomes much more flexible. To prove the flexibility actually works, we now emit all PPP state (except for viewport and scissor state) as a single PPP update. This works. After this we can move onto more interesting arrangements of state for lower driver overhead. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 15:17:22 -04:00
<struct name="Fragment control 2" size="4">
<field name="Unk 1" size="1" start="9" type="bool" default="true"/>
<!-- Or discards? -->
<field name="No colour output" size="1" start="21" type="bool"/>
asahi: Identify "Sample mask after depth/stencil" bit Corresponds to Metal [[sample_mask,post_depth_coverage]]. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-10-23 16:50:00 -04:00
<field name="Sample mask after depth/stencil" size="1" start="25" type="bool"/>
asahi: Match PPP data structures with PowerVR Looking at PowerVR's PPP definitions in tree in Mesa (src/imagination/csbgen/), we find that AGX's "tagged" data structures are actually sequences of state items prefixed by a header specifying which state follows. Rather than hardcoding the sequences in which Apple's driver chooses to bundle state, we need the XML to be flexible enough to encode or decode any valid combination of state. That means reworking the XML. While doing so, we find a number of fields that are identical between RGX and AGX, and fix the names while at it (for example, the W Clamp floating point). Names are from the PowerVR code in Mesa where sensible. Once we've reworked the XML, we need to rework the decoder. Instead of reading tags and printing the combined state packets, the decoder now must unpack the header and print the individual state items specified by the header, with slightly more complicated bounds checking. Finally, state emission in the driver becomes much more flexible. To prove the flexibility actually works, we now emit all PPP state (except for viewport and scissor state) as a single PPP update. This works. After this we can move onto more interesting arrangements of state for lower driver overhead. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 15:17:22 -04:00
<field name="Lines or points" size="1" start="26" type="bool"/>
asahi: Identify the pass type enum Via PowerVR. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-10-23 13:43:25 -04:00
<field name="Pass type" size="3" start="29" type="Pass type"/>
asahi: Match PPP data structures with PowerVR Looking at PowerVR's PPP definitions in tree in Mesa (src/imagination/csbgen/), we find that AGX's "tagged" data structures are actually sequences of state items prefixed by a header specifying which state follows. Rather than hardcoding the sequences in which Apple's driver chooses to bundle state, we need the XML to be flexible enough to encode or decode any valid combination of state. That means reworking the XML. While doing so, we find a number of fields that are identical between RGX and AGX, and fix the names while at it (for example, the W Clamp floating point). Names are from the PowerVR code in Mesa where sensible. Once we've reworked the XML, we need to rework the decoder. Instead of reading tags and printing the combined state packets, the decoder now must unpack the header and print the individual state items specified by the header, with slightly more complicated bounds checking. Finally, state emission in the driver becomes much more flexible. To prove the flexibility actually works, we now emit all PPP state (except for viewport and scissor state) as a single PPP update. This works. After this we can move onto more interesting arrangements of state for lower driver overhead. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 15:17:22 -04:00
</struct>
<struct name="Fragment occlusion query" size="4">
asahi: Split RASTERIZER into constituent words As done in the PowerVR driver. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 13:42:05 -04:00
<field name="Offset" size="18" start="14" type="uint"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
</struct>
asahi: Match PPP data structures with PowerVR Looking at PowerVR's PPP definitions in tree in Mesa (src/imagination/csbgen/), we find that AGX's "tagged" data structures are actually sequences of state items prefixed by a header specifying which state follows. Rather than hardcoding the sequences in which Apple's driver chooses to bundle state, we need the XML to be flexible enough to encode or decode any valid combination of state. That means reworking the XML. While doing so, we find a number of fields that are identical between RGX and AGX, and fix the names while at it (for example, the W Clamp floating point). Names are from the PowerVR code in Mesa where sensible. Once we've reworked the XML, we need to rework the decoder. Instead of reading tags and printing the combined state packets, the decoder now must unpack the header and print the individual state items specified by the header, with slightly more complicated bounds checking. Finally, state emission in the driver becomes much more flexible. To prove the flexibility actually works, we now emit all PPP state (except for viewport and scissor state) as a single PPP update. This works. After this we can move onto more interesting arrangements of state for lower driver overhead. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 15:17:22 -04:00
<struct name="Fragment occlusion query 2" size="4">
<field name="Unknown" size="17" start="0" type="hex"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
</struct>
asahi: Match PPP data structures with PowerVR Looking at PowerVR's PPP definitions in tree in Mesa (src/imagination/csbgen/), we find that AGX's "tagged" data structures are actually sequences of state items prefixed by a header specifying which state follows. Rather than hardcoding the sequences in which Apple's driver chooses to bundle state, we need the XML to be flexible enough to encode or decode any valid combination of state. That means reworking the XML. While doing so, we find a number of fields that are identical between RGX and AGX, and fix the names while at it (for example, the W Clamp floating point). Names are from the PowerVR code in Mesa where sensible. Once we've reworked the XML, we need to rework the decoder. Instead of reading tags and printing the combined state packets, the decoder now must unpack the header and print the individual state items specified by the header, with slightly more complicated bounds checking. Finally, state emission in the driver becomes much more flexible. To prove the flexibility actually works, we now emit all PPP state (except for viewport and scissor state) as a single PPP update. This works. After this we can move onto more interesting arrangements of state for lower driver overhead. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 15:17:22 -04:00
<struct name="W Clamp" size="4">
<field name="W Clamp" size="32" start="0" type="float"/>
asahi: Add XML for unknown 0x4a packet Enough bits of this packet are known that open-coding hex bytes for it is annoying. Add some XML correpsonding to what we know. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14219>
2021-12-15 21:15:55 -05:00
</struct>
asahi: Match PPP data structures with PowerVR Looking at PowerVR's PPP definitions in tree in Mesa (src/imagination/csbgen/), we find that AGX's "tagged" data structures are actually sequences of state items prefixed by a header specifying which state follows. Rather than hardcoding the sequences in which Apple's driver chooses to bundle state, we need the XML to be flexible enough to encode or decode any valid combination of state. That means reworking the XML. While doing so, we find a number of fields that are identical between RGX and AGX, and fix the names while at it (for example, the W Clamp floating point). Names are from the PowerVR code in Mesa where sensible. Once we've reworked the XML, we need to rework the decoder. Instead of reading tags and printing the combined state packets, the decoder now must unpack the header and print the individual state items specified by the header, with slightly more complicated bounds checking. Finally, state emission in the driver becomes much more flexible. To prove the flexibility actually works, we now emit all PPP state (except for viewport and scissor state) as a single PPP update. This works. After this we can move onto more interesting arrangements of state for lower driver overhead. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 15:17:22 -04:00
<struct name="Cull" size="4">
<field name="Cull front" size="1" start="0" type="bool"/>
<field name="Cull back" size="1" start="1" type="bool"/>
<field name="Unk GL 1" size="1" start="7" type="bool"/>
<field name="Unk GL 2" size="1" start="8" type="bool"/>
<field name="Depth clip" size="1" start="10" type="bool"/>
<field name="Depth clamp" size="1" start="11" type="bool"/>
<field name="Front face CCW" size="1" start="16" type="bool"/>
</struct>
<struct name="Cull 2" size="4">
<field name="Unknown 2" size="32" start="0" type="hex" default="0xa0"/>
asahi: Add more XML via PowerVR These bits are the same as RGX. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
2022-11-18 22:48:20 -05:00
<field name="Draw clipped edges" size="1" start="9" type="bool"/>
<field name="Primitive MSAA" size="1" start="15" type="bool"/>
asahi: Match PPP data structures with PowerVR Looking at PowerVR's PPP definitions in tree in Mesa (src/imagination/csbgen/), we find that AGX's "tagged" data structures are actually sequences of state items prefixed by a header specifying which state follows. Rather than hardcoding the sequences in which Apple's driver chooses to bundle state, we need the XML to be flexible enough to encode or decode any valid combination of state. That means reworking the XML. While doing so, we find a number of fields that are identical between RGX and AGX, and fix the names while at it (for example, the W Clamp floating point). Names are from the PowerVR code in Mesa where sensible. Once we've reworked the XML, we need to rework the decoder. Instead of reading tags and printing the combined state packets, the decoder now must unpack the header and print the individual state items specified by the header, with slightly more complicated bounds checking. Finally, state emission in the driver becomes much more flexible. To prove the flexibility actually works, we now emit all PPP state (except for viewport and scissor state) as a single PPP update. This works. After this we can move onto more interesting arrangements of state for lower driver overhead. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 15:17:22 -04:00
</struct>
<struct name="Varying 0" size="4">
asahi: Add note to XML about 16-bit varyings Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
2022-11-18 22:47:52 -05:00
<!-- TODO: 16-bit is separate AFAIU -->
asahi: Match PPP data structures with PowerVR Looking at PowerVR's PPP definitions in tree in Mesa (src/imagination/csbgen/), we find that AGX's "tagged" data structures are actually sequences of state items prefixed by a header specifying which state follows. Rather than hardcoding the sequences in which Apple's driver chooses to bundle state, we need the XML to be flexible enough to encode or decode any valid combination of state. That means reworking the XML. While doing so, we find a number of fields that are identical between RGX and AGX, and fix the names while at it (for example, the W Clamp floating point). Names are from the PowerVR code in Mesa where sensible. Once we've reworked the XML, we need to rework the decoder. Instead of reading tags and printing the combined state packets, the decoder now must unpack the header and print the individual state items specified by the header, with slightly more complicated bounds checking. Finally, state emission in the driver becomes much more flexible. To prove the flexibility actually works, we now emit all PPP state (except for viewport and scissor state) as a single PPP update. This works. After this we can move onto more interesting arrangements of state for lower driver overhead. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 15:17:22 -04:00
<field name="Count" size="32" start="0" type="uint"/>
</struct>
<struct name="Varying 1" size="4">
<!-- TODO -->
asahi: Add XML for unknown 0x4a packet Enough bits of this packet are known that open-coding hex bytes for it is annoying. Add some XML correpsonding to what we know. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14219>
2021-12-15 21:15:55 -05:00
</struct>
asahi: Match PPP data structures with PowerVR Looking at PowerVR's PPP definitions in tree in Mesa (src/imagination/csbgen/), we find that AGX's "tagged" data structures are actually sequences of state items prefixed by a header specifying which state follows. Rather than hardcoding the sequences in which Apple's driver chooses to bundle state, we need the XML to be flexible enough to encode or decode any valid combination of state. That means reworking the XML. While doing so, we find a number of fields that are identical between RGX and AGX, and fix the names while at it (for example, the W Clamp floating point). Names are from the PowerVR code in Mesa where sensible. Once we've reworked the XML, we need to rework the decoder. Instead of reading tags and printing the combined state packets, the decoder now must unpack the header and print the individual state items specified by the header, with slightly more complicated bounds checking. Finally, state emission in the driver becomes much more flexible. To prove the flexibility actually works, we now emit all PPP state (except for viewport and scissor state) as a single PPP update. This works. After this we can move onto more interesting arrangements of state for lower driver overhead. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 15:17:22 -04:00
<struct name="Varying 2" size="8">
<!-- TODO -->
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
</struct>
asahi: Match PPP data structures with PowerVR Looking at PowerVR's PPP definitions in tree in Mesa (src/imagination/csbgen/), we find that AGX's "tagged" data structures are actually sequences of state items prefixed by a header specifying which state follows. Rather than hardcoding the sequences in which Apple's driver chooses to bundle state, we need the XML to be flexible enough to encode or decode any valid combination of state. That means reworking the XML. While doing so, we find a number of fields that are identical between RGX and AGX, and fix the names while at it (for example, the W Clamp floating point). Names are from the PowerVR code in Mesa where sensible. Once we've reworked the XML, we need to rework the decoder. Instead of reading tags and printing the combined state packets, the decoder now must unpack the header and print the individual state items specified by the header, with slightly more complicated bounds checking. Finally, state emission in the driver becomes much more flexible. To prove the flexibility actually works, we now emit all PPP state (except for viewport and scissor state) as a single PPP update. This works. After this we can move onto more interesting arrangements of state for lower driver overhead. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 15:17:22 -04:00
<struct name="Output Select" size="4">
asahi: Add more XML via PowerVR These bits are the same as RGX. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
2022-11-18 22:48:20 -05:00
<field name="Clip distance plane 0" size="1" start="0" type="bool"/>
<field name="Clip distance plane 1" size="1" start="1" type="bool"/>
<field name="Clip distance plane 2" size="1" start="2" type="bool"/>
<field name="Clip distance plane 3" size="1" start="3" type="bool"/>
<field name="Clip distance plane 4" size="1" start="4" type="bool"/>
<field name="Clip distance plane 5" size="1" start="5" type="bool"/>
<field name="Clip distance plane 6" size="1" start="6" type="bool"/>
<field name="Clip distance plane 7" size="1" start="7" type="bool"/>
<field name="Clip distance plane 8" size="1" start="8" type="bool"/>
<field name="Clip distance plane 9" size="1" start="9" type="bool"/>
<field name="Clip distance plane 10" size="1" start="10" type="bool"/>
<field name="Clip distance plane 11" size="1" start="11" type="bool"/>
<field name="Clip distance plane 12" size="1" start="12" type="bool"/>
<field name="Clip distance plane 13" size="1" start="13" type="bool"/>
<field name="Clip distance plane 14" size="1" start="14" type="bool"/>
<field name="Clip distance plane 15" size="1" start="15" type="bool"/>
asahi: Match PPP data structures with PowerVR Looking at PowerVR's PPP definitions in tree in Mesa (src/imagination/csbgen/), we find that AGX's "tagged" data structures are actually sequences of state items prefixed by a header specifying which state follows. Rather than hardcoding the sequences in which Apple's driver chooses to bundle state, we need the XML to be flexible enough to encode or decode any valid combination of state. That means reworking the XML. While doing so, we find a number of fields that are identical between RGX and AGX, and fix the names while at it (for example, the W Clamp floating point). Names are from the PowerVR code in Mesa where sensible. Once we've reworked the XML, we need to rework the decoder. Instead of reading tags and printing the combined state packets, the decoder now must unpack the header and print the individual state items specified by the header, with slightly more complicated bounds checking. Finally, state emission in the driver becomes much more flexible. To prove the flexibility actually works, we now emit all PPP state (except for viewport and scissor state) as a single PPP update. This works. After this we can move onto more interesting arrangements of state for lower driver overhead. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 15:17:22 -04:00
<field name="Varyings" size="1" start="16" type="bool"/>
<field name="Point size" size="1" start="18" type="bool"/>
asahi: Add XML for layered rendering We don't need to support this for a while but it's good to know the mechanism. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
2022-11-18 22:46:55 -05:00
<!-- For layered rendering, enable both and write the 2x16-bit tuple from
the vertex shader (layer, (viewport << u) + (u & layer)). So far unclear
what u is supposed to be. If u=0, this simplifies to the expected (layer,
viewport) at least. -->
<field name="Viewport target" size="1" start="19" type="bool"/>
<field name="Render target" size="1" start="20" type="bool"/>
asahi: Match PPP data structures with PowerVR Looking at PowerVR's PPP definitions in tree in Mesa (src/imagination/csbgen/), we find that AGX's "tagged" data structures are actually sequences of state items prefixed by a header specifying which state follows. Rather than hardcoding the sequences in which Apple's driver chooses to bundle state, we need the XML to be flexible enough to encode or decode any valid combination of state. That means reworking the XML. While doing so, we find a number of fields that are identical between RGX and AGX, and fix the names while at it (for example, the W Clamp floating point). Names are from the PowerVR code in Mesa where sensible. Once we've reworked the XML, we need to rework the decoder. Instead of reading tags and printing the combined state packets, the decoder now must unpack the header and print the individual state items specified by the header, with slightly more complicated bounds checking. Finally, state emission in the driver becomes much more flexible. To prove the flexibility actually works, we now emit all PPP state (except for viewport and scissor state) as a single PPP update. This works. After this we can move onto more interesting arrangements of state for lower driver overhead. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 15:17:22 -04:00
<field name="Frag coord Z" size="1" start="21" type="bool"/>
asahi: Use XML for interpolation packet Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11730>
2021-07-05 23:17:33 -04:00
</struct>
asahi: Match PPP data structures with PowerVR Looking at PowerVR's PPP definitions in tree in Mesa (src/imagination/csbgen/), we find that AGX's "tagged" data structures are actually sequences of state items prefixed by a header specifying which state follows. Rather than hardcoding the sequences in which Apple's driver chooses to bundle state, we need the XML to be flexible enough to encode or decode any valid combination of state. That means reworking the XML. While doing so, we find a number of fields that are identical between RGX and AGX, and fix the names while at it (for example, the W Clamp floating point). Names are from the PowerVR code in Mesa where sensible. Once we've reworked the XML, we need to rework the decoder. Instead of reading tags and printing the combined state packets, the decoder now must unpack the header and print the individual state items specified by the header, with slightly more complicated bounds checking. Finally, state emission in the driver becomes much more flexible. To prove the flexibility actually works, we now emit all PPP state (except for viewport and scissor state) as a single PPP update. This works. After this we can move onto more interesting arrangements of state for lower driver overhead. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 15:17:22 -04:00
<struct name="Output Unknown" size="4">
<!-- So far always zero -->
</struct>
<struct name="Output Size" size="4">
<field name="Count" size="32" start="0" type="uint"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
</struct>
asahi: Identify "set depth bias index" field Grouped together with the "set scissor index" field, which is natural. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-04-02 15:17:52 -04:00
<!-- Indexes into the scissor and depth bias arrays -->
asahi: Match PPP data structures with PowerVR Looking at PowerVR's PPP definitions in tree in Mesa (src/imagination/csbgen/), we find that AGX's "tagged" data structures are actually sequences of state items prefixed by a header specifying which state follows. Rather than hardcoding the sequences in which Apple's driver chooses to bundle state, we need the XML to be flexible enough to encode or decode any valid combination of state. That means reworking the XML. While doing so, we find a number of fields that are identical between RGX and AGX, and fix the names while at it (for example, the W Clamp floating point). Names are from the PowerVR code in Mesa where sensible. Once we've reworked the XML, we need to rework the decoder. Instead of reading tags and printing the combined state packets, the decoder now must unpack the header and print the individual state items specified by the header, with slightly more complicated bounds checking. Finally, state emission in the driver becomes much more flexible. To prove the flexibility actually works, we now emit all PPP state (except for viewport and scissor state) as a single PPP update. This works. After this we can move onto more interesting arrangements of state for lower driver overhead. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 15:17:22 -04:00
<struct name="Depth bias/Scissor" size="4">
<field name="Scissor" size="16" start="0" type="uint"/>
<field name="Depth bias" size="16" start="16" type="uint"/>
</struct>
<struct name="Fragment shader" size="16">
asahi: Identify more shader-related fields The big discovery is the "number of uniform registers" field. I learned about this one accidentally when my preamble shaders weren't working right, because we had inadvertently hardcoded "at most 32 registers" :-) In the course of identifying that field, I found that the pipeline address is used as a tagged pointer, with some unknown field in the bottom bits and alignment demanded. The XML is updated to account for this. I later found that there's also a "number of general purpose registers used by the preamble shader" field. I missed this one first, because the encoding is slightly different from the usual "number of general purpose registers in the main shader" field. The specification is slightly coarser. I don't know why the hardware needs that information anyway -- occupancy of the preamble shader should be irrelevant -- but it's not a big deal. Finally I found that the "more than 4 textures?" bit is... not that. I do not yet know what it is, but it is... not that. These all use the new groups() modifier for GenXML Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
2022-10-13 23:08:11 -04:00
<field name="Unknown 0" size="1" start="0" type="hex" default="0"/>
<field name="Uniform register count" size="3" start="1" type="uint" modifier="groups(64)"/>
<field name="Texture state register count" size="5" start="4" type="uint" modifier="groups(8)"/>
<field name="Sampler state register count" size="3" start="9" type="uint" modifier="groups(4)"/>
<field name="Preshader register count" size="4" start="12" type="uint" modifier="groups(16)"/>
<field name="CF binding count" size="7" start="16" type="uint"/>
<field name="Unknown 1:0" size="2" start="1:0" type="hex"/>
<field name="Pipeline" size="26" start="1:6" type="address" modifier="shr(6)"/>
<field name="CF bindings" size="30" start="2:2" type="address" modifier="shr(2)"/>
<!-- Seems to be set to small values depending on textures? and pushed
uniforms? Needs investigation -->
<field name="Unknown 3:0" start="3:0" size="4" type="hex"/>
asahi: Add "set scissor" command Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11084>
2021-05-27 22:31:08 -04:00
</struct>
asahi: Match PPP data structures with PowerVR Looking at PowerVR's PPP definitions in tree in Mesa (src/imagination/csbgen/), we find that AGX's "tagged" data structures are actually sequences of state items prefixed by a header specifying which state follows. Rather than hardcoding the sequences in which Apple's driver chooses to bundle state, we need the XML to be flexible enough to encode or decode any valid combination of state. That means reworking the XML. While doing so, we find a number of fields that are identical between RGX and AGX, and fix the names while at it (for example, the W Clamp floating point). Names are from the PowerVR code in Mesa where sensible. Once we've reworked the XML, we need to rework the decoder. Instead of reading tags and printing the combined state packets, the decoder now must unpack the header and print the individual state items specified by the header, with slightly more complicated bounds checking. Finally, state emission in the driver becomes much more flexible. To prove the flexibility actually works, we now emit all PPP state (except for viewport and scissor state) as a single PPP update. This works. After this we can move onto more interesting arrangements of state for lower driver overhead. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-04 15:17:22 -04:00
<!-- PPP state ends -->
asahi: Consolidate magic numbers for USC controls Aka "pipeline" states. It's another command/control stream. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-15 17:15:44 -04:00
<!-- USC state starts -->
<enum name="USC Control">
asahi: Overhaul USC control packing Break up the monolithic SET_SHADER_EXTENDED packet into the separate underlying commands (some only 2-byte sized and aligned), and add a builder for USC control streams like we did for PPP updates to make that change manageable. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-17 11:22:01 -04:00
<value name="Preshader" value="0x38"/>
<value name="Fragment properties" value="0x58"/>
<value name="No preshader" value="0x88"/>
<value name="Shader" value="0x0d"/>
asahi: Consolidate magic numbers for USC controls Aka "pipeline" states. It's another command/control stream. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-15 17:15:44 -04:00
<value name="Uniform" value="0x1d"/>
asahi: Identify "Uniform high" USC word The start field in the Uniform USC word is only 8-bits, whereas 9-bits are required to address the entire uniform register file. This other word gets used for the high half, with start indexed from u128l in the natural way. Apparently spending the evening stuffing too many uniforms into Metal is paying off. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
2022-10-16 20:47:18 -04:00
<value name="Uniform high" value="0x3d"/>
asahi: Overhaul USC control packing Break up the monolithic SET_SHADER_EXTENDED packet into the separate underlying commands (some only 2-byte sized and aligned), and add a builder for USC control streams like we did for PPP updates to make that change manageable. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-17 11:22:01 -04:00
<value name="Shared" value="0x4d"/>
<value name="Registers" value="0x8d"/>
asahi: Consolidate magic numbers for USC controls Aka "pipeline" states. It's another command/control stream. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-15 17:15:44 -04:00
<value name="Sampler" value="0x9d"/>
<value name="Texture" value="0xdd"/>
</enum>
asahi: Overhaul USC control packing Break up the monolithic SET_SHADER_EXTENDED packet into the separate underlying commands (some only 2-byte sized and aligned), and add a builder for USC control streams like we did for PPP updates to make that change manageable. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-17 11:22:01 -04:00
<struct name="USC Uniform" size="8">
asahi: Consolidate magic numbers for USC controls Aka "pipeline" states. It's another command/control stream. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-15 17:15:44 -04:00
<field name="Tag" size="8" start="0:0" type="USC Control" default="Uniform"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
<field name="Start (halfs)" size="8" start="0:8" type="uint"/>
asahi: Identify "Uniform high" USC word The start field in the Uniform USC word is only 8-bits, whereas 9-bits are required to address the entire uniform register file. This other word gets used for the high half, with start indexed from u128l in the natural way. Apparently spending the evening stuffing too many uniforms into Metal is paying off. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
2022-10-16 20:47:18 -04:00
<!-- Exact split is unknown. -->
<field name="Size (halfs)" size="7" start="0:20" type="uint"/>
<field name="Buffer" size="36" start="0:27" type="address" modifier="shr(3)"/>
</struct>
<struct name="USC Uniform High" size="8">
<field name="Tag" size="8" start="0:0" type="USC Control" default="Uniform High"/>
<field name="Start (halfs)" size="8" start="0:8" type="uint"/>
asahi: Extend counts in BIND packets We can bind at least 16 textures. Fix the sizes in the XML so this can be decoded correctly. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-05-22 22:37:51 -04:00
<!-- Exact split is unknown. -->
asahi: Fix bind sizes Otherwise we get a nonsensical count of 129 in one Metal sample. Exact size still not known but this bounds somewhat. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>
2022-08-09 20:44:17 -04:00
<field name="Size (halfs)" size="7" start="0:20" type="uint"/>
<field name="Buffer" size="36" start="0:27" type="address" modifier="shr(3)"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
</struct>
asahi: Overhaul USC control packing Break up the monolithic SET_SHADER_EXTENDED packet into the separate underlying commands (some only 2-byte sized and aligned), and add a builder for USC control streams like we did for PPP updates to make that change manageable. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-17 11:22:01 -04:00
<struct name="USC Texture" size="8">
asahi: Consolidate magic numbers for USC controls Aka "pipeline" states. It's another command/control stream. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-15 17:15:44 -04:00
<field name="Tag" size="8" start="0:0" type="USC Control" default="Texture"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
<field name="Start" size="8" start="0:8" type="uint"/>
asahi: Fix bind sizes Otherwise we get a nonsensical count of 129 in one Metal sample. Exact size still not known but this bounds somewhat. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>
2022-08-09 20:44:17 -04:00
<!-- Exact split is unknown. Count is at least 5 bits. Less than 8 bits. -->
<field name="Count" size="7" start="0:20" type="uint"/>
<field name="Buffer" size="36" start="0:27" type="address" modifier="shr(3)"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
</struct>
asahi: Overhaul USC control packing Break up the monolithic SET_SHADER_EXTENDED packet into the separate underlying commands (some only 2-byte sized and aligned), and add a builder for USC control streams like we did for PPP updates to make that change manageable. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-17 11:22:01 -04:00
<struct name="USC Sampler" size="8">
asahi: Consolidate magic numbers for USC controls Aka "pipeline" states. It's another command/control stream. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-15 17:15:44 -04:00
<field name="Tag" size="8" start="0:0" type="USC Control" default="Sampler"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
<field name="Start" size="8" start="0:8" type="uint"/>
asahi: Fix bind sizes Otherwise we get a nonsensical count of 129 in one Metal sample. Exact size still not known but this bounds somewhat. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>
2022-08-09 20:44:17 -04:00
<field name="Count" size="7" start="0:20" type="uint"/>
asahi: Extend counts in BIND packets We can bind at least 16 textures. Fix the sizes in the XML so this can be decoded correctly. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-05-22 22:37:51 -04:00
<!-- Exact split is unknown. -->
asahi: Fix bind sizes Otherwise we get a nonsensical count of 129 in one Metal sample. Exact size still not known but this bounds somewhat. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18167>
2022-08-09 20:44:17 -04:00
<field name="Buffer" size="36" start="0:27" type="address" modifier="shr(3)"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
</struct>
asahi: Identify shared memory layouts Somehow maps to the tile size. Not sure about the details yet. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-17 17:14:17 -04:00
<enum name="Shared layout">
<value name="Vertex/compute" value="0x24"/>
<value name="32x32" value="0x2f"/>
<value name="32x16" value="0x3f"/>
<value name="16x16" value="0x36"/>
</enum>
asahi: Overhaul USC control packing Break up the monolithic SET_SHADER_EXTENDED packet into the separate underlying commands (some only 2-byte sized and aligned), and add a builder for USC control streams like we did for PPP updates to make that change manageable. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-17 11:22:01 -04:00
<struct name="USC Shared" size="4">
<field name="Tag" size="8" start="0" type="USC Control" default="Shared"/>
<field name="Uses shared memory" size="1" start="8" type="bool"/>
asahi: Identify multisampling fields of shared layout Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
2022-11-07 20:01:40 -05:00
<field name="Layout" size="6" start="10" type="Shared layout"/>
<field name="Sample count" size="2" start="16" type="uint" default="1" modifier="log2"/>
<field name="Sample stride in 8 bytes" size="4" start="20" type="uint"/>
<field name="Bytes per threadgroup" size="8" start="24" type="uint" modifier="groups(256)"/>
asahi: Overhaul USC control packing Break up the monolithic SET_SHADER_EXTENDED packet into the separate underlying commands (some only 2-byte sized and aligned), and add a builder for USC control streams like we did for PPP updates to make that change manageable. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-17 11:22:01 -04:00
</struct>
<struct name="USC Shader" size="6">
<field name="Tag" size="8" start="0" type="USC Control" default="Shader"/>
<field name="Loads varyings" size="1" start="8" type="bool"/>
asahi: Add some notes about unknowns to the XML Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
2022-10-23 17:44:11 -04:00
<!-- Seen set for pixel rate fragment shaders? -->
asahi: Overhaul USC control packing Break up the monolithic SET_SHADER_EXTENDED packet into the separate underlying commands (some only 2-byte sized and aligned), and add a builder for USC control streams like we did for PPP updates to make that change manageable. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-17 11:22:01 -04:00
<field name="Unk 1" size="1" start="9" type="bool" default="0"/>
<field name="Unk 2" size="6" start="10" type="uint" default="3"/>
<field name="Code" size="32" start="16" type="address"/>
</struct>
<struct name="USC Registers" size="4">
<field name="Tag" size="8" start="0" type="USC Control" default="Registers"/>
asahi: Identify more shader-related fields The big discovery is the "number of uniform registers" field. I learned about this one accidentally when my preamble shaders weren't working right, because we had inadvertently hardcoded "at most 32 registers" :-) In the course of identifying that field, I found that the pipeline address is used as a tagged pointer, with some unknown field in the bottom bits and alignment demanded. The XML is updated to account for this. I later found that there's also a "number of general purpose registers used by the preamble shader" field. I missed this one first, because the encoding is slightly different from the usual "number of general purpose registers in the main shader" field. The specification is slightly coarser. I don't know why the hardware needs that information anyway -- occupancy of the preamble shader should be irrelevant -- but it's not a big deal. Finally I found that the "more than 4 textures?" bit is... not that. I do not yet know what it is, but it is... not that. These all use the new groups() modifier for GenXML Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
2022-10-13 23:08:11 -04:00
<field name="Register count" size="5" start="8" type="uint" modifier="groups(8)"/>
asahi: Overhaul USC control packing Break up the monolithic SET_SHADER_EXTENDED packet into the separate underlying commands (some only 2-byte sized and aligned), and add a builder for USC control streams like we did for PPP updates to make that change manageable. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-17 11:22:01 -04:00
<field name="Unk 1" size="1" start="13" type="bool" default="false"/>
<field name="Spill size" size="8" start="16" type="hex" default="0"/> <!-- TODO: determine relation, see docs/table.py -->
<field name="Unk 4" size="8" start="24" type="hex" default="0x1"/>
</struct>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
asahi: Overhaul USC control packing Break up the monolithic SET_SHADER_EXTENDED packet into the separate underlying commands (some only 2-byte sized and aligned), and add a builder for USC control streams like we did for PPP updates to make that change manageable. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-17 11:22:01 -04:00
<struct name="USC No Preshader" size="2">
<field name="Tag" size="8" start="0" type="USC Control" default="No preshader"/>
</struct>
<struct name="USC Preshader" size="8">
<field name="Tag" size="8" start="0" type="USC Control" default="Preshader"/>
<field name="Unk" size="24" start="8" type="hex" default="0xc08000"/>
<field name="Code" size="32" start="32" type="address"/>
</struct>
<struct name="USC Fragment Properties" size="4">
<field name="Tag" size="8" start="0" type="USC Control" default="Fragment properties"/>
asahi: Break out Fragment Parameters word What the other 31 bits are for is anyone's guess. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14219>
2022-01-16 12:54:10 -05:00
<!-- Guess. Set if the shader does not write the sample mask (including by
discard_fragment) -->
asahi: Overhaul USC control packing Break up the monolithic SET_SHADER_EXTENDED packet into the separate underlying commands (some only 2-byte sized and aligned), and add a builder for USC control streams like we did for PPP updates to make that change manageable. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-17 11:22:01 -04:00
<field name="Early-z testing" size="1" start="8" type="bool"/>
<field name="Unk 2" size="1" start="9" type="bool" default="true"/>
<field name="Unconditional discard 1" size="1" start="10" type="bool"/>
<field name="Unconditional discard 2" size="1" start="11" type="bool"/>
<field name="Unk 3" size="4" start="12" type="hex" default="0xf"/>
<field name="Unk 4" size="8" start="16" type="hex" default="0"/> <!-- TODO: determine relation, see docs/table.py -->
<field name="Unk 5" size="8" start="24" type="hex" default="0x01"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
</struct>
asahi: Consolidate magic numbers for USC controls Aka "pipeline" states. It's another command/control stream. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-15 17:15:44 -04:00
<!-- USC commands end -->
asahi: Express VDM commands according to PowerVR Piles of unknown bits go away, as we find they're either "field present" bits or block types. And yep, the block type enum lines up between AGX and RGX. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-05 15:49:39 -04:00
<!-- VDM commands start. VDM commands are padded out to 8b alignment. -->
<enum name="VDM Block Type">
<value name="PPP State Update" value="0"/>
<value name="VDM State Update" value="2"/>
<value name="Index List" value="3"/>
asahi: Handle Stream Link VDM commands Jumps in the command streams, allowing us to chain ("link") command buffers. Naming is from PowerVR, which contains an identical command. PowerVR's has conditional jumps and function call support, it's likely that AGX inherited this too but I haven't tested that. (Those might be useful for conditional rendering and secondary command buffers respectively?) Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-05 17:43:34 -04:00
<value name="Stream Link" value="4"/>
asahi: Express VDM commands according to PowerVR Piles of unknown bits go away, as we find they're either "field present" bits or block types. And yep, the block type enum lines up between AGX and RGX. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-05 15:49:39 -04:00
<value name="Stream terminate" value="6"/>
</enum>
<struct name="PPP State" size="8">
<field name="Pointer (hi)" size="8" start="0" type="hex"/>
<field name="Size (words)" size="8" start="8" type="uint"/>
<field name="Block Type" size="3" start="29" type="VDM Block Type" default="PPP State Update"/>
<field name="Pointer (lo)" size="32" start="32" type="address"/>
</struct>
<enum name="Index size">
<value name="U8" value="0"/>
<value name="U16" value="1"/>
<value name="U32" value="2"/>
</enum>
asahi: Annotate VDM/CDM commands as per PVR Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-05 15:17:10 -04:00
asahi: Express VDM commands according to PowerVR Piles of unknown bits go away, as we find they're either "field present" bits or block types. And yep, the block type enum lines up between AGX and RGX. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-05 15:49:39 -04:00
<struct name="VDM State" size="4">
<field name="Restart index present" size="1" start="0" type="bool"/>
<field name="Vertex shader word 0 present" size="1" start="1" type="bool"/>
<field name="Vertex shader word 1 present" size="1" start="2" type="bool"/>
<field name="Vertex outputs present" size="1" start="3" type="bool"/>
<field name="Vertex unknown present" size="1" start="5" type="bool"/>
<field name="Block Type" size="3" start="29" type="VDM Block Type" default="VDM State Update"/>
</struct>
<struct name="VDM State Restart Index" size="4">
<field name="Value" size="32" start="0" type="hex"/>
</struct>
<struct name="VDM State Vertex Shader Word 0" size="4">
asahi: Identify more shader-related fields The big discovery is the "number of uniform registers" field. I learned about this one accidentally when my preamble shaders weren't working right, because we had inadvertently hardcoded "at most 32 registers" :-) In the course of identifying that field, I found that the pipeline address is used as a tagged pointer, with some unknown field in the bottom bits and alignment demanded. The XML is updated to account for this. I later found that there's also a "number of general purpose registers used by the preamble shader" field. I missed this one first, because the encoding is slightly different from the usual "number of general purpose registers in the main shader" field. The specification is slightly coarser. I don't know why the hardware needs that information anyway -- occupancy of the preamble shader should be irrelevant -- but it's not a big deal. Finally I found that the "more than 4 textures?" bit is... not that. I do not yet know what it is, but it is... not that. These all use the new groups() modifier for GenXML Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
2022-10-13 23:08:11 -04:00
<field name="Unknown 0" size="1" start="0" type="hex" default="0"/>
<field name="Uniform register count" size="3" start="1" type="uint" modifier="groups(64)"/>
<field name="Texture state register count" size="5" start="4" type="uint" modifier="groups(8)"/>
<field name="Sampler state register count" size="3" start="9" type="uint" modifier="groups(4)"/>
<field name="Preshader register count" size="4" start="12" type="uint" modifier="groups(16)"/>
asahi: Split vertex/fragment pipeline binds Although these are similar data structures, they are not identical and trying to cover both in the same struct is causing problems with aliasing. Split them out to get a more accurate representation. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-05-23 12:27:39 -04:00
</struct>
asahi: Fix using multiple textures/samplers The counts for textures/samplers are specified in the bind texture/sampler packets. What's in the bind pipeline appear to be... hints? of some kind? It's a direct function of the numbers of textures and samplers, but much more coarse. Unknown purpose. This should be correct for up to 48 textures and at least 8 samplers. For more than 48 textures, Metal switches to a "bindless" mode, where the textures are instead bound with a bind uniform packet, ts* is no longer read in the shader, and instead registers and immediates are used to index the texture with a substantial preshader. Details TBD. We don't need to worry about that for a long while, though. Fixes a number of dEQPs. dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.array_in_struct.sampler2D_samplerCube_both,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.array_in_struct.sampler2D_samplerCube_fragment,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.array_in_struct.sampler2D_samplerCube_vertex,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.nested_structs_arrays.sampler2D_samplerCube_both,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.nested_structs_arrays.sampler2D_samplerCube_fragment,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_pointer.render.nested_structs_arrays.sampler2D_samplerCube_vertex,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.array_in_struct.sampler2D_samplerCube_both,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.array_in_struct.sampler2D_samplerCube_fragment,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.array_in_struct.sampler2D_samplerCube_vertex,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.nested_structs_arrays.sampler2D_samplerCube_both,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.nested_structs_arrays.sampler2D_samplerCube_fragment,Crash dEQP-GLES2.functional.uniform_api.value.assigned.by_value.render.nested_structs_arrays.sampler2D_samplerCube_vertex,Crash Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/17198>
2022-01-18 21:54:22 -05:00
asahi: Express VDM commands according to PowerVR Piles of unknown bits go away, as we find they're either "field present" bits or block types. And yep, the block type enum lines up between AGX and RGX. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-05 15:49:39 -04:00
<struct name="VDM State Vertex Shader Word 1" size="4">
<field name="Pipeline" size="32" start="0" type="address"/>
</struct>
<struct name="VDM State Vertex Outputs" size="4">
<field name="Output count 1" size="8" start="0" type="uint" default="0"/>
<field name="Output count 2" size="8" start="8" type="uint" default="0"/>
</struct>
<struct name="VDM State Vertex Unknown" size="4">
asahi: Identify more shader-related fields The big discovery is the "number of uniform registers" field. I learned about this one accidentally when my preamble shaders weren't working right, because we had inadvertently hardcoded "at most 32 registers" :-) In the course of identifying that field, I found that the pipeline address is used as a tagged pointer, with some unknown field in the bottom bits and alignment demanded. The XML is updated to account for this. I later found that there's also a "number of general purpose registers used by the preamble shader" field. I missed this one first, because the encoding is slightly different from the usual "number of general purpose registers in the main shader" field. The specification is slightly coarser. I don't know why the hardware needs that information anyway -- occupancy of the preamble shader should be irrelevant -- but it's not a big deal. Finally I found that the "more than 4 textures?" bit is... not that. I do not yet know what it is, but it is... not that. These all use the new groups() modifier for GenXML Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18813>
2022-10-13 23:08:11 -04:00
<field name="Unknown" start="0" size="1" type="bool"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
</struct>
<!--- Command to issue a direct non-indexed draw -->
asahi: Express VDM commands according to PowerVR Piles of unknown bits go away, as we find they're either "field present" bits or block types. And yep, the block type enum lines up between AGX and RGX. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-05 15:49:39 -04:00
<struct name="Index List" size="4">
<field name="Index buffer hi" size="8" start="0" type="hex"/>
<field name="Primitive" size="8" start="8" type="Primitive"/>
<!-- Metal sets this bit for strips, probably wrong though -->
<field name="Restart enable" size="1" start="16" type="bool"/>
<field name="Index size" size="3" start="17" type="Index size"/>
<!-- XXX: Might be backwards, not sure how to check that -->
<field name="Index buffer present" size="1" start="20" type="bool"/>
<field name="Index buffer size present" size="1" start="21" type="bool"/>
<!-- XXX: Might be mixed up, not sure how to check that -->
<field name="Index count present" size="1" start="22" type="bool" default="true"/>
<field name="Instance count present" size="1" start="23" type="bool" default="true"/>
<field name="Start present" size="1" start="24" type="bool" default="true"/>
<field name="Block Type" size="3" start="29" type="VDM Block Type" default="Index List"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
</struct>
asahi: Express VDM commands according to PowerVR Piles of unknown bits go away, as we find they're either "field present" bits or block types. And yep, the block type enum lines up between AGX and RGX. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-05 15:49:39 -04:00
<struct name="Index List: Buffer lo" size="4">
<!-- Index buffer lsb -->
<field name="Buffer lo" size="32" start="0" type="hex"/>
</struct>
<struct name="Index List: Count" size="4">
<!-- Vertex count for non-indexed, index count for index count -->
<field name="Count" size="32" start="0" type="uint"/>
</struct>
<struct name="Index List: Instances" size="4">
<field name="Count" size="32" start="0" type="uint"/> <!-- must be nonzero -->
</struct>
<struct name="Index List: Start" size="4">
<!-- Base vertex for indexed draws -->
<field name="Start" size="32" start="0" type="uint"/>
</struct>
<struct name="Index List: Buffer size" size="4">
<field name="Size" size="32" start="0" type="uint" modifier="shr(2)"/>
</struct>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
asahi: Handle Stream Link VDM commands Jumps in the command streams, allowing us to chain ("link") command buffers. Naming is from PowerVR, which contains an identical command. PowerVR's has conditional jumps and function call support, it's likely that AGX inherited this too but I haven't tested that. (Those might be useful for conditional rendering and secondary command buffers respectively?) Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-05 17:43:34 -04:00
<!-- Conditional branching and function calls may be supported, see the
STREAM_LINK0 struct in mesa/src/imagination/csbgen/rogue_vdm.xml for a
probable dfinition -->
asahi: Identify CDM block types Same enum as PowerVR CDM, annoyingly different from the VDM block types. Split out the stream link / terminate structs (both observed with Metal for copious amounts of compute), in preparation for decoding "properly". Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-12 22:22:56 -04:00
<struct name="VDM Stream Link" size="8">
asahi: Handle Stream Link VDM commands Jumps in the command streams, allowing us to chain ("link") command buffers. Naming is from PowerVR, which contains an identical command. PowerVR's has conditional jumps and function call support, it's likely that AGX inherited this too but I haven't tested that. (Those might be useful for conditional rendering and secondary command buffers respectively?) Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-05 17:43:34 -04:00
<field name="Target hi" size="8" start="0" type="hex"/>
<field name="Block Type" size="3" start="29" type="VDM Block Type" default="Stream Link"/>
<field name="Target lo" size="32" start="32" type="hex"/>
</struct>
asahi: Identify CDM block types Same enum as PowerVR CDM, annoyingly different from the VDM block types. Split out the stream link / terminate structs (both observed with Metal for copious amounts of compute), in preparation for decoding "properly". Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-12 22:22:56 -04:00
<struct name="VDM Stream Terminate" size="8">
asahi: Express VDM commands according to PowerVR Piles of unknown bits go away, as we find they're either "field present" bits or block types. And yep, the block type enum lines up between AGX and RGX. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-05 15:49:39 -04:00
<field name="Block Type" size="3" start="29" type="VDM Block Type" default="Stream Terminate"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
</struct>
asahi: Annotate VDM/CDM commands as per PVR Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-05 15:17:10 -04:00
<!-- VDM commands end -->
<!-- CDM commands start -->
asahi: Identify CDM block types Same enum as PowerVR CDM, annoyingly different from the VDM block types. Split out the stream link / terminate structs (both observed with Metal for copious amounts of compute), in preparation for decoding "properly". Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-12 22:22:56 -04:00
<enum name="CDM Block Type">
<value name="Compute Kernel" value="0"/>
<value name="Stream Link" value="1"/>
<value name="Stream Terminate" value="2"/>
</enum>
asahi: Annotate VDM/CDM commands as per PVR Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-05 15:17:10 -04:00
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
<!--- Command to launch a direct compute kernel -->
<struct name="Launch" size="36">
asahi: Identify counts for compute kernels In the same place as for vertex/fragment. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19265>
2022-10-23 22:21:20 -04:00
<field name="Uniform register count" size="3" start="1" type="uint" modifier="groups(64)"/>
<field name="Texture state register count" size="5" start="4" type="uint" modifier="groups(8)"/>
<field name="Sampler state register count" size="3" start="9" type="uint" modifier="groups(4)"/>
<field name="Preshader register count" size="4" start="12" type="uint" modifier="groups(16)"/>
asahi: Identify CDM block types Same enum as PowerVR CDM, annoyingly different from the VDM block types. Split out the stream link / terminate structs (both observed with Metal for copious amounts of compute), in preparation for decoding "properly". Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-12 22:22:56 -04:00
<field name="Block Type" size="3" start="29" type="CDM Block Type" default="Compute Kernel"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
<field name="Pipeline" size="32" start="1:0" type="address"/>
<field name="Group count X" size="32" start="2:0" type="uint"/>
<field name="Group count Y" size="32" start="3:0" type="uint"/>
<field name="Group count Z" size="32" start="4:0" type="uint"/>
<field name="Local size X" size="32" start="5:0" type="uint"/>
<field name="Local size Y" size="32" start="6:0" type="uint"/>
<field name="Local size Z" size="32" start="7:0" type="uint"/>
asahi: Identify CDM block types Same enum as PowerVR CDM, annoyingly different from the VDM block types. Split out the stream link / terminate structs (both observed with Metal for copious amounts of compute), in preparation for decoding "properly". Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-12 22:22:56 -04:00
<field name="Unk 2" size="32" start="8:0" type="hex" default="0x60000160"/>
</struct>
<struct name="CDM Stream Link" size="8">
<field name="Target hi" size="8" start="0" type="hex"/>
<field name="Block Type" size="3" start="29" type="CDM Block Type" default="Stream Link"/>
<field name="Target lo" size="32" start="32" type="hex"/>
</struct>
<struct name="CDM Stream Terminate" size="8">
<field name="Block Type" size="3" start="29" type="CDM Block Type" default="Stream Terminate"/>
asahi: Add command buffer XML definitions Formatted for GenXML. Incomplete and probably riddled with errors, but a good start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Acked-by: Jason Ekstrand <jason@jlekstrand.net> Acked-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/10582>
2021-04-24 19:08:14 -04:00
</struct>
asahi: Add XML for the attachment structure We need a lot more control over these magic structures to get Z/S attachments working correctly. This is an early start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11730>
2021-07-05 19:26:20 -04:00
asahi: Annotate VDM/CDM commands as per PVR Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18421>
2022-09-05 15:17:10 -04:00
<!-- CDM commands end -->
asahi: Add XML for the attachment structure We need a lot more control over these magic structures to get Z/S attachments working correctly. This is an early start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11730>
2021-07-05 19:26:20 -04:00
<!--- The rest of this file is likely software defined by macOS kernel -->
<enum name="IOGPU Attachment Type">
asahi: Port driver to macOS 12.x ABI There's lots of reshuffling required. Nothing "interesting", though. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15482>
2022-03-20 21:03:00 -04:00
<value name="Colour" value="0xE"/>
<value name="Depth" value="0x10"/>
<value name="Stencil" value="0x11"/>
asahi: Add XML used for visibility tests Aka occlusion queries. There is an annoying limitation in the hardware (reflected in Metal) that only a single buffer may be bound per render pass, with the per-draw settings merely specifying an offset. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-04-02 14:58:44 -04:00
<value name="Visibility" value="0x12"/>
asahi: Add XML for the attachment structure We need a lot more control over these magic structures to get Z/S attachments working correctly. This is an early start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11730>
2021-07-05 19:26:20 -04:00
</enum>
<struct name="IOGPU Attachment" size="24">
<field name="Unk 0" start="0:0" size="16" default="0x100" type="hex"/>
<field name="Address" start="0:16" size="48" type="address"/>
<field name="Type" start="2:16" size="16" type="IOGPU Attachment Type"/>
asahi: Port driver to macOS 12.x ABI There's lots of reshuffling required. Nothing "interesting", though. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15482>
2022-03-20 21:03:00 -04:00
<field name="Size" start="3:9" size="32" type="uint"/>
asahi: Add XML for the attachment structure We need a lot more control over these magic structures to get Z/S attachments working correctly. This is an early start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/11730>
2021-07-05 19:26:20 -04:00
<field name="Unk 3" start="4:16" size="4" type="hex" default="0xC"/>
<!-- Percent of total attachment space used for this attachment, expressed
in a decimal percentage [0, 100] <field name="Percent" start="5:16" -->
<field name="Percent" start="5:16" size="16" type="uint"/>
</struct>
asahi: Identify IOGPU Clear Z/S structure Not sure on the details yet but identify and dump the data structure to start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15482>
2022-02-21 11:41:39 -05:00
asahi: Identify ZLS Control word from PowerVR We're into the cr.xml file now, which is the blob that gets passed through the kernel. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-05 21:42:20 -04:00
<enum name="ZLS Format">
<value name="32F" value="0"/>
<value name="16" value="2"/>
</enum>
<struct name="ZLS Control" size="8">
<field name="Unknown 0" start="0" size="1" type="bool"/>
<field name="Unknown 1" start="1" size="1" type="bool"/>
asahi: Identify compression-related XML Signed-off-by: Asahi Lina <lina@asahilina.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19999>
2022-11-23 22:21:18 +09:00
<field name="Z Compress 1" start="2" size="1" type="bool"/>
asahi: Identify ZLS Control word from PowerVR We're into the cr.xml file now, which is the blob that gets passed through the kernel. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-05 21:42:20 -04:00
<field name="Unknown 3" start="3" size="1" type="bool"/>
asahi: Identify compression-related XML Signed-off-by: Asahi Lina <lina@asahilina.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19999>
2022-11-23 22:21:18 +09:00
<field name="S Compress 1" start="4" size="1" type="bool"/>
asahi: Identify ZLS Control word from PowerVR We're into the cr.xml file now, which is the blob that gets passed through the kernel. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-05 21:42:20 -04:00
<field name="Unknown 5" start="5" size="1" type="bool"/>
asahi: Identify compression-related XML Signed-off-by: Asahi Lina <lina@asahilina.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19999>
2022-11-23 22:21:18 +09:00
<field name="Z Compress 2" start="6" size="1" type="bool"/>
asahi: Identify ZLS Control word from PowerVR We're into the cr.xml file now, which is the blob that gets passed through the kernel. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-05 21:42:20 -04:00
<field name="Unknown 7" start="7" size="1" type="bool"/>
asahi: Identify compression-related XML Signed-off-by: Asahi Lina <lina@asahilina.net> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19999>
2022-11-23 22:21:18 +09:00
<field name="S Compress 2" start="8" size="1" type="bool"/>
asahi: Identify ZLS Control word from PowerVR We're into the cr.xml file now, which is the blob that gets passed through the kernel. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-05 21:42:20 -04:00
<field name="S Load Enable" start="14" size="1" type="bool"/>
<field name="Z Load Enable" start="15" size="1" type="bool"/>
<field name="S Store Enable" start="18" size="1" type="bool"/>
<field name="Z Store Enable" start="19" size="1" type="bool"/>
<field name="Z Format" start="25" size="2" type="ZLS Format"/>
</struct>
asahi: Shuffle IOGPU structs We need the header to be common between gfx and compute, but everything else seems to be different. Shuffle so we can decode compute without any terrible hacks. I don't know the exact layout and don't care: the layout of the fields here is all software defined in macOS, even though the *values* are defined by hardware (or firmware in a few cases). Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-11 12:03:01 -04:00
<struct name="IOGPU Header" size="64">
<field name="Unk 0" start="0:0" size="32" default="0x10000" type="hex"/>
<field name="Total size" start="1:0" size="32" type="uint"/>
<!-- 0x7 in 11.x -->
<field name="Unk 2" start="2:0" size="32" default="0x4" type="hex"/>
<field name="Attachment length" start="9:0" size="32" type="uint"/>
<field name="Attachment offset" start="10:0" size="32" type="uint"/>
<field name="Unknown offset" start="11:0" size="32" type="uint"/>
<field name="Unk 4" start="12:0" size="32" default="0x30" type="hex"/>
<field name="Unk 5" start="13:0" size="32" default="0x01" type="hex"/>
<field name="Encoder" start="14:0" size="64" type="address"/>
</struct>
asahi: Identify spill buffer histogram Histogram of sizes of the spill buffer, with logarithmic bucket sizes (relative to the amount spilled from the perspective of a single thread). Pretty funny. Also mark a few unknowns that are nonzero when spilling is used. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-15 18:19:25 -04:00
<struct name="Spill Buffer Histogram" size="60">
<field name="Bin 0" start="0:0" size="4" type="uint"/>
<field name="Bin 1" start="1:0" size="4" type="uint"/>
<field name="Bin 2" start="2:0" size="4" type="uint"/>
<field name="Bin 3" start="3:0" size="4" type="uint"/>
<field name="Bin 4" start="4:0" size="4" type="uint"/>
<field name="Bin 5" start="5:0" size="4" type="uint"/>
<field name="Bin 6" start="6:0" size="4" type="uint"/>
<field name="Bin 7" start="7:0" size="4" type="uint"/>
<field name="Bin 8" start="8:0" size="4" type="uint"/>
<field name="Bin 9" start="9:0" size="4" type="uint"/>
<field name="Bin 10" start="10:0" size="4" type="uint"/>
<field name="Bin 11" start="11:0" size="4" type="uint"/>
<field name="Bin 12" start="12:0" size="4" type="uint"/>
<field name="Bin 13" start="13:0" size="4" type="uint"/>
<field name="Bin 14" start="14:0" size="4" type="uint"/>
</struct>
asahi: Identify IOGPU compute header Much simpler than the graphics one. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-14 20:07:54 -04:00
<struct name="IOGPU Compute" size="384">
<field name="Deflake 1" start="20:0" size="64" type="address"/>
<field name="Terminate of encoder" start="22:0" size="64" type="address"/>
<field name="Deflake 2" start="26:0" size="64" type="address"/>
<field name="Deflake 3" start="28:0" size="64" type="address"/>
<field name="Deflake 4" start="30:0" size="64" type="address"/>
<field name="Deflake 5" start="32:0" size="64" type="address"/>
<field name="Unk 34" start="34:0" size="32" default="1" type="hex"/>
<field name="Unk address" start="36:0" size="64" type="address"/>
<field name="Unk 40" start="40:0" size="32" default="0x1c" type="hex"/>
<field name="Encoder ID" start="41:0" size="32" type="hex"/>
<field name="Unk 44" start="44:0" size="32" default="0xffffffff" type="hex"/>
<field name="Unk 48" start="48:0" size="32" default="0x40" type="hex"/>
<field name="Unk 56" start="56:0" size="32" default="6" type="hex"/>
asahi: Identify spill buffer histogram Histogram of sizes of the spill buffer, with logarithmic bucket sizes (relative to the amount spilled from the perspective of a single thread). Pretty funny. Also mark a few unknowns that are nonzero when spilling is used. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-15 18:19:25 -04:00
<field name="Spilling unk 1" start="57:3" size="1" type="bool"/>
asahi: Identify IOGPU compute header Much simpler than the graphics one. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-14 20:07:54 -04:00
<field name="Unk 58" start="58:0" size="32" default="0x62" type="hex"/>
asahi: Identify spill buffer histogram Histogram of sizes of the spill buffer, with logarithmic bucket sizes (relative to the amount spilled from the perspective of a single thread). Pretty funny. Also mark a few unknowns that are nonzero when spilling is used. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-15 18:19:25 -04:00
<field name="Spill Buffer Histogram" start="60:0" size="480" type="Spill Buffer Histogram"/>
asahi: Identify IOGPU compute header Much simpler than the graphics one. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-14 20:07:54 -04:00
<field name="Unk 75" start="75:0" size="32" default="0x10000" type="hex"/>
<field name="Unk 94" start="94:0" size="32" default="0xffffffff" type="hex"/>
<field name="Unk 95" start="95:0" size="32" default="0xffffffff" type="hex"/>
</struct>
asahi: Shuffle IOGPU structs We need the header to be common between gfx and compute, but everything else seems to be different. Shuffle so we can decode compute without any terrible hacks. I don't know the exact layout and don't care: the layout of the fields here is all software defined in macOS, even though the *values* are defined by hardware (or firmware in a few cases). Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-11 12:03:01 -04:00
<struct name="IOGPU Graphics" size="1920">
<!-- if either deflake address is null, rendering gets flaky for high
geometry counts -->
<field name="Deflake 1" start="22:0" size="64" type="address"/>
<field name="Deflake 2" start="24:0" size="64" type="address"/>
<field name="Unk 54" start="38:0" size="32" default="0x6b0003" type="hex"/>
<field name="Unk 55" start="39:0" size="32" default="0x3a0012" type="hex"/>
<field name="Unk 56" start="40:0" size="32" default="0x1" type="hex"/>
<field name="Deflake 3" start="94:0" size="64" type="address"/>
<field name="Unk 112" start="96:0" size="32" default="0x1" type="hex"/>
<field name="Unk 114" start="98:0" size="32" default="0x1c" type="hex"/>
asahi: Note some magic bits used with memoryless RTs Obviously there can't *actually* be memoryless render targets, because how would partial renders work? The control stream with memoryless looks like everything would if it went to memory (e.g. full 2D MSAA attachments for the partial loads/stores even if only a resolved 2D image for the final store). Except the memoryless attachments all load from the same address 0xeeee0000. Clearly that's not actually what happens, so what gives? Unclear... but I see the magic bits mentioned here set, and I assume there are some firmware (or kernel) shenanigans used to JIT allocate the backing storage for partial renders. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-09 20:17:42 -05:00
<field name="Memoryless render targets used" start="100:0" size="1" type="bool"/>
asahi: Shuffle IOGPU structs We need the header to be common between gfx and compute, but everything else seems to be different. Shuffle so we can decode compute without any terrible hacks. I don't know the exact layout and don't care: the layout of the fields here is all software defined in macOS, even though the *values* are defined by hardware (or firmware in a few cases). Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-11 12:03:01 -04:00
<field name="OpenGL depth clipping" start="100:24" size="1" type="bool"/>
<field name="Unk 118" start="102:0" size="32" default="0xffffffff" type="hex"/>
<field name="Unk 119" start="103:0" size="32" default="0xffffffff" type="hex"/>
<field name="Unk 120" start="104:0" size="32" default="0xffffffff" type="hex"/>
<field name="Clear pipeline bind" start="146:0" size="32" type="hex"/>
<field name="Clear pipeline unk" start="148:0" size="4" default="4" type="hex"/>
<field name="Clear pipeline" start="148:4" size="28" type="address" modifier="shr(4)"/>
<field name="Store pipeline bind" start="154:0" size="32" type="hex"/>
<field name="Store pipeline unk" start="156:0" size="4" default="4" type="hex"/>
<field name="Store pipeline" start="156:4" size="28" type="address" modifier="shr(4)"/>
<field name="Scissor array" start="158:0" size="64" type="address"/>
<field name="Depth bias array" start="160:0" size="64" type="address"/>
<field name="ZLS control" start="164:0" size="32" type="ZLS Control"/>
<field name="Depth width" start="170:0" size="15" type="uint" default="1" modifier="minus(1)"/>
<field name="Depth height" start="170:15" size="15" type="uint" default="1" modifier="minus(1)"/>
<field name="Depth buffer 1" start="172:7" size="33" type="address" modifier="shr(7)"/>
asahi: Identify some more fields used with layered These values depend on the framebuffer width/height and maybe other stuff. Maybe strides. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20123>
2022-11-27 23:55:55 -05:00
<!-- Normally 0, 0x38001 with layered -->
<field name="Depth unknown 1" start="176:0" size="32" type="hex"/>
asahi: Shuffle IOGPU structs We need the header to be common between gfx and compute, but everything else seems to be different. Shuffle so we can decode compute without any terrible hacks. I don't know the exact layout and don't care: the layout of the fields here is all software defined in macOS, even though the *values* are defined by hardware (or firmware in a few cases). Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-11 12:03:01 -04:00
<field name="Depth acceleration buffer 1" start="178:7" size="33" type="address" modifier="shr(7)"/>
<field name="Depth buffer 2" start="182:7" size="33" type="address" modifier="shr(7)"/>
<field name="Depth acceleration buffer 2" start="188:7" size="33" type="address" modifier="shr(7)"/>
asahi: Identify some more fields used with layered These values depend on the framebuffer width/height and maybe other stuff. Maybe strides. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20123>
2022-11-27 23:55:55 -05:00
<!-- Normally 0, 0x38001 with layered -->
<field name="Depth unknown 2" start="186:0" size="32" type="hex"/>
asahi: Shuffle IOGPU structs We need the header to be common between gfx and compute, but everything else seems to be different. Shuffle so we can decode compute without any terrible hacks. I don't know the exact layout and don't care: the layout of the fields here is all software defined in macOS, even though the *values* are defined by hardware (or firmware in a few cases). Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-11 12:03:01 -04:00
<field name="Stencil buffer 1" start="192:7" size="33" type="address" modifier="shr(7)"/>
asahi: Identify some more fields used with layered These values depend on the framebuffer width/height and maybe other stuff. Maybe strides. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20123>
2022-11-27 23:55:55 -05:00
<!-- Normally 0, 0x10001 with layered -->
<field name="Stencil unknown 1" start="196:0" size="32" type="hex"/>
asahi: Shuffle IOGPU structs We need the header to be common between gfx and compute, but everything else seems to be different. Shuffle so we can decode compute without any terrible hacks. I don't know the exact layout and don't care: the layout of the fields here is all software defined in macOS, even though the *values* are defined by hardware (or firmware in a few cases). Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-11 12:03:01 -04:00
<field name="Stencil acceleration buffer 1" start="198:7" size="33" type="address" modifier="shr(7)"/>
<field name="Stencil buffer 2" start="202:7" size="33" type="address" modifier="shr(7)"/>
asahi: Identify some more fields used with layered These values depend on the framebuffer width/height and maybe other stuff. Maybe strides. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20123>
2022-11-27 23:55:55 -05:00
<!-- Normally 0, 0x10001 with layered -->
<field name="Stencil unknown 2" start="206:0" size="32" type="hex"/>
asahi: Shuffle IOGPU structs We need the header to be common between gfx and compute, but everything else seems to be different. Shuffle so we can decode compute without any terrible hacks. I don't know the exact layout and don't care: the layout of the fields here is all software defined in macOS, even though the *values* are defined by hardware (or firmware in a few cases). Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-11 12:03:01 -04:00
<field name="Stencil acceleration buffer 2" start="208:7" size="33" type="address" modifier="shr(7)"/>
asahi: Add some notes about unknowns to the XML Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
2022-10-23 17:44:11 -04:00
<!-- Proportional to tile width * tile height * sample count -->
asahi: Shuffle IOGPU structs We need the header to be common between gfx and compute, but everything else seems to be different. Shuffle so we can decode compute without any terrible hacks. I don't know the exact layout and don't care: the layout of the fields here is all software defined in macOS, even though the *values* are defined by hardware (or firmware in a few cases). Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-11 12:03:01 -04:00
<field name="Unk 212" start="212:0" size="32" default="0x4" type="hex"/>
<field name="Unk 214" start="214:0" size="16" default="0xc000" type="hex"/>
<field name="Z16 Unorm attachment 1" start="214:18" size="1" type="bool"/>
<field name="Width 1" start="216:0" size="32" type="uint"/>
<field name="Height 1" start="217:0" size="32" type="uint"/>
<field name="Pointer" start="218:0" size="64" type="address"/>
asahi: Identify spill buffer histogram Histogram of sizes of the spill buffer, with logarithmic bucket sizes (relative to the amount spilled from the perspective of a single thread). Pretty funny. Also mark a few unknowns that are nonzero when spilling is used. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-15 18:19:25 -04:00
<!-- 0x40 with frag spilling -->
<field name="Spilling unk 1" start="226:0" size="32" type="hex"/>
<field name="Spill Buffer Histogram" start="238:0" size="480" type="Spill Buffer Histogram"/>
asahi: Identify IOGPU Clear Z/S structure Not sure on the details yet but identify and dump the data structure to start. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15482>
2022-02-21 11:41:39 -05:00
<!-- Encoded like the depth attachment -->
asahi: Shuffle IOGPU structs We need the header to be common between gfx and compute, but everything else seems to be different. Shuffle so we can decode compute without any terrible hacks. I don't know the exact layout and don't care: the layout of the fields here is all software defined in macOS, even though the *values* are defined by hardware (or firmware in a few cases). Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-11 12:03:01 -04:00
<field name="Depth clear value" start="276:0" size="32" type="hex"/>
<field name="Stencil clear value" start="277:0" size="8" type="uint"/>
<field name="Unk 277" start="277:8" size="8" type="hex" default="3"/>
<field name="Set when reloading Z or S 1" start="279:8" size="1" type="bool"/>
asahi: Identify spill buffer histogram Histogram of sizes of the spill buffer, with logarithmic bucket sizes (relative to the amount spilled from the perspective of a single thread). Pretty funny. Also mark a few unknowns that are nonzero when spilling is used. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-15 18:19:25 -04:00
<field name="Set when frag shader spills" start="279:24" size="1" type="bool"/>
asahi: Shuffle IOGPU structs We need the header to be common between gfx and compute, but everything else seems to be different. Shuffle so we can decode compute without any terrible hacks. I don't know the exact layout and don't care: the layout of the fields here is all software defined in macOS, even though the *values* are defined by hardware (or firmware in a few cases). Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-11 12:03:01 -04:00
<field name="Set when reloading Z or S 2" start="280:24" size="1" type="bool"/>
<field name="Z16 Unorm attachment 2" start="281:8" size="1" type="bool"/>
<field name="Unk 282" start="282:0" size="32" type="hex" default="0xffffffff"/>
<field name="Unk 283" start="283:0" size="32" type="hex" default="0xffffffff"/>
<field name="Unk 284" start="284:0" size="32" type="hex" default="0xffffffff"/>
<field name="Visibility result buffer" start="286:0" size="64" type="address"/>
<field name="Partial reload pipeline bind" start="296:0" size="32" type="hex"/>
<field name="Partial reload pipeline unk" start="298:0" size="4" default="4" type="hex"/>
<field name="Partial reload pipeline" start="298:4" size="28" type="address" modifier="shr(4)"/>
<field name="Partial store pipeline bind" start="304:0" size="32" type="hex"/>
<field name="Partial store pipeline unk" start="306:0" size="4" default="4" type="hex"/>
<field name="Partial store pipeline" start="306:4" size="28" type="address" modifier="shr(4)"/>
asahi: Port driver to macOS 12.x ABI There's lots of reshuffling required. Nothing "interesting", though. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15482>
2022-03-20 21:03:00 -04:00
<!-- New in 12.x -->
asahi: Shuffle IOGPU structs We need the header to be common between gfx and compute, but everything else seems to be different. Shuffle so we can decode compute without any terrible hacks. I don't know the exact layout and don't care: the layout of the fields here is all software defined in macOS, even though the *values* are defined by hardware (or firmware in a few cases). Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-11 12:03:01 -04:00
<field name="Depth buffer 3" start="340:0" size="64" type="address"/>
<field name="Depth acceleration buffer 3" start="342:0" size="64" type="address"/>
<field name="Stencil buffer 3" start="344:0" size="64" type="address"/>
<field name="Stencil acceleration buffer 3" start="346:0" size="64" type="address"/>
asahi: Identify IOGPU_MISC data structure This will be elaborated upon soon. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15482>
2022-02-21 13:09:36 -05:00
<!-- maybe only set when doing a depth clear? -->
asahi: Note some magic bits used with memoryless RTs Obviously there can't *actually* be memoryless render targets, because how would partial renders work? The control stream with memoryless looks like everything would if it went to memory (e.g. full 2D MSAA attachments for the partial loads/stores even if only a resolved 2D image for the final store). Except the memoryless attachments all load from the same address 0xeeee0000. Clearly that's not actually what happens, so what gives? Unclear... but I see the magic bits mentioned here set, and I assume there are some firmware (or kernel) shenanigans used to JIT allocate the backing storage for partial renders. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19811>
2022-11-09 20:17:42 -05:00
<!-- 0x1000000 bit set with memoryless render targets? -->
asahi: Shuffle IOGPU structs We need the header to be common between gfx and compute, but everything else seems to be different. Shuffle so we can decode compute without any terrible hacks. I don't know the exact layout and don't care: the layout of the fields here is all software defined in macOS, even though the *values* are defined by hardware (or firmware in a few cases). Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-11 12:03:01 -04:00
<field name="Unk 352" start="352:0" size="32" default="0x1" type="hex"/>
<field name="Unk 360" start="360:0" size="32" default="0x1c" type="hex"/>
<field name="Encoder ID" start="362:0" size="32" type="hex"/>
asahi: Identify IOGPU_MISC data structure This will be elaborated upon soon. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15482>
2022-02-21 13:09:36 -05:00
<!-- top bit maybe only set with a depth clear? -->
asahi: Shuffle IOGPU structs We need the header to be common between gfx and compute, but everything else seems to be different. Shuffle so we can decode compute without any terrible hacks. I don't know the exact layout and don't care: the layout of the fields here is all software defined in macOS, even though the *values* are defined by hardware (or firmware in a few cases). Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-11 12:03:01 -04:00
<field name="Unk 365" start="365:0" size="64" default="0x1ffffffff" type="hex"/>
<field name="Unknown buffer" start="370:0" size="64" type="address"/>
<field name="Width 2" start="382:0" size="32" type="uint"/>
<field name="Height 2" start="383:0" size="32" type="uint"/>
asahi: Add XML for layered rendering We don't need to support this for a while but it's good to know the mechanism. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
2022-11-18 22:46:55 -05:00
<field name="Sample count" start="384:0" size="32" default="1" type="uint"/>
<!-- Divided by 16 and rounded -->
<field name="Sample 0 X" start="385:0" size="5" default="8" type="uint"/>
<field name="Sample 0 Y" start="386:0" size="5" default="8" type="uint"/>
<field name="Sample 1 X" start="387:0" size="5" default="0" type="uint"/>
<field name="Sample 1 Y" start="388:0" size="5" default="0" type="uint"/>
<field name="Sample 2 X" start="389:0" size="5" default="0" type="uint"/>
<field name="Sample 2 Y" start="390:0" size="5" default="0" type="uint"/>
<field name="Sample 3 X" start="391:0" size="5" default="0" type="uint"/>
<field name="Sample 3 Y" start="392:0" size="5" default="0" type="uint"/>
asahi: Shuffle IOGPU structs We need the header to be common between gfx and compute, but everything else seems to be different. Shuffle so we can decode compute without any terrible hacks. I don't know the exact layout and don't care: the layout of the fields here is all software defined in macOS, even though the *values* are defined by hardware (or firmware in a few cases). Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-11 12:03:01 -04:00
<!-- if tile size 32x32: max(tib allocation, 8) rounded to POT
if tile size 32x16: that, halved
-->
<field name="Unk 49:0" start="401:0" size="32" default="8" type="uint"/>
<field name="Tile width" start="402:0" size="32" default="32" type="uint"/>
<field name="Tile height" start="403:0" size="32" default="32" type="uint"/>
asahi: Add XML for layered rendering We don't need to support this for a while but it's good to know the mechanism. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/19871>
2022-11-18 22:46:55 -05:00
<!-- Number of framebuffer layers when rendering to a layered framebuffer (1
otherwise). This affects tiling calculations. It also affects how many
times the background program and end-of-tile programs are executed. The
layer index is available in sr2. -->
<field name="Framebuffer layers" start="404:0" size="32" default="1" type="uint"/>
asahi: Shuffle IOGPU structs We need the header to be common between gfx and compute, but everything else seems to be different. Shuffle so we can decode compute without any terrible hacks. I don't know the exact layout and don't care: the layout of the fields here is all software defined in macOS, even though the *values* are defined by hardware (or firmware in a few cases). Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18623>
2022-09-11 12:03:01 -04:00
<field name="Unk 56:0" start="408:0" size="32" default="0" type="uint"/>
<field name="Unk 70:0" start="410:0" size="32" default="1" type="uint"/>
asahi: Identify IOGPU_MISC data structure This will be elaborated upon soon. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15482>
2022-02-21 13:09:36 -05:00
</struct>
asahi: Account for every byte of the cmdbuf This adds the remaining XML. I don't know how much of this is correct, but it nominally accounts for every byte. So there shouldn't be more surprises in the command buffer after this. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/16512>
2022-04-02 12:35:57 -04:00
<struct name="IOGPU Attachment Count" size="16">
<field name="Count" start="3:0" size="32" type="uint"/>
</struct>
asahi: Use a header more like Intel's GenXML We're trying to converge on a common schema. Signed-off-by: Alyssa Rosenzweig <alyssa@collabora.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/18922>
2022-09-30 21:16:35 -04:00
</genxml>
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