2012-04-10 12:01:50 -07:00
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/*
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* Copyright © 2012 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
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* IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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*
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*/
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2012-10-03 13:03:12 -07:00
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#include "brw_cfg.h"
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2016-03-09 15:38:55 -08:00
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#include "brw_shader.h"
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2012-04-10 12:01:50 -07:00
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2013-10-30 16:51:32 -07:00
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/** @file brw_cfg.cpp
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2012-04-10 12:01:50 -07:00
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*
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* Walks the shader instructions generated and creates a set of basic
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* blocks with successor/predecessor edges connecting them.
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*/
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2016-03-09 23:31:05 -08:00
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using namespace brw;
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2012-10-03 13:16:09 -07:00
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static bblock_t *
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2012-04-10 12:01:50 -07:00
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pop_stack(exec_list *list)
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{
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2012-10-03 13:16:09 -07:00
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bblock_link *link = (bblock_link *)list->get_tail();
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bblock_t *block = link->block;
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2014-05-12 14:40:40 -07:00
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link->link.remove();
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2012-04-10 12:01:50 -07:00
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return block;
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}
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2014-05-12 14:40:40 -07:00
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static exec_node *
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2019-08-05 17:36:40 -07:00
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link(void *mem_ctx, bblock_t *block, enum bblock_link_kind kind)
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2014-05-12 14:40:40 -07:00
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{
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2019-08-05 17:36:40 -07:00
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bblock_link *l = new(mem_ctx) bblock_link(block, kind);
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2014-05-12 14:40:40 -07:00
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return &l->link;
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}
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2019-09-27 14:49:14 -07:00
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void
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push_stack(exec_list *list, void *mem_ctx, bblock_t *block)
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{
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/* The kind of the link is immaterial, but we need to provide one since
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* this is (ab)using the edge data structure in order to implement a stack.
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*/
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list->push_tail(link(mem_ctx, block, bblock_link_logical));
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}
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2014-07-13 22:17:50 -07:00
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bblock_t::bblock_t(cfg_t *cfg) :
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2021-06-28 19:02:11 -07:00
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cfg(cfg), start_ip(0), end_ip(0), end_ip_delta(0), num(0)
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2012-04-10 12:01:50 -07:00
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{
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2014-09-01 15:01:23 -07:00
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instructions.make_empty();
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2012-04-10 12:01:50 -07:00
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parents.make_empty();
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children.make_empty();
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}
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void
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2019-08-05 17:36:40 -07:00
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bblock_t::add_successor(void *mem_ctx, bblock_t *successor,
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enum bblock_link_kind kind)
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2012-04-10 12:01:50 -07:00
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{
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2019-08-05 17:36:40 -07:00
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successor->parents.push_tail(::link(mem_ctx, this, kind));
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children.push_tail(::link(mem_ctx, successor, kind));
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2012-04-10 12:01:50 -07:00
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}
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2014-07-16 12:14:41 -07:00
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bool
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2019-08-05 17:36:40 -07:00
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bblock_t::is_predecessor_of(const bblock_t *block,
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enum bblock_link_kind kind) const
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2014-07-16 12:14:41 -07:00
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{
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foreach_list_typed_safe (bblock_link, parent, link, &block->parents) {
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2019-08-05 17:36:40 -07:00
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if (parent->block == this && parent->kind <= kind) {
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2014-07-16 12:14:41 -07:00
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return true;
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}
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}
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return false;
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}
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bool
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2019-08-05 17:36:40 -07:00
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bblock_t::is_successor_of(const bblock_t *block,
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enum bblock_link_kind kind) const
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2014-07-16 12:14:41 -07:00
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{
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foreach_list_typed_safe (bblock_link, child, link, &block->children) {
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2019-08-05 17:36:40 -07:00
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if (child->block == this && child->kind <= kind) {
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2014-07-16 12:14:41 -07:00
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return true;
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}
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}
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return false;
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}
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2014-07-15 14:51:43 -07:00
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static bool
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ends_block(const backend_instruction *inst)
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{
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enum opcode op = inst->opcode;
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return op == BRW_OPCODE_IF ||
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op == BRW_OPCODE_ELSE ||
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op == BRW_OPCODE_CONTINUE ||
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op == BRW_OPCODE_BREAK ||
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2017-10-13 17:52:00 -07:00
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op == BRW_OPCODE_DO ||
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2014-07-15 14:51:43 -07:00
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op == BRW_OPCODE_WHILE;
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}
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static bool
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starts_block(const backend_instruction *inst)
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{
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enum opcode op = inst->opcode;
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return op == BRW_OPCODE_DO ||
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op == BRW_OPCODE_ENDIF;
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}
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bool
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bblock_t::can_combine_with(const bblock_t *that) const
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{
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if ((const bblock_t *)this->link.next != that)
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return false;
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2014-09-01 15:01:23 -07:00
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if (ends_block(this->end()) ||
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starts_block(that->start()))
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2014-07-15 14:51:43 -07:00
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return false;
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return true;
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}
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void
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bblock_t::combine_with(bblock_t *that)
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{
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assert(this->can_combine_with(that));
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foreach_list_typed (bblock_link, link, link, &that->parents) {
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assert(link->block == this);
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}
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this->end_ip = that->end_ip;
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2014-09-01 15:01:23 -07:00
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this->instructions.append_list(&that->instructions);
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2014-07-15 14:51:43 -07:00
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this->cfg->remove_block(that);
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}
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2013-11-28 11:03:14 -08:00
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void
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2020-03-06 13:34:13 -08:00
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bblock_t::dump() const
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2013-11-28 11:03:14 -08:00
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{
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2020-03-06 13:34:13 -08:00
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const backend_shader *s = this->cfg->s;
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2013-11-28 11:03:14 -08:00
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int ip = this->start_ip;
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2014-09-01 15:01:23 -07:00
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foreach_inst_in_block(backend_instruction, inst, this) {
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2013-12-22 23:29:31 -08:00
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fprintf(stderr, "%5d: ", ip);
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2015-05-20 09:44:01 -07:00
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s->dump_instruction(inst);
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2013-11-28 11:03:14 -08:00
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ip++;
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}
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}
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2023-09-13 10:44:31 -07:00
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void
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bblock_t::unlink_list(exec_list *list)
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{
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assert(list == &parents || list == &children);
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const bool remove_parent = list == &children;
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foreach_list_typed_safe(bblock_link, link, link, list) {
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/* Also break the links from the other block back to this block. */
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exec_list *sub_list = remove_parent ? &link->block->parents : &link->block->children;
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foreach_list_typed_safe(bblock_link, sub_link, link, sub_list) {
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if (sub_link->block == this) {
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sub_link->link.remove();
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ralloc_free(sub_link);
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}
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}
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link->link.remove();
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ralloc_free(link);
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}
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}
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2020-03-06 13:34:13 -08:00
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cfg_t::cfg_t(const backend_shader *s, exec_list *instructions) :
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s(s)
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2012-11-20 17:30:46 -08:00
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{
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2013-10-23 11:16:26 -07:00
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mem_ctx = ralloc_context(NULL);
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2012-04-10 12:01:50 -07:00
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block_list.make_empty();
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2013-09-20 16:29:48 -07:00
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blocks = NULL;
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2012-04-10 12:01:50 -07:00
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num_blocks = 0;
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2013-11-30 20:38:48 -08:00
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bblock_t *cur = NULL;
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int ip = 0;
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2012-04-10 12:01:50 -07:00
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2012-10-03 13:16:09 -07:00
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bblock_t *entry = new_block();
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2013-12-02 10:29:49 -08:00
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bblock_t *cur_if = NULL; /**< BB ending with IF. */
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bblock_t *cur_else = NULL; /**< BB ending with ELSE. */
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2014-05-17 11:53:45 -07:00
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bblock_t *cur_do = NULL; /**< BB starting with DO. */
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2013-12-02 10:29:49 -08:00
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bblock_t *cur_while = NULL; /**< BB immediately following WHILE. */
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2013-11-28 23:39:02 -08:00
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exec_list if_stack, else_stack, do_stack, while_stack;
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2012-10-03 13:16:09 -07:00
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bblock_t *next;
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2012-04-10 12:01:50 -07:00
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2013-11-30 20:38:48 -08:00
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set_next_block(&cur, entry, ip);
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2012-04-10 12:01:50 -07:00
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2014-09-01 15:01:23 -07:00
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foreach_in_list_safe(backend_instruction, inst, instructions) {
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2012-04-10 12:01:50 -07:00
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/* set_next_block wants the post-incremented ip */
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ip++;
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2016-08-17 11:40:01 -07:00
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inst->exec_node::remove();
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2012-04-10 12:01:50 -07:00
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switch (inst->opcode) {
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case BRW_OPCODE_IF:
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2014-09-01 15:01:23 -07:00
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cur->instructions.push_tail(inst);
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2012-04-10 12:01:50 -07:00
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/* Push our information onto a stack so we can recover from
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* nested ifs.
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*/
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2019-09-27 14:49:14 -07:00
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push_stack(&if_stack, mem_ctx, cur_if);
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push_stack(&else_stack, mem_ctx, cur_else);
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2012-04-10 12:01:50 -07:00
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cur_if = cur;
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cur_else = NULL;
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/* Set up our immediately following block, full of "then"
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* instructions.
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*/
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next = new_block();
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2019-08-05 17:36:40 -07:00
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cur_if->add_successor(mem_ctx, next, bblock_link_logical);
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2012-04-10 12:01:50 -07:00
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2013-11-30 20:38:48 -08:00
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set_next_block(&cur, next, ip);
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2012-04-10 12:01:50 -07:00
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break;
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case BRW_OPCODE_ELSE:
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2014-09-01 15:01:23 -07:00
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cur->instructions.push_tail(inst);
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i965/cfg: Rework to make IF & ELSE blocks flow into ENDIF.
Previously we made the basic block following an ENDIF instruction a
successor of the basic blocks ending with IF and ELSE. The PRM says that
IF and ELSE instructions jump *to* the ENDIF, rather than over it.
This should be immaterial to dataflow analysis, except for if, break,
endif sequences:
START B1 <-B0 <-B9
0x00000100: cmp.g.f0(8) null g15<8,8,1>F g4<0,1,0>F
0x00000110: (+f0) if(8) 0 0 null 0x00000000UD
END B1 ->B2 ->B4
START B2 <-B1
break
0x00000120: break(8) 0 0 null 0D
END B2 ->B10
START B3
0x00000130: endif(8) 2 null 0x00000002UD
END B3 ->B4
The ENDIF block would have no parents, so dataflow analysis would
generate incorrect results, preventing copy propagation from eliminating
some instructions.
This patch changes the CFG to make ENDIF start rather than end basic
blocks, so that it can be the jump target of the IF and ELSE
instructions.
It helps three programs (including two fs8/fs16 pairs).
total instructions in shared programs: 1561126 -> 1561060 (-0.00%)
instructions in affected programs: 837 -> 771 (-7.89%)
More importantly, it allows copy propagation to handle more cases.
Disabling the register_coalesce() pass before this patch hurts 58
programs, while afterward it only hurts 11 programs.
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-11-28 21:33:05 -08:00
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cur_else = cur;
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2012-04-10 12:01:50 -07:00
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next = new_block();
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2015-07-10 19:49:49 -07:00
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assert(cur_if != NULL);
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2019-08-05 17:36:40 -07:00
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cur_if->add_successor(mem_ctx, next, bblock_link_logical);
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2019-09-27 14:49:42 -07:00
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cur_else->add_successor(mem_ctx, next, bblock_link_physical);
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2012-04-10 12:01:50 -07:00
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2013-11-30 20:38:48 -08:00
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set_next_block(&cur, next, ip);
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2012-04-10 12:01:50 -07:00
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break;
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2013-10-30 16:51:32 -07:00
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case BRW_OPCODE_ENDIF: {
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2023-09-11 11:10:30 -07:00
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bblock_t *cur_endif;
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2014-09-01 15:01:23 -07:00
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if (cur->instructions.is_empty()) {
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i965/cfg: Rework to make IF & ELSE blocks flow into ENDIF.
Previously we made the basic block following an ENDIF instruction a
successor of the basic blocks ending with IF and ELSE. The PRM says that
IF and ELSE instructions jump *to* the ENDIF, rather than over it.
This should be immaterial to dataflow analysis, except for if, break,
endif sequences:
START B1 <-B0 <-B9
0x00000100: cmp.g.f0(8) null g15<8,8,1>F g4<0,1,0>F
0x00000110: (+f0) if(8) 0 0 null 0x00000000UD
END B1 ->B2 ->B4
START B2 <-B1
break
0x00000120: break(8) 0 0 null 0D
END B2 ->B10
START B3
0x00000130: endif(8) 2 null 0x00000002UD
END B3 ->B4
The ENDIF block would have no parents, so dataflow analysis would
generate incorrect results, preventing copy propagation from eliminating
some instructions.
This patch changes the CFG to make ENDIF start rather than end basic
blocks, so that it can be the jump target of the IF and ELSE
instructions.
It helps three programs (including two fs8/fs16 pairs).
total instructions in shared programs: 1561126 -> 1561060 (-0.00%)
instructions in affected programs: 837 -> 771 (-7.89%)
More importantly, it allows copy propagation to handle more cases.
Disabling the register_coalesce() pass before this patch hurts 58
programs, while afterward it only hurts 11 programs.
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-11-28 21:33:05 -08:00
|
|
|
/* New block was just created; use it. */
|
|
|
|
|
cur_endif = cur;
|
|
|
|
|
} else {
|
|
|
|
|
cur_endif = new_block();
|
|
|
|
|
|
2019-08-05 17:36:40 -07:00
|
|
|
cur->add_successor(mem_ctx, cur_endif, bblock_link_logical);
|
i965/cfg: Rework to make IF & ELSE blocks flow into ENDIF.
Previously we made the basic block following an ENDIF instruction a
successor of the basic blocks ending with IF and ELSE. The PRM says that
IF and ELSE instructions jump *to* the ENDIF, rather than over it.
This should be immaterial to dataflow analysis, except for if, break,
endif sequences:
START B1 <-B0 <-B9
0x00000100: cmp.g.f0(8) null g15<8,8,1>F g4<0,1,0>F
0x00000110: (+f0) if(8) 0 0 null 0x00000000UD
END B1 ->B2 ->B4
START B2 <-B1
break
0x00000120: break(8) 0 0 null 0D
END B2 ->B10
START B3
0x00000130: endif(8) 2 null 0x00000002UD
END B3 ->B4
The ENDIF block would have no parents, so dataflow analysis would
generate incorrect results, preventing copy propagation from eliminating
some instructions.
This patch changes the CFG to make ENDIF start rather than end basic
blocks, so that it can be the jump target of the IF and ELSE
instructions.
It helps three programs (including two fs8/fs16 pairs).
total instructions in shared programs: 1561126 -> 1561060 (-0.00%)
instructions in affected programs: 837 -> 771 (-7.89%)
More importantly, it allows copy propagation to handle more cases.
Disabling the register_coalesce() pass before this patch hurts 58
programs, while afterward it only hurts 11 programs.
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-11-28 21:33:05 -08:00
|
|
|
|
2013-11-30 20:38:48 -08:00
|
|
|
set_next_block(&cur, cur_endif, ip - 1);
|
i965/cfg: Rework to make IF & ELSE blocks flow into ENDIF.
Previously we made the basic block following an ENDIF instruction a
successor of the basic blocks ending with IF and ELSE. The PRM says that
IF and ELSE instructions jump *to* the ENDIF, rather than over it.
This should be immaterial to dataflow analysis, except for if, break,
endif sequences:
START B1 <-B0 <-B9
0x00000100: cmp.g.f0(8) null g15<8,8,1>F g4<0,1,0>F
0x00000110: (+f0) if(8) 0 0 null 0x00000000UD
END B1 ->B2 ->B4
START B2 <-B1
break
0x00000120: break(8) 0 0 null 0D
END B2 ->B10
START B3
0x00000130: endif(8) 2 null 0x00000002UD
END B3 ->B4
The ENDIF block would have no parents, so dataflow analysis would
generate incorrect results, preventing copy propagation from eliminating
some instructions.
This patch changes the CFG to make ENDIF start rather than end basic
blocks, so that it can be the jump target of the IF and ELSE
instructions.
It helps three programs (including two fs8/fs16 pairs).
total instructions in shared programs: 1561126 -> 1561060 (-0.00%)
instructions in affected programs: 837 -> 771 (-7.89%)
More importantly, it allows copy propagation to handle more cases.
Disabling the register_coalesce() pass before this patch hurts 58
programs, while afterward it only hurts 11 programs.
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-11-28 21:33:05 -08:00
|
|
|
}
|
|
|
|
|
|
2014-09-01 15:01:23 -07:00
|
|
|
cur->instructions.push_tail(inst);
|
|
|
|
|
|
i965/cfg: Rework to make IF & ELSE blocks flow into ENDIF.
Previously we made the basic block following an ENDIF instruction a
successor of the basic blocks ending with IF and ELSE. The PRM says that
IF and ELSE instructions jump *to* the ENDIF, rather than over it.
This should be immaterial to dataflow analysis, except for if, break,
endif sequences:
START B1 <-B0 <-B9
0x00000100: cmp.g.f0(8) null g15<8,8,1>F g4<0,1,0>F
0x00000110: (+f0) if(8) 0 0 null 0x00000000UD
END B1 ->B2 ->B4
START B2 <-B1
break
0x00000120: break(8) 0 0 null 0D
END B2 ->B10
START B3
0x00000130: endif(8) 2 null 0x00000002UD
END B3 ->B4
The ENDIF block would have no parents, so dataflow analysis would
generate incorrect results, preventing copy propagation from eliminating
some instructions.
This patch changes the CFG to make ENDIF start rather than end basic
blocks, so that it can be the jump target of the IF and ELSE
instructions.
It helps three programs (including two fs8/fs16 pairs).
total instructions in shared programs: 1561126 -> 1561060 (-0.00%)
instructions in affected programs: 837 -> 771 (-7.89%)
More importantly, it allows copy propagation to handle more cases.
Disabling the register_coalesce() pass before this patch hurts 58
programs, while afterward it only hurts 11 programs.
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-11-28 21:33:05 -08:00
|
|
|
if (cur_else) {
|
2019-08-05 17:36:40 -07:00
|
|
|
cur_else->add_successor(mem_ctx, cur_endif, bblock_link_logical);
|
i965/cfg: Rework to make IF & ELSE blocks flow into ENDIF.
Previously we made the basic block following an ENDIF instruction a
successor of the basic blocks ending with IF and ELSE. The PRM says that
IF and ELSE instructions jump *to* the ENDIF, rather than over it.
This should be immaterial to dataflow analysis, except for if, break,
endif sequences:
START B1 <-B0 <-B9
0x00000100: cmp.g.f0(8) null g15<8,8,1>F g4<0,1,0>F
0x00000110: (+f0) if(8) 0 0 null 0x00000000UD
END B1 ->B2 ->B4
START B2 <-B1
break
0x00000120: break(8) 0 0 null 0D
END B2 ->B10
START B3
0x00000130: endif(8) 2 null 0x00000002UD
END B3 ->B4
The ENDIF block would have no parents, so dataflow analysis would
generate incorrect results, preventing copy propagation from eliminating
some instructions.
This patch changes the CFG to make ENDIF start rather than end basic
blocks, so that it can be the jump target of the IF and ELSE
instructions.
It helps three programs (including two fs8/fs16 pairs).
total instructions in shared programs: 1561126 -> 1561060 (-0.00%)
instructions in affected programs: 837 -> 771 (-7.89%)
More importantly, it allows copy propagation to handle more cases.
Disabling the register_coalesce() pass before this patch hurts 58
programs, while afterward it only hurts 11 programs.
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-11-28 21:33:05 -08:00
|
|
|
} else {
|
2015-06-22 11:09:49 -07:00
|
|
|
assert(cur_if != NULL);
|
2019-08-05 17:36:40 -07:00
|
|
|
cur_if->add_successor(mem_ctx, cur_endif, bblock_link_logical);
|
i965/cfg: Rework to make IF & ELSE blocks flow into ENDIF.
Previously we made the basic block following an ENDIF instruction a
successor of the basic blocks ending with IF and ELSE. The PRM says that
IF and ELSE instructions jump *to* the ENDIF, rather than over it.
This should be immaterial to dataflow analysis, except for if, break,
endif sequences:
START B1 <-B0 <-B9
0x00000100: cmp.g.f0(8) null g15<8,8,1>F g4<0,1,0>F
0x00000110: (+f0) if(8) 0 0 null 0x00000000UD
END B1 ->B2 ->B4
START B2 <-B1
break
0x00000120: break(8) 0 0 null 0D
END B2 ->B10
START B3
0x00000130: endif(8) 2 null 0x00000002UD
END B3 ->B4
The ENDIF block would have no parents, so dataflow analysis would
generate incorrect results, preventing copy propagation from eliminating
some instructions.
This patch changes the CFG to make ENDIF start rather than end basic
blocks, so that it can be the jump target of the IF and ELSE
instructions.
It helps three programs (including two fs8/fs16 pairs).
total instructions in shared programs: 1561126 -> 1561060 (-0.00%)
instructions in affected programs: 837 -> 771 (-7.89%)
More importantly, it allows copy propagation to handle more cases.
Disabling the register_coalesce() pass before this patch hurts 58
programs, while afterward it only hurts 11 programs.
Reviewed-by: Eric Anholt <eric@anholt.net>
2013-11-28 21:33:05 -08:00
|
|
|
}
|
2013-10-30 16:51:32 -07:00
|
|
|
|
2014-09-01 15:01:23 -07:00
|
|
|
assert(cur_if->end()->opcode == BRW_OPCODE_IF);
|
|
|
|
|
assert(!cur_else || cur_else->end()->opcode == BRW_OPCODE_ELSE);
|
2013-10-30 16:51:32 -07:00
|
|
|
|
2012-04-10 12:01:50 -07:00
|
|
|
/* Pop the stack so we're in the previous if/else/endif */
|
|
|
|
|
cur_if = pop_stack(&if_stack);
|
|
|
|
|
cur_else = pop_stack(&else_stack);
|
|
|
|
|
break;
|
2013-10-30 16:51:32 -07:00
|
|
|
}
|
2012-04-10 12:01:50 -07:00
|
|
|
case BRW_OPCODE_DO:
|
|
|
|
|
/* Push our information onto a stack so we can recover from
|
|
|
|
|
* nested loops.
|
|
|
|
|
*/
|
2019-09-27 14:49:14 -07:00
|
|
|
push_stack(&do_stack, mem_ctx, cur_do);
|
|
|
|
|
push_stack(&while_stack, mem_ctx, cur_while);
|
2012-04-10 12:01:50 -07:00
|
|
|
|
|
|
|
|
/* Set up the block just after the while. Don't know when exactly
|
|
|
|
|
* it will start, yet.
|
|
|
|
|
*/
|
|
|
|
|
cur_while = new_block();
|
|
|
|
|
|
2014-09-01 15:01:23 -07:00
|
|
|
if (cur->instructions.is_empty()) {
|
2014-05-17 11:53:45 -07:00
|
|
|
/* New block was just created; use it. */
|
|
|
|
|
cur_do = cur;
|
|
|
|
|
} else {
|
|
|
|
|
cur_do = new_block();
|
2012-04-10 12:01:50 -07:00
|
|
|
|
2019-08-05 17:36:40 -07:00
|
|
|
cur->add_successor(mem_ctx, cur_do, bblock_link_logical);
|
2014-05-17 11:53:45 -07:00
|
|
|
|
|
|
|
|
set_next_block(&cur, cur_do, ip - 1);
|
|
|
|
|
}
|
2014-09-01 15:01:23 -07:00
|
|
|
|
|
|
|
|
cur->instructions.push_tail(inst);
|
2017-10-13 17:52:00 -07:00
|
|
|
|
|
|
|
|
/* Represent divergent execution of the loop as a pair of alternative
|
|
|
|
|
* edges coming out of the DO instruction: For any physical iteration
|
|
|
|
|
* of the loop a given logical thread can either start off enabled
|
|
|
|
|
* (which is represented as the "next" successor), or disabled (if it
|
|
|
|
|
* has reached a non-uniform exit of the loop during a previous
|
|
|
|
|
* iteration, which is represented as the "cur_while" successor).
|
|
|
|
|
*
|
|
|
|
|
* The disabled edge will be taken by the logical thread anytime we
|
|
|
|
|
* arrive at the DO instruction through a back-edge coming from a
|
|
|
|
|
* conditional exit of the loop where divergent control flow started.
|
|
|
|
|
*
|
|
|
|
|
* This guarantees that there is a control-flow path from any
|
|
|
|
|
* divergence point of the loop into the convergence point
|
|
|
|
|
* (immediately past the WHILE instruction) such that it overlaps the
|
|
|
|
|
* whole IP region of divergent control flow (potentially the whole
|
|
|
|
|
* loop) *and* doesn't imply the execution of any instructions part
|
|
|
|
|
* of the loop (since the corresponding execution mask bit will be
|
|
|
|
|
* disabled for a diverging thread).
|
|
|
|
|
*
|
|
|
|
|
* This way we make sure that any variables that are live throughout
|
|
|
|
|
* the region of divergence for an inactive logical thread are also
|
|
|
|
|
* considered to interfere with any other variables assigned by
|
|
|
|
|
* active logical threads within the same physical region of the
|
|
|
|
|
* program, since otherwise we would risk cross-channel data
|
|
|
|
|
* corruption.
|
|
|
|
|
*/
|
|
|
|
|
next = new_block();
|
2019-08-05 17:36:40 -07:00
|
|
|
cur->add_successor(mem_ctx, next, bblock_link_logical);
|
|
|
|
|
cur->add_successor(mem_ctx, cur_while, bblock_link_physical);
|
2017-10-13 17:52:00 -07:00
|
|
|
set_next_block(&cur, next, ip);
|
2012-04-10 12:01:50 -07:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BRW_OPCODE_CONTINUE:
|
2014-09-01 15:01:23 -07:00
|
|
|
cur->instructions.push_tail(inst);
|
|
|
|
|
|
2017-10-13 17:52:00 -07:00
|
|
|
/* A conditional CONTINUE may start a region of divergent control
|
|
|
|
|
* flow until the start of the next loop iteration (*not* until the
|
|
|
|
|
* end of the loop which is why the successor is not the top-level
|
|
|
|
|
* divergence point at cur_do). The live interval of any variable
|
|
|
|
|
* extending through a CONTINUE edge is guaranteed to overlap the
|
|
|
|
|
* whole region of divergent execution, because any variable live-out
|
|
|
|
|
* at the CONTINUE instruction will also be live-in at the top of the
|
|
|
|
|
* loop, and therefore also live-out at the bottom-most point of the
|
|
|
|
|
* loop which is reachable from the top (since a control flow path
|
|
|
|
|
* exists from a definition of the variable through this CONTINUE
|
|
|
|
|
* instruction, the top of the loop, the (reachable) bottom of the
|
|
|
|
|
* loop, the top of the loop again, into a use of the variable).
|
|
|
|
|
*/
|
2015-07-10 19:49:49 -07:00
|
|
|
assert(cur_do != NULL);
|
2019-08-05 17:36:40 -07:00
|
|
|
cur->add_successor(mem_ctx, cur_do->next(), bblock_link_logical);
|
2012-04-10 12:01:50 -07:00
|
|
|
|
|
|
|
|
next = new_block();
|
2012-10-03 13:23:05 -07:00
|
|
|
if (inst->predicate)
|
2019-08-05 17:36:40 -07:00
|
|
|
cur->add_successor(mem_ctx, next, bblock_link_logical);
|
2019-09-27 14:50:00 -07:00
|
|
|
else
|
|
|
|
|
cur->add_successor(mem_ctx, next, bblock_link_physical);
|
2012-04-10 12:01:50 -07:00
|
|
|
|
2013-11-30 20:38:48 -08:00
|
|
|
set_next_block(&cur, next, ip);
|
2012-04-10 12:01:50 -07:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BRW_OPCODE_BREAK:
|
2014-09-01 15:01:23 -07:00
|
|
|
cur->instructions.push_tail(inst);
|
|
|
|
|
|
2017-10-13 17:52:00 -07:00
|
|
|
/* A conditional BREAK instruction may start a region of divergent
|
|
|
|
|
* control flow until the end of the loop if the condition is
|
|
|
|
|
* non-uniform, in which case the loop will execute additional
|
|
|
|
|
* iterations with the present channel disabled. We model this as a
|
|
|
|
|
* control flow path from the divergence point to the convergence
|
|
|
|
|
* point that overlaps the whole IP range of the loop and skips over
|
|
|
|
|
* the execution of any other instructions part of the loop.
|
|
|
|
|
*
|
|
|
|
|
* See the DO case for additional explanation.
|
|
|
|
|
*/
|
|
|
|
|
assert(cur_do != NULL);
|
2019-08-05 17:36:40 -07:00
|
|
|
cur->add_successor(mem_ctx, cur_do, bblock_link_physical);
|
2019-08-05 18:21:05 -07:00
|
|
|
cur->add_successor(mem_ctx, cur_while, bblock_link_logical);
|
2012-04-10 12:01:50 -07:00
|
|
|
|
|
|
|
|
next = new_block();
|
2012-10-03 13:23:05 -07:00
|
|
|
if (inst->predicate)
|
2019-08-05 17:36:40 -07:00
|
|
|
cur->add_successor(mem_ctx, next, bblock_link_logical);
|
2021-12-14 13:40:49 -08:00
|
|
|
else
|
|
|
|
|
cur->add_successor(mem_ctx, next, bblock_link_physical);
|
2012-04-10 12:01:50 -07:00
|
|
|
|
2013-11-30 20:38:48 -08:00
|
|
|
set_next_block(&cur, next, ip);
|
2012-04-10 12:01:50 -07:00
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
case BRW_OPCODE_WHILE:
|
2014-09-01 15:01:23 -07:00
|
|
|
cur->instructions.push_tail(inst);
|
2012-04-10 12:01:50 -07:00
|
|
|
|
2015-06-22 11:09:49 -07:00
|
|
|
assert(cur_do != NULL && cur_while != NULL);
|
2015-10-05 13:50:56 +02:00
|
|
|
|
2017-10-13 17:52:00 -07:00
|
|
|
/* A conditional WHILE instruction may start a region of divergent
|
|
|
|
|
* control flow until the end of the loop, just like the BREAK
|
|
|
|
|
* instruction. See the BREAK case for more details. OTOH an
|
|
|
|
|
* unconditional WHILE instruction is non-divergent (just like an
|
|
|
|
|
* unconditional CONTINUE), and will necessarily lead to the
|
|
|
|
|
* execution of an additional iteration of the loop for all enabled
|
|
|
|
|
* channels, so we may skip over the divergence point at the top of
|
|
|
|
|
* the loop to keep the CFG as unambiguous as possible.
|
|
|
|
|
*/
|
2019-08-05 17:36:40 -07:00
|
|
|
if (inst->predicate) {
|
|
|
|
|
cur->add_successor(mem_ctx, cur_do, bblock_link_logical);
|
|
|
|
|
} else {
|
|
|
|
|
cur->add_successor(mem_ctx, cur_do->next(), bblock_link_logical);
|
|
|
|
|
}
|
2015-10-05 13:50:56 +02:00
|
|
|
|
2013-11-30 20:38:48 -08:00
|
|
|
set_next_block(&cur, cur_while, ip);
|
2012-04-10 12:01:50 -07:00
|
|
|
|
|
|
|
|
/* Pop the stack so we're in the previous loop */
|
|
|
|
|
cur_do = pop_stack(&do_stack);
|
|
|
|
|
cur_while = pop_stack(&while_stack);
|
|
|
|
|
break;
|
|
|
|
|
|
|
|
|
|
default:
|
2014-09-01 15:01:23 -07:00
|
|
|
cur->instructions.push_tail(inst);
|
2012-04-10 12:01:50 -07:00
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2015-01-04 18:04:13 -08:00
|
|
|
cur->end_ip = ip - 1;
|
2012-04-10 12:01:50 -07:00
|
|
|
|
|
|
|
|
make_block_array();
|
|
|
|
|
}
|
|
|
|
|
|
2012-10-03 13:16:09 -07:00
|
|
|
cfg_t::~cfg_t()
|
2012-04-10 12:01:50 -07:00
|
|
|
{
|
|
|
|
|
ralloc_free(mem_ctx);
|
|
|
|
|
}
|
|
|
|
|
|
2014-07-13 22:17:50 -07:00
|
|
|
void
|
|
|
|
|
cfg_t::remove_block(bblock_t *block)
|
|
|
|
|
{
|
|
|
|
|
foreach_list_typed_safe (bblock_link, predecessor, link, &block->parents) {
|
2023-09-11 11:29:12 -07:00
|
|
|
/* cfg_t::validate checks that predecessor and successor lists are well
|
|
|
|
|
* formed, so it is known that the loop here would find exactly one
|
|
|
|
|
* block. Set old_link_kind to silence "variable used but not set"
|
|
|
|
|
* warnings.
|
|
|
|
|
*/
|
|
|
|
|
bblock_link_kind old_link_kind = bblock_link_logical;
|
|
|
|
|
|
2014-07-13 22:17:50 -07:00
|
|
|
/* Remove block from all of its predecessors' successor lists. */
|
|
|
|
|
foreach_list_typed_safe (bblock_link, successor, link,
|
|
|
|
|
&predecessor->block->children) {
|
|
|
|
|
if (block == successor->block) {
|
2023-09-11 11:29:12 -07:00
|
|
|
old_link_kind = successor->kind;
|
2014-07-13 22:17:50 -07:00
|
|
|
successor->link.remove();
|
|
|
|
|
ralloc_free(successor);
|
2023-09-11 11:29:12 -07:00
|
|
|
break;
|
2014-07-13 22:17:50 -07:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Add removed-block's successors to its predecessors' successor lists. */
|
|
|
|
|
foreach_list_typed (bblock_link, successor, link, &block->children) {
|
2023-09-11 10:01:22 -07:00
|
|
|
bool need_to_link = true;
|
2023-09-11 11:29:12 -07:00
|
|
|
bblock_link_kind new_link_kind = MAX2(old_link_kind, successor->kind);
|
2023-09-11 10:01:22 -07:00
|
|
|
|
|
|
|
|
foreach_list_typed_safe (bblock_link, child, link, &predecessor->block->children) {
|
|
|
|
|
/* There is already a link between the two blocks. If the links
|
|
|
|
|
* are the same kind or the link is logical, do nothing. If the
|
|
|
|
|
* existing link is physical and the proposed new link is logical,
|
|
|
|
|
* promote the existing link to logical.
|
|
|
|
|
*
|
|
|
|
|
* This is accomplished by taking the minimum of the existing link
|
|
|
|
|
* kind and the proposed link kind.
|
|
|
|
|
*/
|
|
|
|
|
if (child->block == successor->block) {
|
2023-09-11 11:29:12 -07:00
|
|
|
child->kind = MIN2(child->kind, new_link_kind);
|
2023-09-11 10:01:22 -07:00
|
|
|
need_to_link = false;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (need_to_link) {
|
2014-07-13 22:17:50 -07:00
|
|
|
predecessor->block->children.push_tail(link(mem_ctx,
|
2019-08-05 17:36:40 -07:00
|
|
|
successor->block,
|
2023-09-11 11:29:12 -07:00
|
|
|
new_link_kind));
|
2014-07-13 22:17:50 -07:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
foreach_list_typed_safe (bblock_link, successor, link, &block->children) {
|
2023-09-11 11:29:12 -07:00
|
|
|
/* cfg_t::validate checks that predecessor and successor lists are well
|
|
|
|
|
* formed, so it is known that the loop here would find exactly one
|
|
|
|
|
* block. Set old_link_kind to silence "variable used but not set"
|
|
|
|
|
* warnings.
|
|
|
|
|
*/
|
|
|
|
|
bblock_link_kind old_link_kind = bblock_link_logical;
|
|
|
|
|
|
2014-07-13 22:17:50 -07:00
|
|
|
/* Remove block from all of its childrens' parents lists. */
|
|
|
|
|
foreach_list_typed_safe (bblock_link, predecessor, link,
|
|
|
|
|
&successor->block->parents) {
|
|
|
|
|
if (block == predecessor->block) {
|
2023-09-11 11:29:12 -07:00
|
|
|
old_link_kind = predecessor->kind;
|
2014-07-13 22:17:50 -07:00
|
|
|
predecessor->link.remove();
|
|
|
|
|
ralloc_free(predecessor);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
/* Add removed-block's predecessors to its successors' predecessor lists. */
|
|
|
|
|
foreach_list_typed (bblock_link, predecessor, link, &block->parents) {
|
2023-09-11 10:01:22 -07:00
|
|
|
bool need_to_link = true;
|
2023-09-11 11:29:12 -07:00
|
|
|
bblock_link_kind new_link_kind = MAX2(old_link_kind, predecessor->kind);
|
2023-09-11 10:01:22 -07:00
|
|
|
|
|
|
|
|
foreach_list_typed_safe (bblock_link, parent, link, &successor->block->parents) {
|
|
|
|
|
/* There is already a link between the two blocks. If the links
|
|
|
|
|
* are the same kind or the link is logical, do nothing. If the
|
|
|
|
|
* existing link is physical and the proposed new link is logical,
|
|
|
|
|
* promote the existing link to logical.
|
|
|
|
|
*
|
|
|
|
|
* This is accomplished by taking the minimum of the existing link
|
|
|
|
|
* kind and the proposed link kind.
|
|
|
|
|
*/
|
|
|
|
|
if (parent->block == predecessor->block) {
|
2023-09-11 11:29:12 -07:00
|
|
|
parent->kind = MIN2(parent->kind, new_link_kind);
|
2023-09-11 10:01:22 -07:00
|
|
|
need_to_link = false;
|
|
|
|
|
break;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
if (need_to_link) {
|
2014-07-13 22:17:50 -07:00
|
|
|
successor->block->parents.push_tail(link(mem_ctx,
|
2019-08-05 17:36:40 -07:00
|
|
|
predecessor->block,
|
2023-09-11 11:29:12 -07:00
|
|
|
new_link_kind));
|
2014-07-13 22:17:50 -07:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
block->link.remove();
|
|
|
|
|
|
|
|
|
|
for (int b = block->num; b < this->num_blocks - 1; b++) {
|
|
|
|
|
this->blocks[b] = this->blocks[b + 1];
|
|
|
|
|
this->blocks[b]->num = b;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
this->blocks[this->num_blocks - 1]->num = this->num_blocks - 2;
|
|
|
|
|
this->num_blocks--;
|
|
|
|
|
}
|
|
|
|
|
|
2012-10-03 13:16:09 -07:00
|
|
|
bblock_t *
|
|
|
|
|
cfg_t::new_block()
|
2012-04-10 12:01:50 -07:00
|
|
|
{
|
2014-07-13 22:17:50 -07:00
|
|
|
bblock_t *block = new(mem_ctx) bblock_t(this);
|
2012-04-10 12:01:50 -07:00
|
|
|
|
|
|
|
|
return block;
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
2013-11-30 20:38:48 -08:00
|
|
|
cfg_t::set_next_block(bblock_t **cur, bblock_t *block, int ip)
|
2012-04-10 12:01:50 -07:00
|
|
|
{
|
2013-11-30 20:38:48 -08:00
|
|
|
if (*cur) {
|
|
|
|
|
(*cur)->end_ip = ip - 1;
|
2012-04-10 12:01:50 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
block->start_ip = ip;
|
2014-07-11 22:31:39 -07:00
|
|
|
block->num = num_blocks++;
|
2014-07-11 16:17:47 -07:00
|
|
|
block_list.push_tail(&block->link);
|
2013-11-30 20:38:48 -08:00
|
|
|
*cur = block;
|
2012-04-10 12:01:50 -07:00
|
|
|
}
|
|
|
|
|
|
|
|
|
|
void
|
2012-10-03 13:16:09 -07:00
|
|
|
cfg_t::make_block_array()
|
2012-04-10 12:01:50 -07:00
|
|
|
{
|
2012-10-03 13:16:09 -07:00
|
|
|
blocks = ralloc_array(mem_ctx, bblock_t *, num_blocks);
|
2012-04-10 12:01:50 -07:00
|
|
|
|
|
|
|
|
int i = 0;
|
2014-07-11 22:31:39 -07:00
|
|
|
foreach_block (block, this) {
|
2014-07-11 16:17:47 -07:00
|
|
|
blocks[i++] = block;
|
2012-04-10 12:01:50 -07:00
|
|
|
}
|
|
|
|
|
assert(i == num_blocks);
|
|
|
|
|
}
|
2013-11-28 11:03:14 -08:00
|
|
|
|
|
|
|
|
void
|
2020-03-06 13:34:13 -08:00
|
|
|
cfg_t::dump()
|
2013-11-28 11:03:14 -08:00
|
|
|
{
|
2016-03-09 23:31:05 -08:00
|
|
|
const idom_tree *idom = (s ? &s->idom_analysis.require() : NULL);
|
2014-02-18 16:35:56 -08:00
|
|
|
|
2014-07-11 22:31:39 -07:00
|
|
|
foreach_block (block, this) {
|
2016-03-10 20:49:54 -08:00
|
|
|
if (idom && idom->parent(block))
|
|
|
|
|
fprintf(stderr, "START B%d IDOM(B%d)", block->num,
|
|
|
|
|
idom->parent(block)->num);
|
2015-10-05 16:21:10 -07:00
|
|
|
else
|
|
|
|
|
fprintf(stderr, "START B%d IDOM(none)", block->num);
|
|
|
|
|
|
2014-05-12 14:40:40 -07:00
|
|
|
foreach_list_typed(bblock_link, link, link, &block->parents) {
|
2019-08-05 17:36:40 -07:00
|
|
|
fprintf(stderr, " <%cB%d",
|
|
|
|
|
link->kind == bblock_link_logical ? '-' : '~',
|
2014-07-11 22:31:39 -07:00
|
|
|
link->block->num);
|
2013-11-28 11:03:14 -08:00
|
|
|
}
|
2013-12-22 23:29:31 -08:00
|
|
|
fprintf(stderr, "\n");
|
2015-05-20 09:44:01 -07:00
|
|
|
if (s != NULL)
|
2020-03-06 13:34:13 -08:00
|
|
|
block->dump();
|
2014-07-11 22:31:39 -07:00
|
|
|
fprintf(stderr, "END B%d", block->num);
|
2014-05-12 14:40:40 -07:00
|
|
|
foreach_list_typed(bblock_link, link, link, &block->children) {
|
2019-08-05 17:36:40 -07:00
|
|
|
fprintf(stderr, " %c>B%d",
|
|
|
|
|
link->kind == bblock_link_logical ? '-' : '~',
|
2014-07-11 22:31:39 -07:00
|
|
|
link->block->num);
|
2013-11-28 11:03:14 -08:00
|
|
|
}
|
2013-12-22 23:29:31 -08:00
|
|
|
fprintf(stderr, "\n");
|
2013-11-28 11:03:14 -08:00
|
|
|
}
|
|
|
|
|
}
|
2014-02-18 16:35:56 -08:00
|
|
|
|
|
|
|
|
/* Calculates the immediate dominator of each block, according to "A Simple,
|
|
|
|
|
* Fast Dominance Algorithm" by Keith D. Cooper, Timothy J. Harvey, and Ken
|
|
|
|
|
* Kennedy.
|
|
|
|
|
*
|
|
|
|
|
* The authors claim that for control flow graphs of sizes normally encountered
|
|
|
|
|
* (less than 1000 nodes) that this algorithm is significantly faster than
|
|
|
|
|
* others like Lengauer-Tarjan.
|
|
|
|
|
*/
|
2016-03-10 20:49:54 -08:00
|
|
|
idom_tree::idom_tree(const backend_shader *s) :
|
|
|
|
|
num_parents(s->cfg->num_blocks),
|
|
|
|
|
parents(new bblock_t *[num_parents]())
|
2014-02-18 16:35:56 -08:00
|
|
|
{
|
|
|
|
|
bool changed;
|
2016-03-10 20:49:54 -08:00
|
|
|
|
|
|
|
|
parents[0] = s->cfg->blocks[0];
|
|
|
|
|
|
2014-02-18 16:35:56 -08:00
|
|
|
do {
|
|
|
|
|
changed = false;
|
|
|
|
|
|
2016-03-09 23:31:05 -08:00
|
|
|
foreach_block(block, s->cfg) {
|
2014-02-18 16:35:56 -08:00
|
|
|
if (block->num == 0)
|
|
|
|
|
continue;
|
|
|
|
|
|
|
|
|
|
bblock_t *new_idom = NULL;
|
2016-03-10 20:49:54 -08:00
|
|
|
foreach_list_typed(bblock_link, parent_link, link, &block->parents) {
|
|
|
|
|
if (parent(parent_link->block)) {
|
2016-03-10 20:56:47 -08:00
|
|
|
new_idom = (new_idom ? intersect(new_idom, parent_link->block) :
|
|
|
|
|
parent_link->block);
|
2014-02-18 16:35:56 -08:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
2016-03-10 20:49:54 -08:00
|
|
|
if (parent(block) != new_idom) {
|
|
|
|
|
parents[block->num] = new_idom;
|
2014-02-18 16:35:56 -08:00
|
|
|
changed = true;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
} while (changed);
|
|
|
|
|
}
|
|
|
|
|
|
2016-03-10 20:49:54 -08:00
|
|
|
idom_tree::~idom_tree()
|
|
|
|
|
{
|
|
|
|
|
delete[] parents;
|
|
|
|
|
}
|
|
|
|
|
|
2014-02-18 16:35:56 -08:00
|
|
|
bblock_t *
|
2016-03-09 23:31:05 -08:00
|
|
|
idom_tree::intersect(bblock_t *b1, bblock_t *b2) const
|
2014-02-18 16:35:56 -08:00
|
|
|
{
|
|
|
|
|
/* Note, the comparisons here are the opposite of what the paper says
|
|
|
|
|
* because we index blocks from beginning -> end (i.e. reverse post-order)
|
|
|
|
|
* instead of post-order like they assume.
|
|
|
|
|
*/
|
|
|
|
|
while (b1->num != b2->num) {
|
|
|
|
|
while (b1->num > b2->num)
|
2016-03-10 20:49:54 -08:00
|
|
|
b1 = parent(b1);
|
2014-02-18 16:35:56 -08:00
|
|
|
while (b2->num > b1->num)
|
2016-03-10 20:49:54 -08:00
|
|
|
b2 = parent(b2);
|
2014-02-18 16:35:56 -08:00
|
|
|
}
|
|
|
|
|
assert(b1);
|
|
|
|
|
return b1;
|
|
|
|
|
}
|
2014-02-26 16:07:52 -08:00
|
|
|
|
|
|
|
|
void
|
2016-03-10 20:49:54 -08:00
|
|
|
idom_tree::dump() const
|
2014-02-26 16:07:52 -08:00
|
|
|
{
|
2016-03-09 23:31:05 -08:00
|
|
|
printf("digraph DominanceTree {\n");
|
2016-03-10 20:49:54 -08:00
|
|
|
for (unsigned i = 0; i < num_parents; i++)
|
|
|
|
|
printf("\t%d -> %d\n", parents[i]->num, i);
|
2014-02-26 16:07:52 -08:00
|
|
|
printf("}\n");
|
|
|
|
|
}
|
2014-02-26 16:15:52 -08:00
|
|
|
|
|
|
|
|
void
|
2016-03-09 23:31:05 -08:00
|
|
|
cfg_t::dump_cfg()
|
2014-02-26 16:15:52 -08:00
|
|
|
{
|
2016-03-09 23:31:05 -08:00
|
|
|
printf("digraph CFG {\n");
|
|
|
|
|
for (int b = 0; b < num_blocks; b++) {
|
|
|
|
|
bblock_t *block = this->blocks[b];
|
|
|
|
|
|
|
|
|
|
foreach_list_typed_safe (bblock_link, child, link, &block->children) {
|
|
|
|
|
printf("\t%d -> %d\n", b, child->block->num);
|
2015-10-28 21:11:46 -07:00
|
|
|
}
|
2014-02-26 16:15:52 -08:00
|
|
|
}
|
|
|
|
|
printf("}\n");
|
|
|
|
|
}
|
2023-09-11 09:10:47 -07:00
|
|
|
|
|
|
|
|
#define cfgv_assert(assertion) \
|
|
|
|
|
{ \
|
|
|
|
|
if (!(assertion)) { \
|
|
|
|
|
fprintf(stderr, "ASSERT: CFG validation in %s failed!\n", stage_abbrev); \
|
|
|
|
|
fprintf(stderr, "%s:%d: '%s' failed\n", __FILE__, __LINE__, #assertion); \
|
|
|
|
|
abort(); \
|
|
|
|
|
} \
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
#ifndef NDEBUG
|
|
|
|
|
void
|
|
|
|
|
cfg_t::validate(const char *stage_abbrev)
|
|
|
|
|
{
|
|
|
|
|
foreach_block(block, this) {
|
|
|
|
|
foreach_list_typed(bblock_link, successor, link, &block->children) {
|
2023-09-11 10:01:22 -07:00
|
|
|
/* Each successor of a block must have one predecessor link back to
|
2023-09-11 09:10:47 -07:00
|
|
|
* the block.
|
|
|
|
|
*/
|
|
|
|
|
bool successor_links_back_to_predecessor = false;
|
|
|
|
|
bblock_t *succ_block = successor->block;
|
|
|
|
|
|
|
|
|
|
foreach_list_typed(bblock_link, predecessor, link, &succ_block->parents) {
|
|
|
|
|
if (predecessor->block == block) {
|
2023-09-11 10:01:22 -07:00
|
|
|
cfgv_assert(!successor_links_back_to_predecessor);
|
2023-09-11 11:29:12 -07:00
|
|
|
cfgv_assert(successor->kind == predecessor->kind);
|
2023-09-11 09:10:47 -07:00
|
|
|
successor_links_back_to_predecessor = true;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
cfgv_assert(successor_links_back_to_predecessor);
|
2023-09-11 11:29:12 -07:00
|
|
|
|
|
|
|
|
/* Each successor block must appear only once in the list of
|
|
|
|
|
* successors.
|
|
|
|
|
*/
|
|
|
|
|
foreach_list_typed_from(bblock_link, later_successor, link,
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|
|
|
|
&block->children, successor->link.next) {
|
|
|
|
|
cfgv_assert(successor->block != later_successor->block);
|
|
|
|
|
}
|
2023-09-11 09:10:47 -07:00
|
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}
|
|
|
|
|
|
|
|
|
|
foreach_list_typed(bblock_link, predecessor, link, &block->parents) {
|
2023-09-11 10:01:22 -07:00
|
|
|
/* Each predecessor of a block must have one successor link back to
|
2023-09-11 09:10:47 -07:00
|
|
|
* the block.
|
|
|
|
|
*/
|
|
|
|
|
bool predecessor_links_back_to_successor = false;
|
|
|
|
|
bblock_t *pred_block = predecessor->block;
|
|
|
|
|
|
|
|
|
|
foreach_list_typed(bblock_link, successor, link, &pred_block->children) {
|
|
|
|
|
if (successor->block == block) {
|
2023-09-11 10:01:22 -07:00
|
|
|
cfgv_assert(!predecessor_links_back_to_successor);
|
2023-09-11 11:29:12 -07:00
|
|
|
cfgv_assert(successor->kind == predecessor->kind);
|
2023-09-11 09:10:47 -07:00
|
|
|
predecessor_links_back_to_successor = true;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
cfgv_assert(predecessor_links_back_to_successor);
|
2023-09-11 11:29:12 -07:00
|
|
|
|
|
|
|
|
/* Each precessor block must appear only once in the list of
|
|
|
|
|
* precessors.
|
|
|
|
|
*/
|
|
|
|
|
foreach_list_typed_from(bblock_link, later_precessor, link,
|
|
|
|
|
&block->parents, predecessor->link.next) {
|
|
|
|
|
cfgv_assert(predecessor->block != later_precessor->block);
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
backend_instruction *first_inst = block->start();
|
|
|
|
|
if (first_inst->opcode == BRW_OPCODE_DO) {
|
|
|
|
|
/* A block starting with DO should have exactly two successors. One
|
|
|
|
|
* is a physical link to the block starting after the WHILE
|
|
|
|
|
* instruction. The other is a logical link to the block starting the
|
|
|
|
|
* body of the loop.
|
|
|
|
|
*/
|
|
|
|
|
bblock_t *physical_block = nullptr;
|
|
|
|
|
bblock_t *logical_block = nullptr;
|
|
|
|
|
|
|
|
|
|
foreach_list_typed(bblock_link, child, link, &block->children) {
|
|
|
|
|
if (child->kind == bblock_link_physical) {
|
|
|
|
|
cfgv_assert(physical_block == nullptr);
|
|
|
|
|
physical_block = child->block;
|
|
|
|
|
} else {
|
|
|
|
|
cfgv_assert(logical_block == nullptr);
|
|
|
|
|
logical_block = child->block;
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
cfgv_assert(logical_block != nullptr);
|
|
|
|
|
cfgv_assert(physical_block != nullptr);
|
2023-09-11 09:10:47 -07:00
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
}
|
|
|
|
|
#endif
|