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i965: Rename backend_visitor to backend_shader

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The backend_shader class really is a representation of a shader.  The fact
that it inherits from ir_visitor is somewhat immaterial.

Reviewed-by: Matt Turner <mattst88@gmail.com>
Reviewed-by: Kenneth Graunke <kenneth@whitecape.org>
This commit is contained in:
Jason Ekstrand 2015-05-20 09:44:01 -07:00
parent 1ca60de4c0
commit 99cb423320
13 changed files with 44 additions and 44 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

10
src/mesa/drivers/dri/i965/brw_cfg.cpp
View file

@ -141,12 +141,12 @@ bblock_t::combine_with(bblock_t *that)
}
void
bblock_t::dump(backend_visitor *v) const
bblock_t::dump(backend_shader *s) const
{
int ip = this->start_ip;
foreach_inst_in_block(backend_instruction, inst, this) {
fprintf(stderr, "%5d: ", ip);
v->dump_instruction(inst);
s->dump_instruction(inst);
ip++;
}
}
@ -411,7 +411,7 @@ cfg_t::make_block_array()
}
void
cfg_t::dump(backend_visitor *v)
cfg_t::dump(backend_shader *s)
{
if (idom_dirty)
calculate_idom();
@ -423,8 +423,8 @@ cfg_t::dump(backend_visitor *v)
link->block->num);
}
fprintf(stderr, "\n");
if (v != NULL)
block->dump(v);
if (s != NULL)
block->dump(s);
fprintf(stderr, "END B%d", block->num);
foreach_list_typed(bblock_link, link, link, &block->children) {
fprintf(stderr, " ->B%d",

4
src/mesa/drivers/dri/i965/brw_cfg.h
View file

@ -60,7 +60,7 @@ struct bblock_t {
bool is_successor_of(const bblock_t *block) const;
bool can_combine_with(const bblock_t *that) const;
void combine_with(bblock_t *that);
void dump(backend_visitor *v) const;
void dump(backend_shader *s) const;
backend_instruction *start();
const backend_instruction *start() const;
@ -273,7 +273,7 @@ struct cfg_t {
void calculate_idom();
static bblock_t *intersect(bblock_t *b1, bblock_t *b2);
void dump(backend_visitor *v);
void dump(backend_shader *s);
void dump_cfg();
void dump_domtree();
#endif

6
src/mesa/drivers/dri/i965/brw_dead_control_flow.cpp
View file

@ -36,11 +36,11 @@
* - if/else/endif
*/
bool
dead_control_flow_eliminate(backend_visitor *v)
dead_control_flow_eliminate(backend_shader *s)
{
bool progress = false;
foreach_block_safe (block, v->cfg) {
foreach_block_safe (block, s->cfg) {
bblock_t *if_block = NULL, *else_block = NULL, *endif_block = block;
bool found = false;
@ -115,7 +115,7 @@ dead_control_flow_eliminate(backend_visitor *v)
}
if (progress)
v->invalidate_live_intervals();
s->invalidate_live_intervals();
return progress;
}

2
src/mesa/drivers/dri/i965/brw_dead_control_flow.h
View file

@ -23,4 +23,4 @@
#include "brw_shader.h"
bool dead_control_flow_eliminate(backend_visitor *v);
bool dead_control_flow_eliminate(backend_shader *s);

4
src/mesa/drivers/dri/i965/brw_fs.cpp
View file

@ -4100,7 +4100,7 @@ fs_visitor::optimize()
snprintf(filename, 64, "%s%d-%04d-%02d-%02d-" #pass, \
stage_abbrev, dispatch_width, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
\
backend_visitor::dump_instructions(filename); \
backend_shader::dump_instructions(filename); \
} \
\
progress = progress || this_progress; \
@ -4113,7 +4113,7 @@ fs_visitor::optimize()
stage_abbrev, dispatch_width,
shader_prog ? shader_prog->Name : 0);
backend_visitor::dump_instructions(filename);
backend_shader::dump_instructions(filename);
}
bool progress;

2
src/mesa/drivers/dri/i965/brw_fs.h
View file

@ -66,7 +66,7 @@ namespace brw {
*
* Translates either GLSL IR or Mesa IR (for ARB_fragment_program) into FS IR.
*/
class fs_visitor : public backend_visitor
class fs_visitor : public backend_shader
{
public:
const fs_reg reg_null_f;

2
src/mesa/drivers/dri/i965/brw_fs_visitor.cpp
View file

@ -4125,7 +4125,7 @@ fs_visitor::fs_visitor(struct brw_context *brw,
struct gl_shader_program *shader_prog,
struct gl_program *prog,
unsigned dispatch_width)
: backend_visitor(brw, shader_prog, prog, prog_data, stage),
: backend_shader(brw, shader_prog, prog, prog_data, stage),
reg_null_f(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_F)),
reg_null_d(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_D)),
reg_null_ud(retype(brw_null_vec(dispatch_width), BRW_REGISTER_TYPE_UD)),

18
src/mesa/drivers/dri/i965/brw_schedule_instructions.cpp
View file

@ -399,10 +399,10 @@ schedule_node::set_latency_gen7(bool is_haswell)
class instruction_scheduler {
public:
instruction_scheduler(backend_visitor *v, int grf_count,
instruction_scheduler(backend_shader *s, int grf_count,
instruction_scheduler_mode mode)
{
this->bv = v;
this->bs = s;
this->mem_ctx = ralloc_context(NULL);
this->grf_count = grf_count;
this->instructions.make_empty();
@ -455,7 +455,7 @@ public:
int grf_count;
int time;
exec_list instructions;
backend_visitor *bv;
backend_shader *bs;
instruction_scheduler_mode mode;
@ -606,7 +606,7 @@ vec4_instruction_scheduler::get_register_pressure_benefit(backend_instruction *b
schedule_node::schedule_node(backend_instruction *inst,
instruction_scheduler *sched)
{
const struct brw_device_info *devinfo = sched->bv->devinfo;
const struct brw_device_info *devinfo = sched->bs->devinfo;
this->inst = inst;
this->child_array_size = 0;
@ -1384,7 +1384,7 @@ vec4_instruction_scheduler::issue_time(backend_instruction *inst)
void
instruction_scheduler::schedule_instructions(bblock_t *block)
{
const struct brw_device_info *devinfo = bv->devinfo;
const struct brw_device_info *devinfo = bs->devinfo;
backend_instruction *inst = block->end();
time = 0;
@ -1419,7 +1419,7 @@ instruction_scheduler::schedule_instructions(bblock_t *block)
if (debug) {
fprintf(stderr, "clock %4d, scheduled: ", time);
bv->dump_instruction(chosen->inst);
bs->dump_instruction(chosen->inst);
}
/* Now that we've scheduled a new instruction, some of its
@ -1435,7 +1435,7 @@ instruction_scheduler::schedule_instructions(bblock_t *block)
if (debug) {
fprintf(stderr, "\tchild %d, %d parents: ", i, child->parent_count);
bv->dump_instruction(child->inst);
bs->dump_instruction(child->inst);
}
child->cand_generation = cand_generation;
@ -1474,7 +1474,7 @@ instruction_scheduler::run(cfg_t *cfg)
if (debug) {
fprintf(stderr, "\nInstructions before scheduling (reg_alloc %d)\n",
post_reg_alloc);
bv->dump_instructions();
bs->dump_instructions();
}
/* Populate the remaining GRF uses array to improve the pre-regalloc
@ -1504,7 +1504,7 @@ instruction_scheduler::run(cfg_t *cfg)
if (debug) {
fprintf(stderr, "\nInstructions after scheduling (reg_alloc %d)\n",
post_reg_alloc);
bv->dump_instructions();
bs->dump_instructions();
}
}

20
src/mesa/drivers/dri/i965/brw_shader.cpp
View file

@ -754,11 +754,11 @@ brw_abs_immediate(enum brw_reg_type type, struct brw_reg *reg)
return false;
}
backend_visitor::backend_visitor(struct brw_context *brw,
struct gl_shader_program *shader_prog,
struct gl_program *prog,
struct brw_stage_prog_data *stage_prog_data,
gl_shader_stage stage)
backend_shader::backend_shader(struct brw_context *brw,
struct gl_shader_program *shader_prog,
struct gl_program *prog,
struct brw_stage_prog_data *stage_prog_data,
gl_shader_stage stage)
: brw(brw),
devinfo(brw->intelScreen->devinfo),
ctx(&brw->ctx),
@ -1147,13 +1147,13 @@ backend_instruction::remove(bblock_t *block)
}
void
backend_visitor::dump_instructions()
backend_shader::dump_instructions()
{
dump_instructions(NULL);
}
void
backend_visitor::dump_instructions(const char *name)
backend_shader::dump_instructions(const char *name)
{
FILE *file = stderr;
if (name && geteuid() != 0) {
@ -1182,7 +1182,7 @@ backend_visitor::dump_instructions(const char *name)
}
void
backend_visitor::calculate_cfg()
backend_shader::calculate_cfg()
{
if (this->cfg)
return;
@ -1190,7 +1190,7 @@ backend_visitor::calculate_cfg()
}
void
backend_visitor::invalidate_cfg()
backend_shader::invalidate_cfg()
{
ralloc_free(this->cfg);
this->cfg = NULL;
@ -1205,7 +1205,7 @@ backend_visitor::invalidate_cfg()
* trigger some of our asserts that surface indices are < BRW_MAX_SURFACES.
*/
void
backend_visitor::assign_common_binding_table_offsets(uint32_t next_binding_table_offset)
backend_shader::assign_common_binding_table_offsets(uint32_t next_binding_table_offset)
{
int num_textures = _mesa_fls(prog->SamplersUsed);

12
src/mesa/drivers/dri/i965/brw_shader.h
View file

@ -211,14 +211,14 @@ enum instruction_scheduler_mode {
SCHEDULE_POST,
};
class backend_visitor : public ir_visitor {
class backend_shader : public ir_visitor {
protected:
backend_visitor(struct brw_context *brw,
struct gl_shader_program *shader_prog,
struct gl_program *prog,
struct brw_stage_prog_data *stage_prog_data,
gl_shader_stage stage);
backend_shader(struct brw_context *brw,
struct gl_shader_program *shader_prog,
struct gl_program *prog,
struct brw_stage_prog_data *stage_prog_data,
gl_shader_stage stage);
public:

4
src/mesa/drivers/dri/i965/brw_vec4.cpp
View file

@ -1768,7 +1768,7 @@ vec4_visitor::run()
snprintf(filename, 64, "%s-%04d-%02d-%02d-" #pass, \
stage_abbrev, shader_prog ? shader_prog->Name : 0, iteration, pass_num); \
\
backend_visitor::dump_instructions(filename); \
backend_shader::dump_instructions(filename); \
} \
\
progress = progress || this_progress; \
@ -1781,7 +1781,7 @@ vec4_visitor::run()
snprintf(filename, 64, "%s-%04d-00-start",
stage_abbrev, shader_prog ? shader_prog->Name : 0);
backend_visitor::dump_instructions(filename);
backend_shader::dump_instructions(filename);
}
bool progress;

2
src/mesa/drivers/dri/i965/brw_vec4.h
View file

@ -73,7 +73,7 @@ class vec4_live_variables;
* Translates either GLSL IR or Mesa IR (for ARB_vertex_program and
* fixed-function) into VS IR.
*/
class vec4_visitor : public backend_visitor
class vec4_visitor : public backend_shader
{
public:
vec4_visitor(struct brw_context *brw,

2
src/mesa/drivers/dri/i965/brw_vec4_visitor.cpp
View file

@ -3682,7 +3682,7 @@ vec4_visitor::vec4_visitor(struct brw_context *brw,
shader_time_shader_type st_base,
shader_time_shader_type st_written,
shader_time_shader_type st_reset)
: backend_visitor(brw, shader_prog, prog, &prog_data->base, stage),
: backend_shader(brw, shader_prog, prog, &prog_data->base, stage),
c(c),
key(key),
prog_data(prog_data),