Commit graph

1788 commits

Author SHA1 Message Date
Patrice Mandin
0cd5c650d1 nouveau: PUT,GET, not 2xPUT 2007-03-11 14:02:40 +01:00
Nian Wu
b369724077 Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-07 16:01:50 -05:00
Thomas Hellstrom
6ffe94f008 Add via CX700. 2007-03-07 09:19:57 +01:00
Nian Wu
0a85c9fa02 Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-05 09:01:45 -05:00
Dave Airlie
188a93c9df radeon: make PCI GART aperture size variable, but making table size variable
This is precursor to getting a TTM backend for this stuff, and also
allows the PCI table to be allocated at fb 0
2007-03-04 19:10:46 +11:00
Dave Airlie
c9178c3d01 ati: make pcigart code able to handle variable size PCI GART aperture
This code doesn't enable a variable aperture it just modifies the codebase
to allow me fix it up later
2007-03-04 18:16:29 +11:00
Nian Wu
6c48b8e7ff Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-01 09:02:09 -05:00
Ben Skeggs
72caa48c82 nouveau: intrusive drm interface changes
graphics objects:
	- No longer takes flags/dmaobj parameters, requires some major changes
	  to the ddx to setup the object through the FIFO.  This change is
	  likely to cause breakages on some cards (tested on NV05,NV28,NV35,
	  NV40 and NV4E).
dma objects:
	- now takes a "class" parameter, not really used yet but we may need
	  it at some point.
	- parameters are checked, so clients can't randomly create DMA objects
	  pointing at whatever they feel like.
misc:
	- Added FB_SIZE/AGP_SIZE getparams
	- Read PFIFO_INTR in PFIFO irq handler, not PMC_INTR
	- Dump PGRAPH trap info on PGRAPH_INTR_NOTIFY if NSOURCE isn't
	  NOTIFICATION_PENDING.
2007-02-28 15:41:53 +11:00
Nian Wu
df2fc3ec62 Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-02-25 17:06:13 -08:00
Jakob Bornecrantz
9d8ba2d0d4 drm: remove unnecessary NULL checks, and fix some indents.. 2007-02-25 10:48:26 +11:00
Thomas Hellstrom
e0f53e59be Simple fence object sample driver for via, based on idling the GPU.
Buffer object driver for via.
Some changes to buffer object driver callbacks.
Improve fence flushing.
2007-02-16 20:22:24 +01:00
Thomas Hellstrom
7766378d97 Initial support for fence object classes.
(Fence objects belonging to different command submission mechanisms).
2007-02-15 12:11:38 +01:00
Thomas Hellstrom
a78f70faad Merge branch 'ttm-vram-0-1-branch' 2007-02-14 15:33:40 +01:00
Thomas Hellstrom
5c9a7b0f94 Remove an intel-specific hack and replace it with a fence driver callback. 2007-02-14 13:31:35 +01:00
Stephane Marchesin
f524870184 nouveau: fix the build on big endian (thanks CyberFoxx) 2007-02-14 00:08:55 +01:00
B. Rathmann
59af900e4f nouveau: fix memory initialization with multiple cards. 2007-02-14 00:07:31 +01:00
Thomas Hellstrom
e1460426b8 Bugzilla Bug #9457
Add refcounting of user waiters to the DRM hardware lock, so that we can use the
DRM_LOCK_CONT flag more conservatively.

Also add a kernel waiter refcount that if nonzero transfers the lock for the kernel context,
when it is released. This is useful when waiting for idle and can be used
for very simple fence object driver implementations for the new memory manager.

It also resolves the AIGLX startup deadlock for the sis and the via drivers.
i810, i830 still require that the hardware lock is really taken so the deadlock remains
for those two. I'm not sure about ffb. Anyone familiar with that code?
2007-02-13 20:47:30 +01:00
Wang Zhenyu
80095ffe01 i915: Add 965GM pci id update 2007-02-13 16:20:45 +08:00
Thomas Hellstrom
abc14ddfb5 Update flags and comments. 2007-02-12 21:40:42 +01:00
Aapo Tahkola
130c39be3c Sync r300_reg.h from mesa driver. #10210 2007-02-11 10:24:14 +02:00
Michel Dänzer
4f795a05f1 Merge branch 'i915-pageflip' 2007-03-10 00:11:10 +01:00
Michel Dänzer
d734992e6a i915: Only wait for pending flips before asynchronous flips again. 2007-03-10 00:10:49 +01:00
Michel Dänzer
0741064df4 i915: Do not wait for pending flips on both pipes at the same time.
The MI_WAIT_FOR_EVENT instruction does not support waiting for several events
at once, so this should fix the lockups with page flipping when both pipes are
enabled.
2007-03-09 16:39:13 +01:00
Ben Skeggs
1b3a6d4775 nouveau: remove a hack that's not needed since the last interface change. 2007-03-07 21:17:45 +11:00
Ben Skeggs
5bd0e52dba nouveau: ack PFIFO interrupts at PFIFO, not PMC. 2007-03-07 21:00:55 +11:00
Michel Dänzer
a33859184a i915: Eliminate dev_priv->current_page.
Always use dev_priv->sarea_priv->pf_current_page directly. This allows clients
to modify it as well while they hold the HW lock, e.g. in order to sync pages
between pipes.
2007-02-28 17:48:56 +01:00
Michel Dänzer
074e10b384 i915: Only clean up page flipping when the last client goes away, not any one. 2007-02-28 15:57:08 +01:00
Michel Dänzer
1cdc1b6fba i915: Don't emit waits for pending flips before emitting synchronous flips.
The assumption is that synchronous flips are not isolated usually, and waiting
for all of them could result in stalling the pipeline for long periods of time.

Also use i915_emit_mi_flush() instead of an old-fashioned way to achieve the
same effect.
2007-02-28 15:23:19 +01:00
Michel Dänzer
fd0fed3f1e i915: Fix test for synchronous flip affecting both pipes. 2007-02-28 12:33:56 +01:00
Michel Dänzer
1a0d890a42 i915: Add support for scheduled buffer swaps to be done as flips.
Unfortunately, emitting asynchronous flips during vertical blank results in
tearing. So we have to wait for the previous vertical blank and emit a
synchronous flip.
2007-02-22 17:21:18 +01:00
Michel Dänzer
5a40c043cc Add DRM_VBLANK_FLIP.
Used to request that a scheduled buffer swap be done as a flip instead of a
blit.
2007-02-22 17:19:30 +01:00
Michel Dänzer
6f89584e13 i915: Improved page flipping support, including triple buffering.
Pages are tracked independently on each pipe.

Bump the minor version for 3D clients to know page flipping is usable, and
bump driver date.
2007-02-19 15:08:40 +01:00
Michel Dänzer
34aa3393d0 i915: Page flipping enhancements.
Leave it to the client to wait for the flip to complete when necessary,
but wait for a previous flip to complete before emitting another one. This
should help avoid unnecessary stalling of the ring due to pending flips.

Call i915_do_cleanup_pageflip() unconditionally in preclose.
2007-02-19 15:08:40 +01:00
Michel Dänzer
078e430726 i915: Unify breadcrumb emission. 2007-02-19 15:08:40 +01:00
Thomas Hellstrom
53aee3122a I915 accelerated blit copy functional.
Fixed - to System memory copies are implemented by
flipping in a cache-coherent TTM,
blitting to it, and then flipping it out.
2007-02-09 16:36:53 +01:00
Eric Anholt
898aca1a66 Warning fix: correct type of i915_mmio argument. 2007-02-07 21:26:02 -08:00
Eric Anholt
ef9a9d3cd1 Define __iomem for systems without it. 2007-02-07 21:26:01 -08:00
Eric Anholt
8918748058 Add chip family flags to i915 driver, and fix a missing '"' in mach64 ID list. 2007-02-07 21:26:01 -08:00
Thomas Hellstrom
c1fbd8a566 Checkpoint commit.
Flag handling and memory type selection cleanup.
glxgears won't start.
2007-02-07 17:25:13 +01:00
Thomas Hellstrom
609e3b0375 Implement a policy for selecting memory types. 2007-02-06 14:20:33 +01:00
Stephane Marchesin
17985f07d6 nouveau: more work on the nv04 context switch code. 2007-02-06 01:17:32 +01:00
Stephane Marchesin
8c663b4e56 nouveau: and of course, I was missing the last nv04 piece. 2007-02-03 06:13:27 +01:00
Stephane Marchesin
0c13657c33 nouveau: plugin the nv04 graph init function. 2007-02-03 06:00:29 +01:00
Stephane Marchesin
7ab9e7f36f nouveau: cleanup the nv04 pgraph save/restore mechanism. 2007-02-03 05:56:42 +01:00
Stephane Marchesin
d69902db3b nouveau: fix nv04 graph routines for new register names. 2007-02-03 05:25:36 +01:00
Stephane Marchesin
5a072f32c8 nouveau: rename registers to their proper names. 2007-02-03 04:57:06 +01:00
Stephane Marchesin
e64dbef911 nouveau: add NV04 registers required for PGRAPH context switching. 2007-02-03 04:23:09 +01:00
Matthieu Castet
55f7859a25 nouveau: nv ctx switch opps the size of array was wrong 2007-02-02 23:01:03 +01:00
Matthieu Castet
63cf3b3da7 nouveau: nv10 ctx switch, some regs are nv17+ only 2007-02-02 20:08:33 +01:00
Thomas Hellstrom
6c04185857 via: Try to improve command-buffer chaining.
Bump driver date and patchlevel.
2007-02-02 09:22:30 +01:00