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1788 commits

Author SHA1 Message Date
Matthieu Castet
9b7211dd67 nouveau: nv10 per channel init from ddx 2007-04-10 23:20:13 +02:00
Jesse Barnes
44a8761302 Merge branch 'modesetting-101' of git+ssh://git.freedesktop.org/git/mesa/drm into origin/modesetting-101 
Conflicts:

	linux-core/drm_crtc.c - trivial merge
	linux-core/drm_crtc.h - trivial merge
	linux-core/intel_display.c - crtc_config -> mode_config
	shared-core/i915_dma.c - accommodate new init code in i915_init.c
 2007-04-10 10:45:55 -07:00
Jesse Barnes
b59285d738 Move i915 init code to new file, i915_init.c, and create a new high level 
init routine that runs at driver load time.
 2007-04-10 10:31:10 -07:00
Jesse Barnes
5130918e25 Add save/restore state for LVDS code, along with a few other LVDS related 
items to i915 private structure.
 2007-04-10 09:51:17 -07:00
David Airlie
1e39dc4323 export output name to userspace 2007-04-10 16:25:31 +10:00
David Airlie
40bd6dcd86 set the base address of the CRTC correctly 2007-04-10 15:20:50 +10:00
David Airlie
65f465ed5a fixup numerous issues with adding framebuffer support 
This still isn't perfect but it fixes a few oopses and cleans up
some of the tabs and bugs in the original fb limit code
 2007-04-10 14:49:49 +10:00
Jakob Bornecrantz
b50bda002b add addfb/rmfb ioctls 
Originally from Jakob, cleaned up by airlied.
 2007-04-10 18:44:47 +10:00
Oliver McFadden
059b5d9077 rs480: Renamed some unknown registers. See dri-devel list. 2007-04-09 23:23:40 +00:00
Ben Skeggs
2d7f9f59c3 nouveau: NV46 support 2007-04-09 23:20:26 +10:00
Dave Airlie
29f8fe8046 radeon: bump version for IGPGART support 2007-04-09 22:00:34 +10:00
Dave Airlie
a70f8e0ab2 radeon: add support for reverse engineered xpress200m 
The IGPGART setup code was traced using mmio-trace on fglrx by myself
and Phillip Ezolt <phillipezolt@gmail.com> on dri-devel.

This code doesn't let the 3D driver work properly as the card has no
vertex shader support.

Thanks to Matthew Garrett + Ubuntu for providing me some hardware to do this
work on.
 2007-04-09 21:52:59 +10:00
Dave Airlie
46257c51c1 i915: use breadcrumb macro everywhere 2007-04-06 20:21:44 +10:00
Ben Skeggs
78034c06df nouveau: make a note about a bit that breaks some cards 2007-04-06 03:27:55 +10:00
Ben Skeggs
38f52402a8 nouveau: Power up all card units by default on startup. 2007-04-06 03:26:19 +10:00
Dave Airlie
b4094864f1 checkpoint commit: implement SetCrtc so modes can in theory be set from user 
This hooks up the userspace mode set it "seems" to work.
 2007-04-05 18:01:02 +10:00
Dave Airlie
7bb112feca checkpoint commit: added getresources, crtc and output 
This adds the user interfaces from Jakob and hooks them up for 3 ioctls
GetResources, GetCrtc and GetOutput.

I've made the ids for everything fbs, crtcs, outputs and modes go via idr as
per krh's suggestion on irc as it make the code nice and consistent.
 2007-04-05 17:06:42 +10:00
Dave Airlie
5bffbd6e27 initial userspace interface to get modes 2007-04-05 13:34:50 +10:00
Dave Airlie
52f9028c84 Initial import of modesetting for intel driver in DRM 2007-04-05 11:21:06 +10:00
Thomas Hellstrom
139e4bbc73 Make sure we ack irqs before we read a breadcrumb so that 
breadcrumb updates that occur _AFTER_ we've read the breadcrumb really
generates a new IRQ.
 2007-04-03 10:29:15 +02:00
Oliver McFadden
5395a92d40 r300: Synchronize the register header file again. 
It's a good idea to keep these synchronized; even though the DRM doesn't use all
the defines, maintaining two different copies is prone to errors when the diff
gets bigger.
 2007-04-02 19:45:10 +00:00
Matthieu Castet
cbbdbd5e65 nouveau: fix usage of PGRAPH_CTX_CONTROL on nv20+ 
http://gitweb.freedesktop.org/?p=mesa/drm.git;a=commitdiff;h=17985f07d68322519919a7f629a6d2d9bf3916ed could have broken some nvxx_graph code : it rename NV03_PGRAPH_CTX_CONTROL to NV10_PGRAPH_CTX_CONTROL, but forgot to update it in nvxx_graph file.

Also when migrating init stuff in http://gitweb.freedesktop.org/?p=mesa/drm.git;a=commitdiff;h=674cefd4fe4b537a20a10edcb4ec5df55facca8e, NV04_PGRAPH_CTX_CONTROL is used everywhere but the old ddx code use NV_PGRAPH_CTX_CONTROL_NV04 or NV_PGRAPH_CTX_CONTROL.
 2007-04-01 14:31:41 +02:00
Matthieu Castet
25cedcf76f nouveau : nv10 ctx switch fix 
restoring NV10_PGRAPH_CTX_SWITCH1 now works
 2007-04-01 14:21:29 +02:00
Dave Airlie
bdc5a8b62e radeon: enable buffer manager 2007-04-01 19:09:00 +10:00
Dave Airlie
b1f0b2d960 radeon: de-static irq function, fixup fence/buffer 2007-04-01 18:24:23 +10:00
Dave Airlie
be5bf1346e copy over some files and reorg radeon to add ttm fencing not working yet 2007-04-01 16:48:38 +10:00
Matthieu Castet
223061e084 nouveau : set the correct PGRAPH_CTX_CONTROL register 
"5a072f32        (Stephane Marchesin     2007-02-03 04:57:06 +0100" broke nv10 ctx switch by setting wrong PGRAPH_CTX_CONTROL reg
 2007-04-01 00:44:11 +02:00
Eric Anholt
ddb1715e06 Merge branch 'crestline-qa', adding support for the 965GM chipset. 2007-03-30 13:11:39 -07:00
Stephane Marchesin
bdabc8f998 nouveau: fix nv04 context switches. 2007-03-29 00:54:18 +02:00
Dave Airlie
81b811da37 drm/i915: set the bo up at firstopen time not after DMA init 
This is required to use TTM to allocate the ring buffer.
 2007-03-27 18:01:31 +10:00
Nian Wu
406a894e52 Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-27 12:53:13 +08:00
Ben Skeggs
674cefd4fe nouveau: move card initialisation into the drm 
The PGRAPH init for the various cards will need cleaning up at some point,
a lot of the values written there are per-context state left over from the
all the hardcoding done in the ddx.

It's possible some cards get broken by this commit, let me know.
Tested on: NV5, NV18, NV28, NV35, NV40, NV4E
 2007-03-26 20:59:37 +10:00
Nian Wu
e7cd5a1e2d Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-23 17:00:41 +08:00
Ben Skeggs
4988fa4886 nouveau: rework nouveau_fifo_alloc() so the drm can create internal FIFOs 2007-03-23 15:25:37 +11:00
Ben Skeggs
2bb9de96d5 nouveau: remove unused cruft 2007-03-23 13:45:29 +11:00
Nian Wu
0467ad4118 Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-21 17:00:43 +08:00
Ben Skeggs
e22225416a nouveau: support multiple channels per client (breaks drm interface) 2007-03-21 17:57:47 +11:00
Nian Wu
8398b99d8d Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-19 17:00:31 +08:00
Dave Airlie
26aba875e1 more whitespace issues 2007-03-19 08:56:24 +11:00
Dave Airlie
2463b03cb4 whitespace cleanup pending a kernel merge 2007-03-19 08:23:43 +11:00
Nian Wu
df73975980 Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-14 17:00:27 +08:00
Oliver McFadden
93f66af76a r300: Renamed the CACHE_CTLSTAT values to include UNKNOWN in the name; not 
enough information is known about them to be sure as to what the values mean.
 2007-03-13 14:48:01 +00:00
Nian Wu
80d0018bc0 Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-13 17:00:31 +08:00
Oliver McFadden
a90c2854a7 Add defines for the values written to R300_RB3D_ZCACHE_CTLSTAT. 
Note that just like the values written to R300_RB3D_DSTCACHE_CTLSTAT these
values are really unknown; ideally more reverse engineering should be done to
determine what these values mean and when they should be set.
 2007-03-13 06:25:04 +00:00
Ben Skeggs
90f8c691a5 nouveau: make sure cmdbuf object gets destroyed 2007-03-13 14:55:54 +11:00
Ben Skeggs
1775202cf9 nouveau: associate all created objects with a channel + cleanups 2007-03-13 14:55:54 +11:00
Ben Skeggs
7e2bbe2954 nouveau: s/fifo/channel/ 2007-03-13 14:55:54 +11:00
Oliver McFadden
462a6ea4ca Corrected values written to R300_RB3D_DSTCACHE_CTLSTAT to either 
R300_RB3D_DSTCACHE_02 or R300_RB3D_DSTCACHE_0A, rather than hexadecimal values.
 2007-03-13 01:19:56 +00:00
Oliver McFadden
5667396e05 Guess another unknown register used for R300 pacification. 2007-03-13 00:50:05 +00:00
Nian Wu
ab75d50d6c Merge git://proxy01.pd.intel.com:9419/git/mesa/drm into crestline 2007-03-12 09:03:40 +08:00