Commit graph

1788 commits

Author SHA1 Message Date
Ben Skeggs
13e1377044 nouveau: Some checks on userspace object handles. 2007-07-11 12:39:30 +10:00
Dave Airlie
2c9e05cf4c Merge branch 'master' into cleanup
Conflicts:

	libdrm/xf86drm.c
	linux-core/drm_bo.c
	linux-core/drm_fence.c
2007-07-11 11:23:41 +10:00
Arthur Huillet
694e1c5c3f Added support for PCIGART for PCI(E) cards. Bumped DRM interface patchlevel. 2007-07-11 02:35:10 +02:00
Ian Romanick
a9c49be6f8 Fix ioctl types.
I had moved code from xgi_drv.h to xgi_drm.h before changing the ioctl
types for XGI_IOCTL_(FB|PCIE)_ALLOC.
2007-07-09 18:52:43 -07:00
Ian Romanick
1f4e24b429 Move types shared with user mode to xgi_drm.h. 2007-07-09 16:33:14 -07:00
Ben Skeggs
023f7d9c00 nouveau: Allocate mappable VRAM for notifiers.. 2007-07-09 23:58:00 +10:00
Ben Skeggs
31e33813e8 nouveau: Don't be so strict on <NV50 2007-07-09 20:02:14 +10:00
Ben Skeggs
3c58195ccd nouveau: Avoid oops
Turns out lastclose() gets called even if firstopen() has never been...
2007-07-09 16:16:44 +10:00
Ben Skeggs
c806bba466 nouveau/nv50: Initial channel/object support
Should be OK on G84 for a single channel, multiple channels *almost* work.

Untested on G80.
2007-07-09 16:16:44 +10:00
Ben Skeggs
3324342e42 nouveau: enable reporting for all PFIFO/PGRAPH irqs 2007-07-09 16:16:44 +10:00
Ben Skeggs
163f852612 nouveau: rewrite gpu object code
Allows multiple references to a single object, needed to support PCI(E)GART
scatter-gather DMA objects which would quickly fill PRAMIN if each channel
had its own.

Handle per-channel private instmem areas.  This is needed to support NV50,
but might be something we want to do on earlier chipsets at some point?

Everything that touches PRAMIN is a GPU object.
2007-07-09 16:16:44 +10:00
Michel Dänzer
5b726b6390 radeon: Improve vblank counter.
The frame counter seems to increase only at the end of vertical blank, so we
need to add 1 while in vertical blank.
2007-07-06 09:50:50 +02:00
Michel Dänzer
91990946fa One more spinlock initializer cleanup. 2007-07-03 12:33:51 +02:00
Alan Hourihane
70fd9351ed Move out the code from i915_dma_cleanup to unload to match
existing code.

This needs verifying.
2007-06-29 21:04:17 +01:00
Alan Hourihane
adff58223f Bring back code from merge that was accidentally removed. 2007-06-29 20:58:16 +01:00
Alan Hourihane
14c49df06b merge fixes 2007-06-29 20:14:09 +01:00
Alan Hourihane
8a78dead29 Merge branch 'master' of git+ssh://git.freedesktop.org/git/mesa/drm into modesetting-101
Conflicts:

	linux-core/drm_drv.c
	linux-core/drm_fops.c
	linux-core/drm_objects.h
	linux-core/drm_stub.c
	shared-core/i915_dma.c
2007-06-29 20:09:44 +01:00
Ben Skeggs
e26ec51146 nouveau: small RAMFC cleanups 2007-06-29 14:20:50 +10:00
Ben Skeggs
1c32fecd6d nouveau: Hack around possible Xv blit adaptor breakage 2007-06-28 21:01:17 +10:00
Ben Skeggs
2dd85772aa nouveau/nv10: Fix earlier NV1x chips
Can't use nv04 code for them, since an extra field was inserted into
RAMFC after DMA_PUT/GET.
2007-06-28 04:23:17 +10:00
Ben Skeggs
68ecf61647 nouveau: never touch PRAMIN with NV_WRITE, cleanup RAMHT code a bit 2007-06-28 03:26:44 +10:00
Ben Skeggs
18a6d1c9c3 nouveau: simplify PRAMIN access 2007-06-28 03:26:44 +10:00
Ben Skeggs
38617b6a26 nouveau: name some regs 2007-06-28 03:26:44 +10:00
Ben Skeggs
ce0d528d3c nouveau/nv50: skeletal backend 2007-06-28 03:26:43 +10:00
Ben Skeggs
695599f18d nouveau: Nuke DMA_OBJECT_INIT ioctl (bumps interface to 0.0.7)
For various reasons, this ioctl was a bad idea.

At channel creation we now automatically create DMA objects covering
available VRAM and GART memory, where the client used to do this themselves.

However, there is still a need to be able to create DMA objects pointing at
specific areas of memory (ie. notifiers).  Each channel is now allocated a
small amount of memory from which a client can suballocate things (such as
notifiers), and have a DMA object created which covers the suballocated area.
The NOTIFIER_ALLOC ioctl exposes this functionality.
2007-06-28 03:26:43 +10:00
Ben Skeggs
4f2dd78ff3 nouveau/nv04: Set NV_PFIFO_CACHE1_PUSH1 correctly + small tweaks 2007-06-28 03:04:48 +10:00
Thomas Hellstrom
9b9a127ed0 More 64-bit padding. 2007-06-26 23:25:40 +02:00
Ian Romanick
5c27f8a70e Add support SiS based XGI chips to SiS DRM. 2007-06-26 09:51:55 -07:00
Ben Skeggs
9f617522d9 nouveau: NV49/NV4B PGRAPH setup from jb17bsome and stephan_2303 2007-06-25 01:57:57 +10:00
Ben Skeggs
3dfc13e2da nouveau: kill some dead code 2007-06-24 19:00:44 +10:00
Ben Skeggs
5f05cd7086 nouveau: NV04/NV10/NV20 PGRAPH engtab functions
NV04/NV10 load_context()/save_context() are stubs.  I don't know enough about
how they work to implement them sanely.  The "old" context_switch() code
remains hooked up, so it shouldn't break anything.

NV20 will probably break if load_context() works.  No inital context values
are filled in, so when the first channel is created PGRAPH will probably end
up having its state zeroed.  Some setup from nv20_graph_init() will probably
need to be moved to the per-channel context setup.
2007-06-24 19:00:26 +10:00
Ben Skeggs
5d55b0655c nouveau: NV3X PGRAPH engtab functions 2007-06-24 18:58:38 +10:00
Ben Skeggs
341bc78207 nouveau: NV1X/2X/3X PFIFO engtab functions
Earlier NV1X chips use the NV04 code, see previous commits about NV10 RAMFC
entry size.
2007-06-24 18:58:14 +10:00
Ben Skeggs
05d86d950a nouveau: NV04 PFIFO engtab functions 2007-06-24 18:57:09 +10:00
Ben Skeggs
acb710d1a5 nouveau: NV4X PGRAPH engtab functions 2007-06-24 18:56:40 +10:00
Ben Skeggs
f2e64d5276 nouveau: NV4X PFIFO engtab functions 2007-06-24 18:56:01 +10:00
Ben Skeggs
0afb3b518e nouveau: split PFIFO/PGRAPH context creation 2007-06-24 18:55:23 +10:00
Ben Skeggs
9dbf322d26 nouveau: (mostly) hook up put_base again 2007-06-24 18:55:06 +10:00
Ben Skeggs
24b71c318a nouveau: prototype PFIFO/PGRAPH engtab API 2007-06-24 18:54:51 +10:00
Ben Skeggs
5c7c07fd49 nouveau: rename engtab functions 2007-06-24 18:54:36 +10:00
Jesse Barnes
7f2a1cf275 Merge branch 'vblank-rework' into vblank 2007-06-22 11:12:02 -07:00
Jesse Barnes
97dcd7fd25 more vblank rework
- use a timer for disabling vblank events to avoid enable/disable calls too
    often
  - make i915 work with pre-965 chips again (would like to structure this
    better, but this hack works on my test system)
2007-06-22 11:06:51 -07:00
Michel Dänzer
068ffc1e1b radeon: Acknowledge all interrupts we're interested in.
Failure to do so was probably the root cause of fd.o bug 11287.
2007-06-22 11:55:26 +02:00
Michel Dänzer
6e2cd7c163 drm_modeset_ctl_t fixes.
s/u64/drm_u64_t/ to allow userspace code using drm.h to compile.

Move 64 bit arg member to the beginning to avoid alignment issues with 32
bit userspace on 64 bit kernels.
2007-06-22 11:44:19 +02:00
Michel Dänzer
b8dd314875 Remove mask parameter from radeon_acknowledge_irqs().
Simply always acknowledge all interrupts we're interested in, to avoid hard
hangs when an unexpected interrupt is flagged.
2007-06-22 11:42:54 +02:00
Jesse Barnes
24c09faec1 Merge branch 'vblank-rework' into vblank 2007-06-21 15:26:34 -07:00
Jesse Barnes
afe842297f RADEON: fix race in vblank interrupt handling
It's possible that we disable vblank interrupts and clear the
corresponding flag in irq_enable_reg, but receive an interrupt at just
the wrong time, causing us to not ack it properly, nor report to the
core kernel that it was handled.  Fix that case by always handling
vblank interrupts, even if the irq_enable_reg field is clear.
2007-06-21 15:23:20 -07:00
Oliver McFadden
40f6a696cb r300: Synchronized the register defines file; documentation changes. 2007-06-21 14:35:11 +00:00
Oliver McFadden
213732af43 r300: Allow writes to R300_VAP_PVS_WAITIDLE. 2007-06-21 14:32:58 +00:00
Jesse Barnes
2d24455ed8 Remove broken CRTC enable checks and incorrect user irq enable in set_pipe
routine.
2007-06-18 17:43:58 -07:00