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1788 commits

Author SHA1 Message Date
Stephane Marchesin
ff9a019cf0 nouveau: add pure nv30 support. 2007-09-06 02:47:06 +02:00
Maarten Maathuis
ef4944de85 Add context init voodoo and context switch code for NV41. 2007-09-04 18:51:57 +02:00
Ian Romanick
fee49e2071 Merge branch 'master' of ssh+git://git.freedesktop.org/git/mesa/drm into xgi-0-0-2 2007-08-31 10:54:55 -07:00
Stephane Marchesin
bac3f49daa nouveau: nv04 context switching support. Works for starting X up at least. 2007-08-31 01:40:00 +02:00
Stephane Marchesin
69b11f44f0 nouveau: give nv03 the last cut. 2007-08-31 01:40:00 +02:00
Keith Packard
c78e610fa4 Add register defines for hw binning 2007-08-28 12:23:51 -07:00
Dave Airlie
589707b765 drm: remove XFREE86_VERSION macros 2007-08-28 15:17:36 +10:00
Matthieu Castet
a331d2e352 nouveau : add NV04_PGRAPH_TRAPPED_ADDR definition 
- fix offset for nv04
- use it in nv10 graph ctx switch for getting next channel
- dump NV10_PGRAPH_TRAPPED_DATA_HIGH on nv10+
 2007-08-26 20:48:32 +02:00
Matthieu Castet
4182fce408 nouveau : nv1x graph reworks 
- add forgotten init value
- use the same PGRAPH_DEBUG than the blob
- remove init of ddx reg : it should be done with object
- better handle of channel destruction

hope I didn't break anything ;)
 2007-08-25 22:10:45 +02:00
Patrice Mandin
502bbdbe14 nouveau: nv10: output a warning if last channel invalid, and switch to next 2007-08-25 00:12:58 +02:00
Patrice Mandin
9875011196 nouveau: nv10: check some NULL pointers inside context switch 2007-08-23 10:20:44 +02:00
Matthieu Castet
8645dac895 nouveau : fix some potential crashes with objects causing hash collision 2007-08-22 23:20:14 +02:00
Ben Skeggs
11c46afe75 nouveau/nv40: Preserve other bits in 0x400304/0x400310 like NVIDIA do. 2007-08-22 13:23:49 +10:00
Ben Skeggs
a654c0341a nouveau/nv40: Dump extra info on ucode state if ctx switch fails. 2007-08-22 13:19:21 +10:00
Ben Skeggs
81eaff44c4 nouveau: NV4c ctx ucode. 
Seems we already have a nv4c_ctx_init() somehow, a quick check shows the
ucode matches it still.
 2007-08-22 13:09:27 +10:00
Ben Skeggs
ae883c97ad nouveau/nv50: Correct thinko for 8800 chips + cleanup a bit. 2007-08-22 12:54:26 +10:00
Stephane Marchesin
c8ee6a6cab nouveau: redo nv30_graph.c. Should work better, but we still lack a couple of cards. 2007-08-22 04:20:50 +02:00
Stephane Marchesin
76337bdb19 nouveau: fix the comment and debug message for PCIGART size 2007-08-22 04:20:50 +02:00
Ben Skeggs
03c0490129 nouveau: Add NV44 ctx ucode. Patch from stillunknown. 
Microcode is similar enough to the NV4A one that it should be able to use
the same initial PGRAPH context.  One day this mess will go away, honest..
 2007-08-21 02:23:21 +10:00
Ben Skeggs
216f1b0573 nouveau: Poke 0x2230 on NV47 also. 
Makes 0x2220 work the same way as on NV40.
 2007-08-21 02:18:27 +10:00
Patrice Mandin
c8760c7999 Check also for Linux, as it's not supported on different OS 2007-08-19 18:45:01 +02:00
Patrice Mandin
a122e7dabf Function pci_get_bus_and_slot needs 2.6.19 or later 2007-08-19 18:41:18 +02:00
Eric Anholt
0055fd5c35 Merge branch 'master' into bo-set-pin 2007-08-16 09:23:09 -07:00
Ben Skeggs
8a4d7f34d9 nouveau: Detect memory on NFORCE/NFORCE2 correctly. 2007-08-17 01:12:46 +10:00
Ben Skeggs
10f9b7bd0b nouveau: Use count parameter in nouveau_notifier_alloc(). 2007-08-15 14:14:23 +10:00
Ben Skeggs
a615d2fde7 nouveau: Turn some messages into DRM_DEBUGs.. 2007-08-15 14:01:35 +10:00
Ben Skeggs
c3faa589b0 nouveau: Allow GART notifiers when using sgdma code. 2007-08-15 13:36:54 +10:00
Ben Skeggs
ee01d3755a nouveau: Workaround mysterious PRAMIN clobbering by the card. 2007-08-15 13:34:57 +10:00
Ian Romanick
f563a50d14 Eliminate unused / useless ioctls. 2007-08-14 13:44:51 -07:00
Ben Skeggs
a6ea60c77e nouveau: Catch all NV4x chips instead of just NV_40. 2007-08-15 01:40:46 +10:00
Ben Skeggs
02c4e0e757 nouveau/nv40: Fix channel scheduling. 
Ensure NV_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLE gets set, otherwise channels
will appear to "freeze" in some circumstances.
 2007-08-15 01:04:41 +10:00
Dave Airlie
da27986870 i915: i965 non-secure batchbuffer bit has moved. 2007-08-11 08:57:53 +10:00
Ben Skeggs
a46104674f nouveau/nv50: demagic instmem setup. 2007-08-10 14:22:50 +10:00
Ben Skeggs
39907f613b nouveau: Allow creation of gpuobjs before any other init has taken place. 2007-08-10 13:53:10 +10:00
Ian Romanick
aea6b4dea9 Unify alloc and free ioctls. 
The DRM_XGI_PCIE_ALLOC and DRM_XGI_FB_ALLOC ioctls (and the matching
free ioctls) are unified to DRM_XGI_ALLOC.  The desired memory region
is selected by xgi_mem_alloc::location.  The region is magically
encoded in xgi_mem_alloc::index, which is used to release the memory.

Bump to version 0.11.0.  This update requires a new DDX.
 2007-08-09 15:30:36 -07:00
Ben Skeggs
7784e8c6e7 nouveau: silence irq handler a bit 2007-08-09 11:12:13 +10:00
Ben Skeggs
7281463f8d nouveau/nv40: add some missing pciids. 2007-08-09 10:23:36 +10:00
Matthieu Castet
e326acf549 nouveau : nv10, nv20, nv30 : don't save all channel in the same RAMFC entry 
This should improve multi fifo
 2007-08-08 22:55:32 +02:00
Ben Skeggs
05633ca370 nouveau: Always allocate drm's push buffer in VRAM 
Fixes #11868
 2007-08-08 16:37:55 +10:00
Ben Skeggs
40f2156356 nouveau: return channel id 2007-08-08 16:12:19 +10:00
Ben Skeggs
296050eee6 nouveau/nv50: hack up initial channel context from current state 
We really should be providing static values like the nv40 PGRAPH code does,
however, this will do for now to keep X at least working.
 2007-08-08 13:01:29 +10:00
Ben Skeggs
4ad487190d nouveau: enable/disable engine-specific interrupts in _init()/_takedown() 
All interrupts are still masked by PMC until init is finished.
 2007-08-08 10:49:05 +10:00
Matthieu Castet
a4759b8513 nouveau : fix enable irq (in the previous code all irq were masked by engine 
init after irq_postinstall)
 2007-08-07 23:09:44 +02:00
Ben Skeggs
66f5232d93 nouveau: Init global gpuobj list early, unbreaks sgdma code. 2007-08-07 01:52:49 +10:00
Stephane Marchesin
ac24f328ec nouveau: Bump PCI GART to 16MB 2007-08-06 17:16:05 +02:00
Ben Skeggs
8d5a8ebc31 nouveau: ouch, add nouveau_dma.[ch] files.. 2007-08-06 22:32:36 +10:00
Ben Skeggs
7a0a812ea4 nouveau: Remove PGRAPH_SURFACE hack, it wont work now anyway. 
Need to find another way of doing this, ideally someone'd hunt down which
object/method controls it!  The Xv blit adaptor is likely now broken on
cards that have pNv->WaitVSyncPossible enabled.
 2007-08-06 22:09:15 +10:00
Ben Skeggs
cf04641bc6 nouveau: Give DRM its own gpu channel 
If your card doesn't have working context switching, it is now broken.
 2007-08-06 22:05:31 +10:00
Ben Skeggs
51f24be578 nouveau: Determine trapped channel id from active grctx on >=NV40 2007-08-06 21:46:55 +10:00
Ben Skeggs
97770db720 nouveau: Various internal and external API changes 
1. DRM_NOUVEAU_GPUOBJ_FREE
	Used to free GPU objects.  The obvious usage case is for Gr objects,
	but notifiers can also be destroyed in the same way.

	GPU objects gain a destructor method and private data fields with
	this change, so other specialised cases (like notifiers) can be
	implemented on top of gpuobjs.

2. DRM_NOUVEAU_CHANNEL_FREE

3. DRM_NOUVEAU_CARD_INIT
	Ideally we'd do init during module load, but this isn't currently
	possible.  Doing init during firstopen() is bad as X has a love of
	opening/closing the DRM many times during startup.  Once the
	modesetting-101 branch is merged this can go away.

	IRQs are enabled in nouveau_card_init() now, rather than having the
	X server call drmCtlInstHandler().  We'll need this for when we give
	the kernel module its own channel.

4. DRM_NOUVEAU_GETPARAM
	Add CHIPSET_ID value, which will return the chipset id derived
	from NV_PMC_BOOT_0.

4. Use list_* in a few places, rather than home-brewed stuff.
 2007-08-06 21:45:18 +10:00