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nouveau: name some regs

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This commit is contained in:
Ben Skeggs 2007-06-25 03:52:06 +10:00
parent ce0d528d3c
commit 38617b6a26
3 changed files with 38 additions and 16 deletions
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15
shared-core/nouveau_reg.h
View file

@ -135,6 +135,17 @@
#define NV10_PGRAPH_CTX_CACHE4 0x004001C0
#define NV04_PGRAPH_CTX_CACHE4 0x004001E0
#define NV10_PGRAPH_CTX_CACHE5 0x004001E0
#define NV40_PGRAPH_CTXCTL_0304 0x00400304
#define NV40_PGRAPH_CTXCTL_0304_XFER_CTX 0x00000001
#define NV40_PGRAPH_CTXCTL_0310 0x00400310
#define NV40_PGRAPH_CTXCTL_0310_XFER_SAVE 0x00000020
#define NV40_PGRAPH_CTXCTL_0310_XFER_LOAD 0x00000040
#define NV40_PGRAPH_CTXCTL_030C 0x0040030c
#define NV40_PGRAPH_CTXCTL_UCODE_INDEX 0x00400324
#define NV40_PGRAPH_CTXCTL_UCODE_DATA 0x00400328
#define NV40_PGRAPH_CTXCTL_CUR 0x0040032c
#define NV40_PGRAPH_CTXCTL_CUR_LOADED 0x01000000
#define NV40_PGRAPH_CTXCTL_CUR_INST_MASK 0x000FFFFF
#define NV03_PGRAPH_ABS_X_RAM 0x00400400
#define NV03_PGRAPH_ABS_Y_RAM 0x00400480
#define NV03_PGRAPH_X_MISC 0x00400500
@ -230,7 +241,11 @@
#define NV10_PGRAPH_SCALED_FORMAT 0x00400778
#define NV10_PGRAPH_CHANNEL_CTX_TABLE 0x00400780
#define NV10_PGRAPH_CHANNEL_CTX_SIZE 0x00400784
#define NV20_PGRAPH_CHANNEL_CTX_POINTER 0x00400784
#define NV10_PGRAPH_CHANNEL_CTX_POINTER 0x00400788
#define NV20_PGRAPH_CHANNEL_CTX_XFER 0x00400788
#define NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD 0x00000001
#define NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE 0x00000002
#define NV04_PGRAPH_PATT_COLOR0 0x00400800
#define NV04_PGRAPH_PATT_COLOR1 0x00400804
#define NV04_PGRAPH_PATTERN 0x00400808

10
shared-core/nv30_graph.c
View file

@ -174,8 +174,9 @@ int nv30_graph_load_context(drm_device_t *dev, int channel)
return DRM_ERR(EINVAL);
inst = nouveau_chip_instance_get(dev, chan->ramin_grctx);
NV_WRITE(0x400784, inst);
NV_WRITE(0x400788, 1);
NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_XFER,
NV20_PGRAPH_CHANNEL_CTX_XFER_LOAD);
return nouveau_graph_wait_idle(dev);
}
@ -190,8 +191,9 @@ int nv30_graph_save_context(drm_device_t *dev, int channel)
return DRM_ERR(EINVAL);
inst = nouveau_chip_instance_get(dev, chan->ramin_grctx);
NV_WRITE(0x400784, inst);
NV_WRITE(0x400788, 2);
NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_XFER,
NV20_PGRAPH_CHANNEL_CTX_XFER_SAVE);
return nouveau_graph_wait_idle(dev);
}

29
shared-core/nv40_graph.c
View file

@ -1304,20 +1304,23 @@ nv40_graph_transfer_context(drm_device_t *dev, uint32_t inst, int save)
uint32_t old_cp, tv = 1000;
int i;
old_cp = NV_READ(0x400784);
NV_WRITE(0x400784, inst);
NV_WRITE(0x400310, save ? 0x20 : 0x40);
NV_WRITE(0x400304, 1);
old_cp = NV_READ(NV20_PGRAPH_CHANNEL_CTX_POINTER);
NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
NV_WRITE(NV40_PGRAPH_CTXCTL_0310,
save ? NV40_PGRAPH_CTXCTL_0310_XFER_SAVE :
NV40_PGRAPH_CTXCTL_0310_XFER_LOAD);
NV_WRITE(NV40_PGRAPH_CTXCTL_0304, NV40_PGRAPH_CTXCTL_0304_XFER_CTX);
for (i = 0; i < tv; i++) {
if (NV_READ(0x40030c) == 0)
if (NV_READ(NV40_PGRAPH_CTXCTL_030C) == 0)
break;
}
NV_WRITE(0x400784, old_cp);
NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, old_cp);
if (i == tv) {
DRM_ERROR("failed: inst=0x%08x save=%d\n", inst, save);
DRM_ERROR("0x40030C = 0x%08x\n", NV_READ(0x40030c));
DRM_ERROR("0x40030C = 0x%08x\n",
NV_READ(NV40_PGRAPH_CTXCTL_030C));
return DRM_ERR(EBUSY);
}
@ -1365,8 +1368,10 @@ nv40_graph_load_context(drm_device_t *dev, int channel)
* unknown as to what bit 24 does. The nv ddx has it set, so we will
* set it here too.
*/
NV_WRITE(0x400784, inst);
NV_WRITE(0x40032C, inst | 0x01000000);
NV_WRITE(NV20_PGRAPH_CHANNEL_CTX_POINTER, inst);
NV_WRITE(NV40_PGRAPH_CTXCTL_CUR,
(inst & NV40_PGRAPH_CTXCTL_CUR_INST_MASK) |
NV40_PGRAPH_CTXCTL_CUR_LOADED);
/* 0x32E0 records the instance address of the active FIFO's PGRAPH
* context. If at any time this doesn't match 0x40032C, you will
* recieve PGRAPH_INTR_CONTEXT_SWITCH
@ -1631,15 +1636,15 @@ nv40_graph_init(drm_device_t *dev)
DRM_DEBUG("Loading context-switch voodoo\n");
i = 0;
NV_WRITE(0x400324, 0);
NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_INDEX, 0);
while (ctx_voodoo[i] != ~0) {
NV_WRITE(0x400328, ctx_voodoo[i]);
NV_WRITE(NV40_PGRAPH_CTXCTL_UCODE_DATA, ctx_voodoo[i]);
i++;
}
}
/* No context present currently */
NV_WRITE(0x40032C, 0x00000000);
NV_WRITE(NV40_PGRAPH_CTXCTL_CUR, 0x00000000);
NV_WRITE(NV03_PGRAPH_INTR_EN, 0x00000000);
NV_WRITE(NV03_PGRAPH_INTR , 0xFFFFFFFF);