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nouveau/nv40: Fix channel scheduling.
Ensure NV_PFIFO_DMA_TIMESLICE_TIMEOUT_ENABLE gets set, otherwise channels will appear to "freeze" in some circumstances.
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3ee211f4f7
commit
02c4e0e757
3 changed files with 15 additions and 1 deletions
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@ -455,6 +455,7 @@ extern int nv10_fifo_load_context(struct nouveau_channel *);
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extern int nv10_fifo_save_context(struct nouveau_channel *);
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/* nv40_fifo.c */
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extern int nv40_fifo_init(struct drm_device *);
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extern int nv40_fifo_create_context(struct nouveau_channel *);
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extern void nv40_fifo_destroy_context(struct nouveau_channel *);
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extern int nv40_fifo_load_context(struct nouveau_channel *);
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@ -224,7 +224,7 @@ static int nouveau_init_engine_ptrs(struct drm_device *dev)
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engine->graph.destroy_context = nv40_graph_destroy_context;
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engine->graph.load_context = nv40_graph_load_context;
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engine->graph.save_context = nv40_graph_save_context;
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engine->fifo.init = nouveau_fifo_init;
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engine->fifo.init = nv40_fifo_init;
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engine->fifo.takedown = nouveau_stub_takedown;
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engine->fifo.create_context = nv40_fifo_create_context;
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engine->fifo.destroy_context = nv40_fifo_destroy_context;
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@ -193,3 +193,16 @@ nv40_fifo_save_context(struct nouveau_channel *chan)
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return 0;
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}
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int
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nv40_fifo_init(struct drm_device *dev)
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{
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struct drm_nouveau_private *dev_priv = dev->dev_private;
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int ret;
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if ((ret = nouveau_fifo_init(dev)))
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return ret;
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NV_WRITE(NV04_PFIFO_DMA_TIMESLICE, 0x2101ffff);
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return 0;
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}
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