being called without the BM enabled. Disabled the code in
RING_SPACE_TEST_WITH_RETURN which seems to be no longer necessary.
Slightly enhanced ADVANCE_RING by eliminating the need to mark DMA_EOL
in the current tail.
need for userspace clients to add HOSTDATA0 commands to blit buffers
every 16 dwords. However, it requires using BM_HOSTDATA rather than
BM_ADDR as the target register in the DMA descriptors for the blit
data. The first descriptor for a blit buffer sets up the state using
BM_ADDR. Both types of descriptor work with SRC_BM_OP_SYSTEM_TO_REG in
SRC_CNTL.
buffer, as well as the relevant registers. Added a few assertions to
make sure we aren't using trying to free used buffers. These checks are
guarded by MACH64_EXTRA_CHECKING to facilitate their future removal.
the lockups experienced in the NO_BATCH_DISPATCH code path. All other
code paths besides NO_BATCH_DISPATCH are broken. do_dma_flush waits for
completion of all DMA buffers and not just idle engine.
the ring as they are sent by the client (enabled with
MACH64_NO_BATCH_DISPATCH). For the "no batch dispatch" path:
- The DMA end of list flag is moved in the COMMIT_RING macro.
- The flush function only starts a new pass if the card has gone idle and
there are descriptors on the ring still unprocessed. This could be
better optimized to flush only when there is a large enough queue on
the card, but we'll always need to flush if we run out of freeable
buffers.
- This path is working up to a point, but lockups still occur. There is a
small performance improvement.
that it's possible to queue buffers while the engine is running. This
code was put instead on mach64_do_dma_idle so that the busmastering is
disabled when giving control to the X server.
registers for aging
- Disabled frame aging in the drm
- Disable save/restore pattern registers on context switch with DDX
- Move wait for DMA idle from EnterServer to XAA Sync.
- Clean up locking/sync macros in DDX
- Group scissor registers with UPLOAD_MISC in sarea to avoid confusion with
cliprects (mach64 doesn't have hardware cliprects, just the single
scissor).
done with the pattern registers which is not ideal, but works. There
are still lots of places where optimizing is needed. We need to do the
minimum required to sync with the X server on context switches, since
right now things slow down whenever the mouse is moved.
mach64-0-0-3-dma-branch)
- I've partly filled in the dma_dispatch implementation from the vertex
dispatch code. We still need to deal with adding a register reset
buffer to the end of the dma pass. The freelist and blits are also
still to be filled in.
- I've added XF86Config options for the driver: ForcePCIMode - Don't use
AGP for buffers/textures, even if agpgart is present PseudoDMAMode -
Dispatch DMA buffers with MMIO, one register at a time. AgpMode - 1 or
2 AgpSize - Size of AGP aperture to use for allocations BufferSize -
Size of vertex buffers in MB (1 or 2)
still be forced at compile time by setting MACH64_USE_DMA to 0.
DMA test now uses already allocated pci pool memory for descriptor table
and allocates a temporary dma buffer from the pool. This should
probabaly be changed to use one of our mapped vertex/dma buffers.
Also, return error code if _dispatch_vertex causes a lockup, either with
DMA (wait for idle fails) or MMIO (wait for fifo times out).
functional for both PCI and AGP). 16 KB descriptor table is created by
the drm and the handles stored in the device private structure.
Finish setup of AGP -- AGP registers are now initialized.
Fix up MMIO for PCI.
Implementation of several functions to support the handling of DMA
buffers. The DMA emulation code is disabled because it segfaults when
trying to read the DMA buffer.
