mirror of
https://gitlab.freedesktop.org/mesa/drm.git
synced 2026-05-09 08:38:23 +02:00
Fixed the bug which caused some lockups: UPDATE_RING_HEAD could (and was)
being called without the BM enabled. Disabled the code in
RING_SPACE_TEST_WITH_RETURN which seems to be no longer necessary.
Slightly enhanced ADVANCE_RING by eliminating the need to mark DMA_EOL
in the current tail.
This commit is contained in:
Jose Fonseca
parent
75d5b6bb0e
commit
95f92b7164
2 changed files with 44 additions and 55 deletions
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@ -1071,50 +1071,26 @@ static int mach64_do_dispatch_pseudo_dma( drm_mach64_private_t *dev_priv )
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#endif /* MACH64_NO_BATCH_DISPATCH */
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int mach64_dma_start( drm_mach64_private_t *dev_priv )
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void mach64_dma_start( drm_mach64_private_t *dev_priv )
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{
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#if MACH64_NO_BATCH_DISPATCH
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drm_mach64_descriptor_ring_t *ring = &dev_priv->ring;
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if ( (MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE) )
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return 0;
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if ( !(MACH64_READ(MACH64_SRC_CNTL) & MACH64_SRC_BM_ENABLE) ) {
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/* enable bus mastering and block 1 registers */
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MACH64_WRITE( MACH64_BUS_CNTL,
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( MACH64_READ(MACH64_BUS_CNTL) &
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~MACH64_BUS_MASTER_DIS )
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| MACH64_BUS_EXT_REG_EN );
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/* enable GUI-master operation */
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MACH64_WRITE( MACH64_SRC_CNTL,
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MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC |
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MACH64_SRC_BM_OP_SYSTEM_TO_REG );
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#if MACH64_EXTRA_CHECKING
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if ( (MACH64_READ(MACH64_SRC_CNTL) & MACH64_SRC_BM_ENABLE) ) {
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DRM_ERROR("Call of mach64_dma_start with BM enabled!!!\n");
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mach64_dump_ring( dev_priv );
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}
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if ( ring->head_addr < ring->start_addr ||
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ring->head_addr > ring->start_addr + (ring->size - 4 * sizeof(u32)) ) {
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DRM_ERROR("Bad address in BM_GUI_TABLE: 0x%08x\n", ring->head_addr);
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return -EINVAL;
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}
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UPDATE_RING_HEAD( dev_priv, ring );
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return 0;
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#else
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DRM_DEBUG("%s\n", __FUNCTION__);
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if (list_empty(&dev_priv->dma_queue))
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return 0;
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dev_priv->sarea_priv->dirty |= (MACH64_UPLOAD_CONTEXT |
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MACH64_UPLOAD_MISC);
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if (dev_priv->driver_mode == MACH64_MODE_MMIO)
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return mach64_do_dispatch_pseudo_dma( dev_priv );
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else
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return mach64_do_dispatch_real_dma( dev_priv );
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#endif
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mach64_do_wait_for_idle( dev_priv );
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/* enable bus mastering and block 1 registers */
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MACH64_WRITE( MACH64_BUS_CNTL,
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( MACH64_READ(MACH64_BUS_CNTL) &
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~MACH64_BUS_MASTER_DIS )
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| MACH64_BUS_EXT_REG_EN );
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/* enable GUI-master operation */
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MACH64_WRITE( MACH64_SRC_CNTL,
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MACH64_SRC_BM_ENABLE | MACH64_SRC_BM_SYNC |
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MACH64_SRC_BM_OP_SYSTEM_TO_REG );
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}
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/* IMPORTANT: This function should only be called when the engine is idle or locked up,
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@ -94,7 +94,7 @@ typedef struct drm_mach64_private {
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/* DMA descriptor table (ring buffer) */
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struct pci_pool *pool; /* DMA memory pool */
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drm_mach64_descriptor_ring_t ring;
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struct list_head free_list; /* Free-list head */
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struct list_head placeholders; /* Free-list placeholder list */
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struct list_head pending; /* Pending submission placeholder */
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@ -143,9 +143,10 @@ extern int mach64_do_wait_for_idle( drm_mach64_private_t *dev_priv );
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extern int mach64_wait_ring( drm_mach64_private_t *dev_priv, int n );
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extern int mach64_do_release_used_buffers( drm_mach64_private_t *dev_priv );
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extern void mach64_dump_engine_info( drm_mach64_private_t *dev_priv );
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extern void mach64_dump_ring( drm_mach64_private_t *dev_priv );
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extern int mach64_do_engine_reset( drm_mach64_private_t *dev_priv );
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extern int mach64_dma_start( drm_mach64_private_t *dev_priv );
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extern void mach64_dma_start( drm_mach64_private_t *dev_priv );
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extern int mach64_do_dma_idle( drm_mach64_private_t *dev_priv );
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extern int mach64_do_dma_flush( drm_mach64_private_t *dev_priv );
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@ -456,15 +457,25 @@ extern int mach64_dma_blit( struct inode *inode, struct file *filp,
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#define UPDATE_RING_HEAD( dev_priv, ring ) \
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do { \
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int gui_active = MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE; \
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int gui_active; \
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/* Start BM if it's not already on */ \
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/* FIXME: This should be done with a private variable to avoid using the BUS. */ \
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if ( !(MACH64_READ(MACH64_SRC_CNTL) & MACH64_SRC_BM_ENABLE) ) \
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mach64_dma_start( dev_priv ); \
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/* GUI_ACTIVE must be read before BM_GUI_TABLE to correctly determine the ring head */ \
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gui_active = MACH64_READ(MACH64_GUI_STAT) & MACH64_GUI_ACTIVE; \
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(ring)->head_addr = (MACH64_READ(MACH64_BM_GUI_TABLE) & 0xfffffff0); \
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if ( gui_active ) { \
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/* If not idle, BM_GUI_TABLE points one descriptor past the current head */ \
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if ((ring)->head_addr == (ring)->start_addr) \
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(ring)->head_addr += (ring)->size - 4 * sizeof(u32); \
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else \
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(ring)->head_addr -= 4 * sizeof(u32); \
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(ring)->head_addr += (ring)->size; \
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(ring)->head_addr -= 4 * sizeof(u32); \
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} \
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if ( MACH64_EXTRA_CHECKING && ((ring)->head_addr < (ring)->start_addr || \
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(ring)->head_addr >= (ring)->start_addr + (ring)->size ) ) { \
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DRM_ERROR("Bad address in BM_GUI_TABLE: 0x%08x\n", (ring)->head_addr); \
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mach64_dump_ring( dev_priv ); \
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} else { \
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(ring)->head = ((ring)->head_addr - (ring)->start_addr) / sizeof(u32); \
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if ( !gui_active && (ring)->head != (ring)->tail ) { \
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/* reset descriptor table ring head */ \
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@ -476,6 +487,7 @@ do { \
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__FUNCTION__, \
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(ring)->head_addr, (ring)->head, (ring)->tail, (ring)->space); \
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} \
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} \
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} while (0)
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static inline void
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@ -523,7 +535,10 @@ do { \
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/* Check for high water mark and flush if reached */
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/* FIXME: right now this is needed to ensure free buffers for state emits */
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#define RING_SPACE_TEST_WITH_RETURN( dev_priv ) \
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/* CHECKME: I've disabled this as it isn't necessary - we already wait for free buffers */
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#define RING_SPACE_TEST_WITH_RETURN( dev_priv )
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#define RING_SPACE_TEST_WITH_RETURN_( dev_priv ) \
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do { \
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struct list_head *ptr; \
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int ret, queued = 0; \
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@ -626,11 +641,11 @@ do { \
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DRM_INFO( "ADVANCE_RING() wr=0x%06x tail=0x%06x\n", \
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write, tail ); \
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} \
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ring[(write - 2) & mask] |= cpu_to_le32( DMA_EOL ); \
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wmb(); \
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mach64_flush_write_combine(); \
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ring[(tail - 2) & mask] &= cpu_to_le32( ~DMA_EOL ); \
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wmb(); \
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mach64_flush_write_combine(); \
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dev_priv->ring.tail = write; \
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UPDATE_RING_HEAD( dev_priv, &(dev_priv)->ring ); \
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} while (0)
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@ -735,11 +750,10 @@ do { \
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\
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OUT_RING( APERTURE_OFFSET + MACH64_BM_ADDR ); \
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OUT_RING( page ); \
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OUT_RING( remainder | DMA_HOLD_OFFSET ); \
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OUT_RING( remainder | DMA_HOLD_OFFSET | DMA_EOL ); \
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OUT_RING( 0 ); \
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\
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ADVANCE_RING(); \
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mach64_dma_start( dev_priv ); \
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} while(0)
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#define DMAADVANCEHOSTDATA( dev_priv ) \
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@ -807,11 +821,10 @@ do { \
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\
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OUT_RING( APERTURE_OFFSET + MACH64_BM_HOSTDATA ); \
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OUT_RING( page ); \
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OUT_RING( remainder | DMA_HOLD_OFFSET ); \
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OUT_RING( remainder | DMA_HOLD_OFFSET | DMA_EOL ); \
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OUT_RING( 0 ); \
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\
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ADVANCE_RING(); \
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mach64_dma_start( dev_priv ); \
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} while(0)
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#endif /* __MACH64_DRV_H__ */
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