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Add agp texture region info to DRM. Also, use DMA* macros for DRM

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emit_state functions. This ensures a wait_for_fifo for the MMIO writes.
This commit is contained in:
Leif Delgass 2002-04-20 20:11:08 +00:00
parent f080c751f3
commit bd00770298
4 changed files with 51 additions and 25 deletions
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20
linux/mach64_dma.c
View file

@ -155,21 +155,21 @@ static int mach64_do_dma_init( drm_device_t *dev, drm_mach64_init_t *init )
break;
}
}
if(!dev_priv->sarea) {
if (!dev_priv->sarea) {
dev->dev_private = (void *)dev_priv;
mach64_do_cleanup_dma(dev);
DRM_ERROR("can not find sarea!\n");
return -EINVAL;
}
DRM_FIND_MAP( dev_priv->fb, init->fb_offset );
if(!dev_priv->fb) {
if (!dev_priv->fb) {
dev->dev_private = (void *)dev_priv;
mach64_do_cleanup_dma(dev);
DRM_ERROR("can not find frame buffer map!\n");
return -EINVAL;
}
DRM_FIND_MAP( dev_priv->mmio, init->mmio_offset );
if(!dev_priv->mmio) {
if (!dev_priv->mmio) {
dev->dev_private = (void *)dev_priv;
mach64_do_cleanup_dma(dev);
DRM_ERROR("can not find mmio map!\n");
@ -182,20 +182,28 @@ static int mach64_do_dma_init( drm_device_t *dev, drm_mach64_init_t *init )
if( !dev_priv->is_pci ) {
DRM_FIND_MAP( dev_priv->buffers, init->buffers_offset );
if( !dev_priv->buffers ) {
if ( !dev_priv->buffers ) {
dev->dev_private = (void *)dev_priv;
mach64_do_cleanup_dma( dev );
DRM_ERROR( "can not find dma buffer map!\n" );
return -EINVAL;
}
DRM_IOREMAP( dev_priv->buffers );
if( !dev_priv->buffers->handle ) {
if ( !dev_priv->buffers->handle ) {
dev->dev_private = (void *) dev_priv;
mach64_do_cleanup_dma( dev );
DRM_ERROR( "can not ioremap virtual address for"
" dma buffer\n" );
return -ENOMEM;
}
DRM_FIND_MAP( dev_priv->agp_textures,
init->agp_textures_offset );
if (!dev_priv->agp_textures) {
dev->dev_private = (void *)dev_priv;
mach64_do_cleanup_dma( dev );
DRM_ERROR("could not find agp texture region!\n");
return -EINVAL;
}
}
tmp = MACH64_READ( MACH64_BUS_CNTL );
@ -220,7 +228,7 @@ int mach64_do_cleanup_dma( drm_device_t *dev )
if ( dev->dev_private ) {
drm_mach64_private_t *dev_priv = dev->dev_private;
if(dev_priv->buffers) {
if (dev_priv->buffers) {
DRM_IOREMAPFREE( dev_priv->buffers );
}
DRM(free)( dev_priv, sizeof(drm_mach64_private_t),

1
linux/mach64_drm.h
View file

@ -161,6 +161,7 @@ typedef struct drm_mach64_init {
unsigned int fb_offset;
unsigned int mmio_offset;
unsigned int buffers_offset;
unsigned int agp_textures_offset;
} drm_mach64_init_t;
typedef struct drm_mach64_clear {

1
linux/mach64_drv.h
View file

@ -50,6 +50,7 @@ typedef struct drm_mach64_private {
drm_map_t *fb;
drm_map_t *mmio;
drm_map_t *buffers;
drm_map_t *agp_textures;
} drm_mach64_private_t;
typedef struct drm_mach64_buf_priv {

54
linux/mach64_state.c
View file

@ -43,10 +43,16 @@ static inline void mach64_emit_texture( drm_mach64_private_t *dev_priv )
drm_mach64_context_regs_t *regs = &sarea_priv->context_state;
u32 offset = ((regs->tex_size_pitch & 0xf0) >> 2);
MACH64_WRITE( MACH64_TEX_SIZE_PITCH, regs->tex_size_pitch );
MACH64_WRITE( MACH64_TEX_CNTL, regs->tex_cntl );
MACH64_WRITE( MACH64_SECONDARY_TEX_OFF, regs->secondary_tex_off );
MACH64_WRITE( MACH64_TEX_0_OFF + offset, regs->tex_offset );
DMALOCALS;
DMAGETPTR( dev_priv, 4 );
DMAOUTREG( MACH64_TEX_SIZE_PITCH, regs->tex_size_pitch );
DMAOUTREG( MACH64_TEX_CNTL, regs->tex_cntl );
DMAOUTREG( MACH64_SECONDARY_TEX_OFF, regs->secondary_tex_off );
DMAOUTREG( MACH64_TEX_0_OFF + offset, regs->tex_offset );
DMAADVANCE( dev_priv );
}
static inline void mach64_emit_state( drm_mach64_private_t *dev_priv )
@ -55,58 +61,68 @@ static inline void mach64_emit_state( drm_mach64_private_t *dev_priv )
drm_mach64_context_regs_t *regs = &sarea_priv->context_state;
unsigned int dirty = sarea_priv->dirty;
DMALOCALS;
DRM_DEBUG( "%s: dirty=0x%08x\n", __FUNCTION__, dirty );
if ( dirty & MACH64_UPLOAD_MISC ) {
MACH64_WRITE( MACH64_DP_MIX, regs->dp_mix );
MACH64_WRITE( MACH64_DP_SRC, regs->dp_src );
MACH64_WRITE( MACH64_CLR_CMP_CNTL, regs->clr_cmp_cntl );
MACH64_WRITE( MACH64_GUI_TRAJ_CNTL, regs->gui_traj_cntl );
DMAGETPTR( dev_priv, 4 );
DMAOUTREG( MACH64_DP_MIX, regs->dp_mix );
DMAOUTREG( MACH64_DP_SRC, regs->dp_src );
DMAOUTREG( MACH64_CLR_CMP_CNTL, regs->clr_cmp_cntl );
DMAOUTREG( MACH64_GUI_TRAJ_CNTL, regs->gui_traj_cntl );
DMAADVANCE( dev_priv );
sarea_priv->dirty &= ~MACH64_UPLOAD_MISC;
}
DMAGETPTR( dev_priv, 9 );
if ( dirty & MACH64_UPLOAD_DST_OFF_PITCH ) {
MACH64_WRITE( MACH64_DST_OFF_PITCH, regs->dst_off_pitch );
DMAOUTREG( MACH64_DST_OFF_PITCH, regs->dst_off_pitch );
sarea_priv->dirty &= ~MACH64_UPLOAD_DST_OFF_PITCH;
}
if ( dirty & MACH64_UPLOAD_Z_OFF_PITCH ) {
MACH64_WRITE( MACH64_Z_OFF_PITCH, regs->z_off_pitch );
DMAOUTREG( MACH64_Z_OFF_PITCH, regs->z_off_pitch );
sarea_priv->dirty &= ~MACH64_UPLOAD_Z_OFF_PITCH;
}
if ( dirty & MACH64_UPLOAD_Z_ALPHA_CNTL ) {
MACH64_WRITE( MACH64_Z_CNTL, regs->z_cntl );
MACH64_WRITE( MACH64_ALPHA_TST_CNTL, regs->alpha_tst_cntl );
DMAOUTREG( MACH64_Z_CNTL, regs->z_cntl );
DMAOUTREG( MACH64_ALPHA_TST_CNTL, regs->alpha_tst_cntl );
sarea_priv->dirty &= ~MACH64_UPLOAD_Z_ALPHA_CNTL;
}
if ( dirty & MACH64_UPLOAD_SCALE_3D_CNTL ) {
MACH64_WRITE( MACH64_SCALE_3D_CNTL, regs->scale_3d_cntl );
DMAOUTREG( MACH64_SCALE_3D_CNTL, regs->scale_3d_cntl );
sarea_priv->dirty &= ~MACH64_UPLOAD_SCALE_3D_CNTL;
}
if ( dirty & MACH64_UPLOAD_DP_FOG_CLR ) {
MACH64_WRITE( MACH64_DP_FOG_CLR, regs->dp_fog_clr );
DMAOUTREG( MACH64_DP_FOG_CLR, regs->dp_fog_clr );
sarea_priv->dirty &= ~MACH64_UPLOAD_DP_FOG_CLR;
}
if ( dirty & MACH64_UPLOAD_DP_WRITE_MASK ) {
MACH64_WRITE( MACH64_DP_WRITE_MASK, regs->dp_write_mask );
DMAOUTREG( MACH64_DP_WRITE_MASK, regs->dp_write_mask );
sarea_priv->dirty &= ~MACH64_UPLOAD_DP_WRITE_MASK;
}
if ( dirty & MACH64_UPLOAD_DP_PIX_WIDTH ) {
MACH64_WRITE( MACH64_DP_PIX_WIDTH, regs->dp_pix_width );
DMAOUTREG( MACH64_DP_PIX_WIDTH, regs->dp_pix_width );
sarea_priv->dirty &= ~MACH64_UPLOAD_DP_PIX_WIDTH;
}
if ( dirty & MACH64_UPLOAD_SETUP_CNTL ) {
MACH64_WRITE( MACH64_SETUP_CNTL, regs->setup_cntl );
DMAOUTREG( MACH64_SETUP_CNTL, regs->setup_cntl );
sarea_priv->dirty &= ~MACH64_UPLOAD_SETUP_CNTL;
}
DMAADVANCE( dev_priv );
if ( dirty & MACH64_UPLOAD_TEXTURE ) {
mach64_emit_texture( dev_priv );
sarea_priv->dirty &= ~MACH64_UPLOAD_TEXTURE;
}
if ( dirty & MACH64_UPLOAD_CLIPRECTS ) {
MACH64_WRITE( MACH64_SC_LEFT_RIGHT, regs->sc_left_right );
MACH64_WRITE( MACH64_SC_TOP_BOTTOM, regs->sc_top_bottom );
DMAGETPTR( dev_priv, 2 );
DMAOUTREG( MACH64_SC_LEFT_RIGHT, regs->sc_left_right );
DMAOUTREG( MACH64_SC_TOP_BOTTOM, regs->sc_top_bottom );
DMAADVANCE( dev_priv );
sarea_priv->dirty &= ~MACH64_UPLOAD_CLIPRECTS;
}