mesa/src/intel/compiler
Lionel Landwerlin ff57c31696
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brw: avoid invalid URB messages
Some new CTS tests have geometry shader looking like this :

   void main()
   {
      gl_Position = gl_in[0].gl_Position;
      EmitVertex();
      EndPrimitive();
      // <-- some storage buffer write
   }

The generate shader has :
   - a message to write the position
   - a message to write to the storage buffer
   - a final message to end the thread

This generates an empty EOT URB messages which is apparently not legal
(simulation complains, HW hangs) :

send(8)         nullUD          g126UD          nullUD          0x04088007                0x00000000
                urb MsgDesc: offset 0 SIMD8 write masked  mlen 2 ex_mlen 0 rlen 0 { align1 1Q A@1 EOT };

Instead emit a write with actual data and the mask set at 0 to discard
the effect :

mov(8)          g127<1>UD       0x00000000UD                    { align1 WE_all 1Q };
mov(8)          g125<1>UD       0x00000000UD                    { align1 1Q };
send(8)         nullUD          g126UD          g125UD          0x04088007                0x00000040
                urb MsgDesc: offset 0 SIMD8 write masked  mlen 2 ex_mlen 1 rlen 0 { align1 1Q A@1 EOT };

Signed-off-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Cc: mesa-stable
Reviewed-by: Ian Romanick <ian.d.romanick@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/38243>
2025-11-05 17:18:09 +00:00
..
brw brw: avoid invalid URB messages 2025-11-05 17:18:09 +00:00
elk elk: Disable IO semantic validation when remapping patch offsets 2025-11-05 10:58:00 +00:00
brw_device_sha1_gen_c.py meson: remove '--outdir' argument in script 2025-10-08 20:51:20 +00:00
brw_list.h intel: fork exec_node/list -> brw_exec_node/list as a private Intel utility 2025-07-31 20:23:02 +00:00
intel_gfx_ver_enum.h build: avoid redefining unreachable() which is standard in C23 2025-07-31 17:49:42 +00:00
intel_nir.c intel/compiler: Use nir_split_conversions() 2025-04-07 17:45:21 -05:00
intel_nir.h brw: add support for separate tessellation shader compilation 2025-09-05 07:46:17 +00:00
intel_nir_blockify_uniform_loads.c intel/nir_blockify_uniform_loads: use helpers 2025-10-09 09:50:20 -04:00
intel_nir_clamp_image_1d_2d_array_sizes.c treewide: simplify nir_def_rewrite_uses_after 2025-08-01 15:34:24 +00:00
intel_nir_clamp_per_vertex_loads.c brw: add support for separate tessellation shader compilation 2025-09-05 07:46:17 +00:00
intel_nir_lower_non_uniform_barycentric_at_sample.c treewide: use nir_def_as_* 2025-08-01 15:34:24 +00:00
intel_nir_lower_non_uniform_resource_intel.c util/dynarray: infer type in append 2025-10-24 18:32:07 +00:00
intel_nir_lower_printf.c intel: Move intel_shader_reloc to common code and drop elk_shader_reloc 2025-10-09 07:01:46 +00:00
intel_nir_lower_shading_rate_output.c treewide: simplify nir_def_rewrite_uses_after 2025-08-01 15:34:24 +00:00
intel_nir_lower_sparse.c treewide: simplify nir_def_rewrite_uses_after 2025-08-01 15:34:24 +00:00
intel_nir_opt_peephole_ffma.c intel/nir: Make ffma peephole optimization preserve fp_fast_math flags 2025-09-30 19:44:02 +00:00
intel_nir_opt_peephole_imul32x16.c nir: remove unsigned upper bound config 2025-09-16 09:24:04 +00:00
intel_nir_tcs_workarounds.c nir: make nir_block::predecessors & dom_frontier sets non-malloc'd 2025-08-21 06:13:48 +00:00
intel_prim.h intel: Re-unify brw_prim.h and elk_prim.h 2025-10-09 07:01:46 +00:00
intel_shader_enums.h intel: Move intel_shader_reloc to common code and drop elk_shader_reloc 2025-10-09 07:01:46 +00:00
meson.build brw: Move into a new src/intel/compiler/brw subdirectory 2025-10-09 07:01:47 +00:00