Samuel Pitoiset fbcc4565c1 radv: fix a perf issue when clearing depth/stencil images on GFX12 ... Clearing on graphics updates HiZ correctly and expanding it always after the clear might hurt because it means HiZ will be disabled. This probably helps performance with the full GFX12 HiZ WA. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/40176>		2026-03-23 15:33:26 +00:00
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addrlib	amd/addrlib: Add more GFX1013 GPUs	2026-03-16 09:40:41 +00:00
ci	radv/ci: update restricted trace checksum	2026-03-19 07:41:30 +00:00
common	ac/cmdbuf: add an assertion for COPY_DATA+PFP with registers	2026-03-23 08:40:22 +00:00
compiler	aco: drop optimizer peephole TODO comment	2026-03-23 11:03:59 +00:00
drm-shim	amd/drm-shim: enable conformant_trunc_coord for navi31	2026-03-17 10:27:07 +00:00
gmlib	meson: Relax -Wmaybe-uninitialized errors	2025-09-16 06:16:20 +00:00
lanczoslib	meson: Relax -Wmaybe-uninitialized errors	2025-09-16 06:16:20 +00:00
llvm	nir: change export_amd intrinsics to use target instead of base	2026-03-23 06:10:49 +00:00
packets	amd: generate a packet parser/printer automatically from packet definitions	2026-03-11 18:54:20 +00:00
registers	amd: Rename GFX1103_R1/R2 to PHOENIX/2	2024-11-20 02:14:40 +00:00
vpelib	amd/vpelib: Apply external CSC	2026-03-04 13:17:26 +08:00
vulkan	radv: fix a perf issue when clearing depth/stencil images on GFX12	2026-03-23 15:33:26 +00:00
meson.build	radv/tests: require drm-shim and use it instead of RADV_FORCE_FAMILY	2025-11-19 07:11:05 +00:00