Jose Maria Casanova Crespo ec15373268 broadcom/compiler: really enable branch in delay slots validation ... The validation of branch instructions happening in branch and thrsw delay slots has been dead code since it was introduced as the check was after: if (inst->type != V3D_QPU_INSTR_TYPE_ALU) return; Now last_branch_ip is updated and checks in_branch_delay_slots() are active. Fixes in_branch_delay_slots, as for branch there are always 3 delay slots. As scheduler enforces this restrictions shader-db does not show any regression. Assisted-by: Claude Opus 4.6 Fixes: 90269ba353 ("broadcom/vc5: Use THRSW to enable multi-threaded shaders.") Reviewed-by: Iago Toral Quiroga <itoral@igalia.com> (cherry picked from commit dd6e7c8ef0) Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/41269>		2026-04-29 17:54:41 +02:00
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ci	vc4: fix unwanted buffer release on uploader	2026-04-01 11:45:35 +02:00
cle	broadcom/cle: bump up gen version for v3d	2026-02-04 18:39:35 +01:00
clif	build: avoid redefining unreachable() which is standard in C23	2025-07-31 17:49:42 +00:00
common	broadcom/common: fix V3D 7.1 TFU ICFG IFORMAT values	2026-04-01 11:45:33 +02:00
compiler	broadcom/compiler: really enable branch in delay slots validation	2026-04-29 17:54:41 +02:00
drm-shim	v3d/drm-shim: add support for multisync	2025-08-04 08:06:36 +02:00
ds	mesa: replace most occurrences of getenv() with os_get_option()	2025-11-06 04:36:13 +00:00
perfcntrs	broadcom: Add perfcount library	2024-12-02 14:13:24 +00:00
qpu	broadcom/compiler: enable umul24 and imul24 ALU opcodes	2025-11-26 13:32:39 +00:00
simulator	treewide: use UTIL_DYNARRAY_INIT	2025-11-04 13:39:48 +00:00
vulkan	v3dv: improve barrier handling for secondary command buffers	2026-01-21 07:37:49 +00:00
.editorconfig
meson.build	broadcom: Add perfetto data source	2024-12-13 12:29:11 +00:00