Samuel Pitoiset f7f6e9ad56 radv: always clear the SR0/SR1 bits of the HTILE buffer ... To make sure the stencil compare state is properly initialized and cleared when the driver performs a fast depth clear. Signed-off-by: Samuel Pitoiset <samuel.pitoiset@gmail.com> Reviewed-by: Bas Nieuwenhuizen <bas@basnieuwenhuizen.nl> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/8039>		2021-01-05 12:10:11 +00:00
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addrlib	amd/addrlib: use cpp.has_argument() to filter compiler arguments	2021-01-05 11:29:11 +00:00
common	ac,radeonsi: limit Smart Access Memory to Zen 3 and GFX10.3 due to perf issues	2021-01-05 02:43:55 +00:00
compiler	aco: fix incorrect address calculation for load_barycentric_at_sample	2021-01-04 16:53:29 +00:00
llvm	ac/nir: use llvm.readcyclecounter for LLVM9+	2021-01-05 10:27:00 +00:00
registers	amd/registers: add missing VRS registers	2020-12-14 16:22:38 +00:00
vulkan	radv: always clear the SR0/SR1 bits of the HTILE buffer	2021-01-05 12:10:11 +00:00
Android.addrlib.mk	android: amd/addrlib: add gfx10 support	2019-07-10 09:03:55 +02:00
Android.common.mk	android: amd/registers: switch to new generated register definitions	2020-09-06 20:20:34 +02:00
Android.compiler.mk	android: aco/isel: Move context initialization code to a dedicated file	2020-09-14 21:26:53 +02:00
Android.mk	android: aco: add support for libmesa_aco	2019-09-28 15:56:34 +02:00
Makefile.sources	android: aco: add aco_form_hard_clauses.cpp to Makefile.sources	2020-10-30 13:34:06 +00:00
meson.build	aco: add framework for unit testing	2020-07-30 16:13:08 +00:00