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fcf1a8062b
With the exception of some variants for framebuffer fetch (to be addressed in a follow up MR, this is big enough as it is) -- this switches us to a shader precompile path for VS & FS. VS prologs let us implement vertex buffer fetch with dynamic formats, FS prologs let us implement misc emulation like API sample masking and cull distance, while FS epilogs handle blending and tilebuffer stores. This should cut down shader recompile jank significantly in the GL driver. It also prepares us with most of what we need for big ticket Vulkan extensions like ESO, GPL, and EDS3. Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/28483> |
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| .. | ||
| test | ||
| agx_builder.h.py | ||
| agx_compile.c | ||
| agx_compile.h | ||
| agx_compiler.h | ||
| agx_dce.c | ||
| agx_debug.h | ||
| agx_insert_waits.c | ||
| agx_internal_formats.h | ||
| agx_ir.c | ||
| agx_liveness.c | ||
| agx_lower_64bit.c | ||
| agx_lower_parallel_copy.c | ||
| agx_lower_pseudo.c | ||
| agx_lower_spill.c | ||
| agx_lower_uniform_sources.c | ||
| agx_minifloat.h | ||
| agx_nir.h | ||
| agx_nir_algebraic.py | ||
| agx_nir_lower_address.c | ||
| agx_nir_lower_cull_distance.c | ||
| agx_nir_lower_discard_zs_emit.c | ||
| agx_nir_lower_frag_sidefx.c | ||
| agx_nir_lower_interpolation.c | ||
| agx_nir_lower_sample_mask.c | ||
| agx_nir_lower_shared_bitsize.c | ||
| agx_nir_lower_subgroups.c | ||
| agx_nir_opt_preamble.c | ||
| agx_opcodes.c.py | ||
| agx_opcodes.h.py | ||
| agx_opcodes.py | ||
| agx_opt_break_if.c | ||
| agx_opt_compact_constants.c | ||
| agx_opt_cse.c | ||
| agx_opt_empty_else.c | ||
| agx_opt_jmp_none.c | ||
| agx_opt_promote_constants.c | ||
| agx_optimizer.c | ||
| agx_pack.c | ||
| agx_performance.c | ||
| agx_pressure_schedule.c | ||
| agx_print.c | ||
| agx_register_allocate.c | ||
| agx_reindex_ssa.c | ||
| agx_repair_ssa.c | ||
| agx_spill.c | ||
| agx_validate.c | ||
| meson.build | ||
| README.md | ||
Special registers
r0l is the hardware nesting counter.
r1 is the hardware link register.
r5 and r6 are preloaded in vertex shaders to the vertex ID and instance ID.
ABI
The following section describes the ABI used by non-monolithic programs.
Vertex
Registers have the following layout at the beginning of the vertex shader (written by the vertex prolog):
r0-r4andr7undefined. This avoids preloading into the nesting counter or having unaligned values. The prolog is free to use these registers as temporaries.r5-r6retain their usual meanings, even if the vertex shader is running as a hardware compute shader. This allows software index fetch code to run in the prolog without contaminating the main shader key.r8onwards contains 128-bit uniform vectors for each attribute. Accommodates 30 attributes without spilling, exceeding the 16 attribute API minimum. For 32 attributes, we will need to use function calls or the stack.
One useful property is that the GPR usage of the combined program is equal to the GPR usage of the main shader. The prolog cannot write higher registers than read by the main shader.
Vertex prologs do not have any uniform registers allocated for preamble optimization or constant promotion, as this adds complexity without any legitimate use case.
For a vertex shader reading n attributes, the following layout is used:
- The first
n64-bit uniforms are the base addresses of each attribute. - The next
n32-bit uniforms are the associated clamps (sizes). Presently robustness is always used. - The next 32-bit uniform is the base instance. This must always be reserved because it is unknown at vertex shader compile-time whether any attribute will use instancing.
- For a hardware compute shader, the next 32-bit uniform is the base/first vertex.
- For a hardware compute shader, the next 64-bit uniform is a pointer to the input assembly buffer.
In total, the first 6n + 2 16-bit uniform slots are reserved for a hardware
vertex shader, or 6n + 8 for a hardware compute shader.
Fragment
When sample shading is enabled in a non-monolithic fragment shader, the fragment shader has the following register inputs:
r0l = 0. This is the hardware nesting counter.r0his the mask of samples currently being shaded. This usually equals to1 << sample ID, for "true" per-sample shading.
When sample shading is disabled, no register inputs are defined. The fragment prolog (if present) may clobber whatever registers it pleases.
Registers have the following layout at the end of the fragment shader (read by the fragment epilog):
r0l = 0if sample shading is enabled. This is implicitly true.r0hpreserved if sample shading is enabled.r2andr3lcontain the emitted depth/stencil respectively, if depth and/or stencil are written by the fragment shader. Depth/stencil writes must be deferred to the epilog for correctness when the epilog can discard (i.e. when alpha-to-coverage is enabled).- The vec4 of 32-bit registers beginning at
r(4 * (i + 1))contains the colour output for render targeti. When dual source blending is enabled, there is only a single render target and the dual source colour is treated as the second render target (registers r8-r11).
Uniform registers have the following layout:
- u0_u1: 64-bit render target texture heap
- u2...u5: Blend constant
- u6_u7: Root descriptor, so we can fetch the 64-bit fragment invocation counter address and (OpenGL only) the 64-bit polygon stipple address