Kenneth Graunke 873dfb673b anv: Perform load_constant address math in 32-bit rather than 64-bit ... We lower NIR's load_constant to load_global_constant, which uses A64 bindless messages. As such, we do the following math to produce the address for each load: base_lo@32 <- BRW_SHADER_RELOC_CONST_DATA_ADDR_LOW base_hi@32 <- BRW_SHADER_RELOC_CONST_DATA_ADDR_HIGH base@64 <- pack_64_2x32_split(base_lo, base_hi) addr@64 <- iadd(base@64, u2u64(offset@32)) On platforms that emulate 64-bit math, we have to emit additional code for the 64-bit iadd to handle the possibility of a carry happening and affecting the top bits. However, NIR constant data is always uploaded adjacent to the shader assembly, in the same buffer. These buffers are required to live in a 4GB region of memory starting at Instruction State Base Address. We always place the base address at a 4GB address. So the constant data always lives in a buffer entirely contained within a 4GB region, which means any offsets from the start of the buffer cannot possibly affect the high bits. So instead, we can simply do a 32-bit addition between the low bits of the base and the offset, then pack that with the unchanged high bits. On anv, INSTRUCTION_STATE_POOL_MIN_ADDRESS is 8GB, so the high bits are always 0x2. We don't even need to patch that portion of the address and can just use an immediate value. We do still need to pack, however. fossil-db on Icelake indicates the following for affected shaders: Instrs: 10830023 -> 10750080 (-0.74%) Cycles: 1048521282 -> 1046770379 (-0.17%); split: -0.33%, +0.16% Subgroup size: 103104 -> 103112 (+0.01%) Send messages: 570886 -> 570760 (-0.02%) Loop count: 14428 -> 14429 (+0.01%) Spill count: 14246 -> 14244 (-0.01%); split: -0.06%, +0.04% Fill count: 22802 -> 22794 (-0.04%); split: -0.04%, +0.01% Scratch Memory Size: 654336 -> 662528 (+1.25%) Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20999>		2023-02-02 02:45:04 +00:00
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blorp	intel: enable existing workaround for ICL platform	2023-02-01 11:09:19 +00:00
ci	anv: expose EXT_load_store_op_none	2023-02-01 12:53:29 +00:00
common	intel: add missing PS restriction on BDW+	2023-02-01 00:28:53 +00:00
compiler	intel/fs: Always stall between the fences on Gen11+	2023-02-02 00:21:21 +00:00
dev	intel/compiler: fine-grained control of dispatch widths	2023-01-27 11:00:41 +00:00
ds	intel/ds: Fix crash when allocating more intel_ds_queues than u_vector was initialized	2023-02-01 18:31:29 +00:00
genxml	intel/genxml: set unused 3DSTATE_PS_EXTRA field as mbz	2023-01-24 10:28:15 +00:00
isl	intel/isl: Disable CCS on MTL until B0 (Wa_14017353530)	2022-12-15 11:43:00 -08:00
nullhw-layer	utils: Merge util/debug.* into util/u_debug.* and remove util/debug.*	2022-11-02 07:25:39 +00:00
perf	intel: add MTL performance metrics	2022-12-09 09:13:02 +00:00
tools	anv,hasvk: migrate align32 to the right functions from util	2023-01-06 17:22:16 +00:00
vulkan	anv: Perform load_constant address math in 32-bit rather than 64-bit	2023-02-02 02:45:04 +00:00
vulkan_hasvk	intel/ds: Fix crash when allocating more intel_ds_queues than u_vector was initialized	2023-02-01 18:31:29 +00:00
meson.build	intel: Disable SSE2 instruction set if building for non x86 architectures	2022-11-23 16:57:23 +00:00