Lucas Stach 992e9d07c5 etnaviv: drm: fix instruction limit for cores with instruction cache ... Some cores with the the instruction cache feature, such as the GC3000 found on the i.MX6QP, have a wrong instruction limit encoded in hardware. The HWDB entry for this core has the correct number (512). Fixup all cores with the instruction cache feature to report at least 512 instructions, which was already assumed when configuring the VS/FS instruction state memory split in other parts of the driver. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33229>		2025-01-31 09:47:34 +00:00
..
tests	build: pass licensing information in SPDX form	2024-06-29 12:42:49 -07:00
etnaviv_bo.c	etnaviv: drm: assert mutual exclusivity between cache and zombie list	2024-11-20 13:08:28 +00:00
etnaviv_bo_cache.c	etnaviv: drm: use list_first_entry	2024-11-20 13:08:28 +00:00
etnaviv_cmd_stream.c	etnaviv: drm: don't skip flush when there are active PMRs	2024-07-08 08:11:47 +00:00
etnaviv_device.c
etnaviv_drmif.h	etnaviv: drm: Drop NPU-related params	2024-04-23 05:39:57 +00:00
etnaviv_gpu.c	etnaviv: drm: fix instruction limit for cores with instruction cache	2025-01-31 09:47:34 +00:00
etnaviv_perfmon.c
etnaviv_pipe.c
etnaviv_priv.h	etnaviv: drm: use COARSE clock for timeouts when possible	2024-07-30 14:35:19 +00:00
meson.build	format: Generate endian-independent format aliases	2024-07-19 13:50:42 +00:00