Lucas Stach 992e9d07c5 etnaviv: drm: fix instruction limit for cores with instruction cache ... Some cores with the the instruction cache feature, such as the GC3000 found on the i.MX6QP, have a wrong instruction limit encoded in hardware. The HWDB entry for this core has the correct number (512). Fixup all cores with the instruction cache feature to report at least 512 instructions, which was already assumed when configuring the VS/FS instruction state memory split in other parts of the driver. Signed-off-by: Lucas Stach <l.stach@pengutronix.de> Reviewed-by: Christian Gmeiner <cgmeiner@igalia.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/33229>		2025-01-31 09:47:34 +00:00
..
ci	etnaviv: always clamp shadow sampler comparison reference value	2025-01-28 00:01:07 +00:00
common	etnaviv: Add script to decode weights in Huffman format	2024-11-13 07:39:35 +00:00
drm	etnaviv: drm: fix instruction limit for cores with instruction cache	2025-01-31 09:47:34 +00:00
drm-shim	build: pass licensing information in SPDX form	2024-06-29 12:42:49 -07:00
hw	etnaviv: Update headers from rnndb	2025-01-08 13:55:26 +00:00
hwdb	etnaviv: hwdb: fix lookup of GC3000 in i.MX6QP	2025-01-26 20:32:04 +00:00
isa	etnaviv: isa: Support src2 for texldb and texldl	2025-01-08 07:57:39 +00:00
meson.build	build: pass licensing information in SPDX form	2024-06-29 12:42:49 -07:00