Benjamin Cheng dd20ec5655 radv/video: send h264 scaling list in raster order ... ITU spec defines the H264 ScalingList{4x4,8x8} in zig-zag order, but AMD HW wants raster order. Reviewed-by: Lynne <dev@lynne.ee> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/24572>		2023-08-25 03:08:13 +00:00
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addrlib	ac/radv: decouple radv vulkan driver and compiler from gallium	2023-08-03 09:45:42 +00:00
ci	ci: disable Material Testers.x86_64_2020.04.08_13.38_frame799.rdc trace	2023-08-21 22:31:21 +00:00
common	treewide: Use nir_shader_intrinsic_pass sometimes	2023-08-24 15:48:02 +00:00
compiler	aco: combine a | ~b to bfi(b, a, -1)	2023-08-23 20:06:49 +00:00
drm-shim	amd/drm-shim: use fixed-width types	2023-06-23 18:35:52 +00:00
llvm	ac: implement AMD_FORCE_FAMILY properly, remove SI_FORCE_FAMILY	2023-08-19 19:36:55 +00:00
registers	ac: change offsets of DMA_DATA dwords to prevent reg offset conflicts	2023-08-19 19:36:55 +00:00
vulkan	radv/video: send h264 scaling list in raster order	2023-08-25 03:08:13 +00:00
meson.build	meson: build radeonsi with aco	2023-05-15 02:01:10 +00:00