Francisco Jerez d622e19f00 intel/fs/xe2+: Enable new format of barycentrics in PS payload. ... The X and Y barycentric vectors are no longer interleaved in SIMD8 chunks (yay), so this is mostly a matter of disabling the lower_barycentrics() pass and switching to a simpler implementation of fetch_barycentric_reg() that simply calls fetch_payload_reg() instead of the SIMD8 shuffling we had to do in previous generations. Reviewed-by: Caio Oliveira <caio.oliveira@intel.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/26606>		2023-12-28 11:07:03 -08:00
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blorp	intel/compiler: Add max_polygons FS compilation parameter.	2023-12-22 18:05:30 +00:00
ci	ci: Remove per-driver wayland-dEQP-EGL xfails	2023-12-22 11:13:23 +00:00
common	intel/gfx12: Enable SIMD8 dispatch in 3DSTATE_PS for FS multipolygon dispatch.	2023-12-22 18:05:31 +00:00
compiler	intel/fs/xe2+: Enable new format of barycentrics in PS payload.	2023-12-28 11:07:03 -08:00
dev	intel: Add debug flag for enabling dual-SIMD8 fragment shader dispatch.	2023-12-22 18:05:31 +00:00
ds	intel/ds: add trace of buffer markers	2023-11-29 01:16:22 +00:00
genxml	intel/genxml: Add 3DSTATE_PS definitions needed for dual-SIMD8 dispatch on Gfx12+.	2023-12-22 18:05:31 +00:00
isl	intel/isl: Add Gfx 12.x RC_CCS_CC into modifier scores	2023-12-19 13:57:16 +00:00
nullhw-layer	meson: support installation tags	2023-09-11 13:00:45 +00:00
perf	intel: Remove unused ALIGN macro	2023-12-07 02:30:53 +00:00
tools	intel/tools: fix compilation of intel_hang_viewer on 32 bits	2023-12-08 22:53:03 +00:00
vulkan	anv: Assume that imported bos already have flat CCS requirements satisfied	2023-12-27 18:05:04 +00:00
vulkan_hasvk	anv/hasvk/drirc: change anv_assume_full_subgroups to have subgroup size	2023-12-15 05:28:51 +00:00
meson.build	intel: Only build perf if drivers or tools are enabled	2023-08-31 21:53:19 +00:00