Rhys Perry d0a09b6ff7 ac/llvm: correctly set alignment of vector global load/store ... For coherent/volatile access, this would be too high for vector access. Even when we didn't set the alignment, LLVM seemed to assume too high of an alignment for 8/16-bit vector access. Fixes generated_tests/cl/vload/vload-char-constant.cl Signed-off-by: Rhys Perry <pendingchaos02@gmail.com> Reviewed-by: Marek Olšák <marek.olsak@amd.com> Tested-by: Michel Dänzer <mdaenzer@redhat.com> Backport-to: 25.0 Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/34903>		2025-05-12 10:51:57 +00:00
..
addrlib	amd/addrlib: remove the DCC page fault workaround	2025-04-01 03:23:22 -04:00
ci	radv/ci: document flakes	2025-05-11 18:46:12 +00:00
common	ac/gpu_info: add has_zerovram_support	2025-05-12 06:53:55 +00:00
compiler	aco/insert_exec_mask: don't create unnecessary loop-header and -exit phis after demote	2025-05-09 17:20:29 +00:00
drm-shim	amd/drm-shim: add gfx1201	2025-03-10 11:21:36 +00:00
gmlib	amd/gmlib: add gmlib for radeonsi	2025-02-27 03:15:16 +00:00
llvm	ac/llvm: correctly set alignment of vector global load/store	2025-05-12 10:51:57 +00:00
registers	amd: Rename GFX1103_R1/R2 to PHOENIX/2	2024-11-20 02:14:40 +00:00
vpelib	amd/vpelib: More parameters to the segmentation process and introduce validation hook	2025-03-06 02:11:53 +00:00
vulkan	radv: ignore radv_zero_vram=true if zeroInitialDeviceMemory is enabled	2025-05-12 06:53:55 +00:00
meson.build	amd/gmlib: add gmlib for radeonsi	2025-02-27 03:15:16 +00:00