mirror of
https://gitlab.freedesktop.org/mesa/mesa.git
synced 2026-05-19 13:38:19 +02:00
This 2 PIPELINE_CONTROL flushes are not necessary for TGL and newer and also it have different requirements of flush, so here doing this two changes at the same time. As no ANV_PIPE_INVALIDATE_BITS is set as parameter of anv_add_pending_pipe_bits(), genX(cmd_buffer_apply_pipe_flushes)(cmd_buffer) will only emit one PIPELINE_CONTROL. BSpec: 44505 Signed-off-by: José Roberto de Souza <jose.souza@intel.com> Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com> Reviewed-by: Kenneth Graunke <kenneth@whitecape.org> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/20501> |
||
|---|---|---|
| .. | ||
| blorp | ||
| ci | ||
| common | ||
| compiler | ||
| dev | ||
| ds | ||
| genxml | ||
| isl | ||
| nullhw-layer | ||
| perf | ||
| tools | ||
| vulkan | ||
| vulkan_hasvk | ||
| meson.build | ||