mesa/src
Kenneth Graunke c46d3acf0e anv: Raise vertex input bindings and attributes limits slightly
This raises our vertex input bindings limit from 28 to 31, and our
vertex input attribute limit from 28 to 29.  We could theoretically
go higher, but it will take additional work.

The 3DSTATE_VERTEX_BUFFERS and 3DSTATE_VERTEX_ELEMENTS limits are 33
vertex buffers, and 34 vertex elements.  But we need up to two vertex
elements for system values (FirstVertex, BaseVertex, BaseInstance,
DrawID), and we currently use two vertex bindings for those.

There is another hidden limit: our compiler backend only supports the
push model for VS inputs currently.  3DSTATE_VS only allows URB Read
Lengths between [0, 15], which is measured in pairs of inputs, which
means we can theoretically push no more than 32 vertex elements.  This
is no artifical limit either, as a vec4 element takes up 4 registers
in the payload, and 32 * 4 = 128, the entire size of our register file.
Plus, the VS Thread payload needs at least g0 and g1 for other things,
so we can really only push 31.

We can theoretically support one additional binding, by combining our
two SGV bindings into a single upload.  In order to support additional
vertex elements, we would need to add support to the backend compiler
for the pull model for VS inputs.

References: https://gitlab.freedesktop.org/mesa/mesa/-/issues/5917
Reviewed-by: Lionel Landwerlin <lionel.g.landwerlin@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/14991>
2022-02-22 21:31:06 +00:00
..
amd ac/nir/ngg: Fix mixed up primitive ID after culling. 2022-02-22 18:15:24 +00:00
android_stub android_stub: update platform headers to include atrace 2021-10-09 00:42:32 +00:00
asahi asahi: Wire in pure integer texture formats 2022-02-18 23:48:33 +00:00
broadcom broadcom/compiler: fix register class patching for postponed spills 2022-02-22 11:17:10 +00:00
compiler nir/spirv: guard macros in case of redefinition 2022-02-21 19:47:17 +00:00
drm-shim
egl egl/wayland: Don't replace existing backbuffer in get_buffers 2022-02-07 09:57:41 +00:00
etnaviv etnaviv: add support for INTEL_blackhole_render 2022-01-31 16:52:29 +00:00
freedreno turnip: Request no implicit sync when we have no implicit-sync WSI BOs. 2022-02-22 17:36:05 +00:00
gallium zink: ci updates 2022-02-22 21:16:55 +00:00
gbm gbm: improve documentation about the lifetime of resources 2022-02-22 14:42:52 +01:00
getopt
glx glx: keep native window glx drawable by driconf option 2022-02-22 07:10:40 +00:00
gtest gtest: Fix output of array ASSERT/EXPECT macros 2021-11-11 09:53:09 -08:00
hgl
imgui
intel anv: Raise vertex input bindings and attributes limits slightly 2022-02-22 21:31:06 +00:00
loader gallium/dri: add missing PIPE_BIND_DRI_PRIME handling 2022-02-08 00:13:07 +00:00
mapi glthread: call _mesa_glthread_BindBuffer unconditionally 2022-02-01 06:11:22 +00:00
mesa mesa: Enable GL_NV_pack_subimage 2022-02-22 10:45:28 -05:00
microsoft nir: Add missing dependency on nir_opcodes.py 2022-02-17 22:57:33 +00:00
nouveau
panfrost pan/bi: Add BIFROST_MESA_DEBUG=nosb option 2022-02-22 16:57:30 +00:00
tool ci: Use a dlclose-disabling preload library for leak checking in Vulkan. 2022-01-27 23:47:46 +00:00
util driconf: add Abaqus configs 2022-02-22 07:10:40 +00:00
virtio vulkan/wsi: untangle buffer-images from prime 2022-02-22 10:04:34 +00:00
vulkan vulkan/wsi: use buffer-image code-path on Windows 2022-02-22 10:04:34 +00:00
meson.build meson: start building intel earlier. 2022-01-20 06:41:17 +00:00