fdo-mirrors/mesa
1
0
Fork 0
mirror of https://gitlab.freedesktop.org/mesa/mesa.git synced 2026-02-20 08:00:28 +01:00
Code Issues Projects Releases Packages Wiki Activity Actions 4

broadcom/compiler: fix register class patching for postponed spills

Browse source 
If we have a postponed spill, the temp we create at ip is no longer
the spilled temp and therefore is affected by the thrsw injection.

Fixes corruption in the additive blending animation demo from
Three.js.

Fixes: f3c3228522 ('broadcom/compiler: do not rebuild the interference graph after each spill')
Reviewed-by: Alejandro Piñeiro <apinheiro@igalia.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/15112>
This commit is contained in:
Iago Toral Quiroga 2022-02-22 10:27:00 +01:00 • committed by Marge Bot
parent 09b86b4061
commit c4a78a2d2a
1 changed files with 5 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

9
src/broadcom/compiler/vir_register_allocate.c
View file

@ -352,14 +352,15 @@ v3d_emit_spill_tmua(struct v3d_compile *c,
* is not affected by the thrsw. Something that ends at ip will be
* affected though.
*
* Spills inject code after ip, so anything that starts later than ip
* is not affected (and only the spilled temp starts at ip). Something
* that ends at ip won't be affected either.
* Spills inject code after ip, so anything that starts strictly later
* than ip is not affected (the temp starting at ip is usually the
* spilled temp except for postponed spills). Something that ends at ip
* won't be affected either.
*/
for (int i = 0; i < c->spill_start_num_temps; i++) {
bool thrsw_cross = fill_dst ?
c->temp_start[i] < ip && c->temp_end[i] >= ip :
c->temp_start[i] < ip && c->temp_end[i] > ip;
c->temp_start[i] <= ip && c->temp_end[i] > ip;
if (thrsw_cross) {
ra_set_node_class(c->g, c->ra_map.temp[i].node,
choose_reg_class(c, CLASS_BITS_PHYS));