mesa/src/intel
Francisco Jerez 0ad835a929 intel/fs/xe2: Fix up subdword integer region restriction with strided byte src and packed byte dst.
This fixes a corner case of the LNL sub-dword integer restrictions
that wasn't being detected by has_subdword_integer_region_restriction(),
specifically:

> if(Src.Type==Byte && Dst.Type==Byte && Dst.Stride==1 && W!=2) {
>    // ...
>    if(Src.Stride == 2) && (Src.UniformStride) && (Dst.SubReg%32  ==  Src.SubReg/2 ) { Allowed }
>    // ...
> }

All the other restrictions that require agreement between the SubReg
number of source and destination only affect sources with a stride
greater than a dword, which is why
has_subdword_integer_region_restriction() was returning false except
when "byte_stride(srcs[i]) >= 4" evaluated to true, but as implied by
the pseudocode above, in the particular case of a packed byte
destination, the restriction applies for source strides as narrow as
2B.

The form of the equation that relates the subreg numbers is consistent
with the existing calculations in brw_fs_lower_regioning (see
required_src_byte_offset()), we just need to enable lowering for this
corner case, and change lower_dst_region() to call lower_instruction()
recursively, since some of the cases where we break this restriction
are copy instructions introduced by brw_fs_lower_regioning() itself
trying to lower other instructions with byte destinations.

This fixes some Vulkan CTS test-cases that were hitting these
restrictions with byte data types.

Fixes: 217d412360 ("intel/fs/gfx20+: Implement sub-dword integer regioning restrictions.")
Reviewed-by: Caio Oliveira <caio.oliveira@intel.com>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/30630>
2024-11-15 07:39:33 +00:00
..
blorp intel: Switch to COMPUTE_WALKER_BODY 2024-10-29 15:54:43 +00:00
ci anv: Access more colors in fast_clear_memory_range 2024-10-28 17:43:21 +00:00
common intel: Avoid unaligned pointer access 2024-11-14 01:05:02 +00:00
compiler intel/fs/xe2: Fix up subdword integer region restriction with strided byte src and packed byte dst. 2024-11-15 07:39:33 +00:00
decoder intel/decoder: fix INTEL_DEBUG=bat 2024-11-13 00:45:40 +00:00
dev intel/dev: update mesa_defs.json from workaround database 2024-11-13 04:54:32 +00:00
ds intel/ds: add L3 fabric flush support 2024-10-08 08:45:40 +00:00
executor intel/executor: Fix exec_size in @read macro for Xe2 2024-11-14 05:31:03 +00:00
genxml anv: implement Wa_16011107343/22018402687 for generated draws 2024-11-12 22:48:39 +00:00
isl isl: modify existing assert by allowing CCS_E aux usage 2024-11-15 05:20:07 +00:00
nullhw-layer build: pass licensing information in SPDX form 2024-06-29 12:42:49 -07:00
perf anv: Protect memcpy/memset/qsort calls against NULL arguments 2024-11-14 01:05:01 +00:00
shaders anv: implement Wa_16011107343/22018402687 for generated draws 2024-11-12 22:48:39 +00:00
tools intel/hang_replay: remove EXEC_OBJECT_WRITE 2024-10-04 21:37:41 +00:00
vulkan anv: remove unused/misleading/wrong parameters from the RT trampoline 2024-11-14 19:23:42 -08:00
vulkan_hasvk anv,hasvk,genxml: Rename genxml files using verx10 2024-11-09 00:04:47 +00:00
meson.build intel: Add executor tool 2024-08-14 03:03:46 +00:00